JPS63163674A - Compound arithmetic circuit - Google Patents

Abstract

PURPOSE:To simplify the scale of a circuit by providing three selectors, selecting each selector, and omitting a multiplier. CONSTITUTION:ALU 30-37 which respectively associate with bits b0-b7 showing a coefficient alpha supplied from a memory (MEM) 1 through a bus bar 2 and form a computer element (ALU) array 3 are provided. The first and the second selectors (SEL) 40-47 and 50-57 are provided at first and second input joints of every ALU 30-37 and these selectors select the real numbers X1-X7 of and Y1-Y7 of them at an accumulation time and at an estimation time, they select the associated bits among accumulation values A from a bus bar 6 and the bits b0-b7 which show the coefficience alpha given from the bus bar 2 and input to each ALU 30-37. Thus the accumulation and the multiplication are executed in the same circuit, and the multiplier is not needed to provide.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a complex arithmetic circuit mainly used for pattern matching processing of characters, figures, etc.

[Conventional technology]

In pattern matching processing of characters, figures, etc., a predetermined arithmetic operation is performed on each element of vector data, the calculated value is accumulated, and then this accumulated value is multiplied by a coefficient. This operation is expressed by the following equation, where Xi and Yi are the first and second real numbers representing each element, @ is an arbitrary arithmetic operation, and α is a similar coefficient.

α・Σ(xl@yt)・・・・・・・・・ (1) Also, to perform the calculation of equation (1), it is common to use a digital signal processor (hereinafter referred to as DSP). For example, the details of DSP are disclosed in "Nikkei Electronics J August 25, 1986 issue No. 402, pages 183-220 (published by Nikkei McGraw-Hill)." In other words, when using DSP, Each real number x5yt is given to the arithmetic unit, a predetermined arithmetic operation is performed, and the calculated value is sequentially accumulated in a register and given to the arithmetic unit again. The value is given to the multiplier, which multiplies the coefficients.

However, in the above configuration, after giving real numbers Xi and Yl,! It takes two cycles to calculate A, which reduces the calculation speed, so different real numbers Xi, Yi~Xi+n, Yi+
An arithmetic unit is provided for each n, and an accumulator for accumulating each of these outputs is provided consisting of an adder and a register, and -
It is conceivable to calculate the cumulative value at the same time and separately perform multiplication by a coefficient.

[Problem that the invention seeks to solve]

However, even when an accumulator is used, a separate multiplier is required, which makes the circuit scale more complex than that of an adder, resulting in an overall high cost. Means for Solving the Problem] In order to solve the above-mentioned problem, the present invention is constructed by the following means.

That is, in the operation circuit that performs a predetermined arithmetic operation on the first and second real numbers, accumulates the calculated value, and multiplies the calculated value by a coefficient, each bit indicating the coefficient corresponds to an arithmetic unit for each bit a, and an arithmetic unit that selects a different first real number at the time of accumulation, selects the accumulated value at the time of multiplication, and supplies it to the first input of each arithmetic unit. and a second selector provided for each of these arithmetic units, which selects different second real numbers during accumulation, selects corresponding bits of coefficients during multiplication, and supplies them to the second input of each arithmetic unit. selector, and the outputs of each adjacent arithmetic unit from the least significant bit in each operation are added pair by pair, and these added values are sequentially added pair by pair from the least significant bit side. Finally, there is a group of adders arranged in multiple stages in a dendritic form that obtains the total addition value. Multiple shift registers that shift the given input to the most significant bit side, select a bypass route through each shift register during accumulation, select the output of each shift register during multiplication, and select the input of the corresponding adder. The third selector is provided for each shift register, and a storage means is provided for storing all the added values of the adder group and providing the stored contents as an accumulated value to each arithmetic unit at the time of multiplication.

[Effect]

Therefore, depending on the selection of each selector, each arithmetic unit and adder group is not shared for accumulation and multiplication, and all operations in equation (1) are performed using the same circuit, so multiplication is performed separately. The need for a container is eliminated.

〔Example〕

Hereinafter, the present invention will be explained in detail with reference to figures showing examples.

FIG. 1 is a block diagram showing the entire configuration.
ALU030-3 are provided to form the ALU array 3, and the first and second inputs on the left and right sides of the figure are connected to the first and second inputs for each ALU3o-3, respectively. 2 selector (hereinafter referred to as 5EL) 40-17.50~5
7), which when accumulated are first and second real numbers
-X7, Y1 to Yth are selected, and at the time of integration, select the corresponding bits in ALU3o to Bγ indicating the accumulated value A consisting of, for example, 16 bits from bus line 6 and the coefficient α from bus line 2. It is given to each of the 37 inputs.

In addition, each output of each ALU 30 to 3T is given to an ADD array 9 that constitutes a timing matching register (hereinafter referred to as REG) 80 to 8.
914 to the DD 911, each adjacent ALU 30-3 from the least significant bit ALU 30 among ALUso~37
The outputs of 1.32.3B, 3;, 35.36, and 37 are added pair by pair, and each of these added values is sequentially added pair by pair from ADD9 t t on the lower bit side, adjacent to each other.
D9zx, added by 922.931, ADD 9
The total addition value is finally obtained as the output of 31.

In addition, the upper bit side input of each ADD 911 to 931, that is, the input on the right side of the figure, is provided with REG 81 according to the number of stages to which λDDs 91t to 931 belong and the corresponding bit position.
,8s,83,8? A shift register (hereinafter referred to as
5RG) 1011-1014.10 to 1021, 102
31 is inserted into each individual, and these and each ADD9
Between 1t and 9st, each ADD 9t 1 to 93
Corresponding to 1, the third 5EL1111 to 1114, N21
, IH2, 1131 is provided, REG8 is set during accumulation.
1. Select each output of 83, 85, 8, 5RG1G1
1 to 1031 is selected, and at the time of integration, each output of 5RGIOII to 1031 is selected and given to the input of the corresponding ADD911 to 931'), and the output of ADD93t is used as a storage means. FLEG
12, and is then stored via the bus 6 in the MEM13, which is also provided as a storage means, or directly provided as the accumulated value A to the ALUs 30 to 37 via the bus 6. .

On the other hand, for these, a processor (hereinafter referred to as CPU) '14 such as a microprocessor is installed. It is assumed that the operation is performed normally.

Therefore, each 5EL40~47.50~57.111
1 to 1131 are in the state of selecting the input on the left side of the diagram, giving each real number Xo to X7, YO to Y7, and ALU3
By performing a predetermined arithmetic operation on ゜~37,
The cumulative value of Σ(xt@yt) is accumulated in the EG12.

Next, give the contents of REG12 to 5EL4o to 47 as an accumulated value consisting of Io-By parallel data,
Alternatively, store it in MEMl3 and then read it to give it in the same way, and also give the coefficient α of MEMl by p)bo~
b? While giving to 5EL5o~57 every time, 5EL40~
47.50 to 57.10 to 1Q31 are selected as the inputs on the right side of the diagram, ALUs 30 to 37 are made to perform logical addition, and 5RGIOII to 1031 are each given a predetermined number of bits on the most significant bit side. When the shift is performed, an operation is performed in which the accumulated value A is multiplied by a coefficient α, and this result is stored in the REG 12.

That is, A is 8 bits from &0 to a7, and α is bo to b7.
8 bits, and when their product P is composed of 16 bits, the multiplication algorithm is as shown in the following table.
Pl is determined by ALU s s, PP2 is determined by ALU32, PP3 is determined by ALU33, and thereafter PP4
~PPy is determined individually by the ALUs 34 to 37, so in the first stage 5RG1011 to 1014, 5RGI
OII moves 1 bit to the most significant bit (hereinafter referred to as MSB),
3RG1Qxz 3 bits to MSB side, 5RG10x3
is 5 bits to the MSB side, 5RG1014 is 7 bits to the MSB side
In addition to individually shifting the bits, the second stage 5RG
1 (In 1! If the shift is performed according to the corresponding bit position, the integrated value P can be obtained as the sum of the bit products PG-P15 forming the portion ytppo-PP7.

On the other hand, A1α is a two's complement of 8 bits each, and P is 16
When it is assumed that it is a two's complement number based on bits and that A%B includes a negative number, A% α is expressed by the following equation.

A=-a72 +a62 +aS2 + ++m4 HatakeQ
2 +m+ t2) α=-by2 +b62 +bs
2+・・−・−・・+b02 ・・−・・・(3) Also, the multiplication algorithm in this case is shown in the table below. When extracted, the first line of
``Computer high-speed calculation method J Kal Hwang
Author, translated by Hisashi Horikoshi, pages 180-185, Showa 5
If you transform the equation according to the following (September 1, 2005, Published by Kindai Kagakusha), you will get the following formula.The second line can be transformed in the same way, so what shows these becomes the part ■. .

(-a7M2'-m)bs2'-4yb42' --
-a7b02°)φ27=(a7Ta2'-)-ayb
sf ←Tof'F;a 2'-1-・-・・--・
-←To17b02゜1γ・(2'+2'+244-...
......+2°)・27=(ayba2'-ht
bs2'-1,tb42,4+-・---)s7b02
゜17・(2-1))・27 = (a7b@26-f-@7bs2'-)-@t-2'
-f-=・”...+a 7b02゜ia2'-2'-
h? )・27 In this case, PI3 is a digit indicating the sign, and the “-1” of Pig can be omitted by ignoring the carry from now on (, P=A・α is shown in Table 2). As shown in (2), it can be obtained only by adding positive numbers and shifting to the MSB side.

FIG. 2 is a block diagram for realizing the above-mentioned functions. Since it is only necessary to add the function of calculating the partial product PPm shown in Table 2 to the configuration shown in FIG.
, and add ADD9ot, ALU311 Hebitsu)
&7,b? and ALU via REG8B
The process is the same as in Figure 1 except that the output of 8s and the output via REG8y of ALU37 are added by ADD901, and thereby the integrated value P in Table 2 becomes REG12.
Accumulated by

Depending on the conditions, a REG for timing alignment may be inserted between the MEMI 13 and the bus 2.6, or REGs 8o to 88 may be omitted. , and the number of stages of the ADD group 9.

Furthermore, if the ALU3o to 38 have addition and shift functions, the logical product is calculated on the input side of these, and the ALU3o
- 38 may be a part of the ADD group 9, or only one of the REG 12 and the MEM 13, and many other modifications are possible.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, accumulation and multiplication are performed by the same circuit, there is no need to provide a multiplier, and the structure is simplified and the cost is reduced.
Remarkable effects can be obtained in various applications in which arithmetic operations including accumulation and operations in which an accumulated value is multiplied by a coefficient are performed.

[Brief explanation of the drawing]

The figures show an embodiment of the present invention, with FIG. 1 being a block diagram of the entire configuration, and FIG. 2 being a block diagram showing another embodiment. 3036...ALU (operating unit), 40 to 4γ, 5
0~57.1111~1131 ・Work...5EL (selector), 9...ADD group (adder group), 911~9
31...-ADD (adder), 1011 to 1031.
...5RG (shift register), 12.e..REG
(register), 13...Fist MEM (memory), Xo-
Xt, YO-Yy @ @ @ Real number.

Claims (1)

[Claims] In an arithmetic circuit that performs a predetermined arithmetic operation on the first and second real numbers, accumulates the calculated value, and multiplies the accumulated value by a coefficient, an arithmetic circuit is provided corresponding to each bit indicating the coefficient. Each of the arithmetic units for each bit and each arithmetic unit that selects a different first real number at the time of the accumulation, selects the accumulated value at the time of the multiplication, and supplies it to the first input of each of the arithmetic units. a first selector provided; and a first selector that selects the second real numbers, which are different during the accumulation, selects a corresponding bit of the coefficient during the multiplication, and supplies the selected bits to the second inputs of the respective arithmetic units. A second selector provided at A group of adders arranged in multiple stages in a dendritic manner that sequentially adds each pair to obtain a final total addition value, and the number of stages to which the adder belongs and the correspondence that is inserted into the upper bit side input of each adder. A plurality of shift registers that shift a given input to the most significant bit side according to the bit position to be processed, a route that bypasses each of the shift registers during the accumulation, and an output of each of the shift registers during the multiplication are selected. A third selector provided for each of the shift registers selected and applied to the input of the corresponding adder, and a third selector provided for each of the shift registers, and storing all added values of the adder group, and transmitting the stored contents as the accumulated value at the time of the multiplication to each arithmetic unit. 1. A complex arithmetic circuit comprising: a storage means for storing data.