JPS6316355A - Data transfer control system - Google Patents

Abstract

PURPOSE:To secure the quick and accurate transfer of data even in case a data transfer request other than that of an N-byte boundary is produced, by providing a bus managing circuit which decides the communication between an N-byte converting circuit and a common bus or a bus for input/output device. CONSTITUTION:When data are transferred to a bus 7 for input/output device from a common bus 8, an N-byte converting circuit 1 is initialized and the transfer of data is finished when the bus managing circuit 4 receives an end signal from a processor 10 even though the circuit 1 is not kept under an N-byte boundary state. In the same way, the data stored in the circuit 1 are transferred to the bus 8 to finish the transfer of data when the circuit 4 receives an end signal from the processor 10 even though the circuit 1 is not kept under an N-byte boundary state when data are transferred to the bus 8 from the bus 7.

Description

[Detailed Description of the Invention] [Summary] In a data transfer control method that employs a multi-byte burst transfer method, an N-byte conversion circuit transfers data via a common bus or transfers data via an input/output device bus. A bus management circuit is provided to control what is to be done.

[Industrial application field]

The present invention relates to an improvement in a data transfer control method that employs a multi-byte burst transfer method.

[Conventional technology]

In systems using microprocessor sensors, there has recently been a trend to connect input/output devices that require high-speed data transfer, such as fixed disks and magnetic tapes.

In such cases, it is common to perform multi-byte burst transfer to reduce the bus load of data transfer.

Multi-byte burst transfer is a method of transferring data at high speed.After accessing the bus, multiple (N)
This method transfers bytes of serial data all at once.

As is well known, when transferring data, bus arbitration (processing of connecting to or disconnecting from the bus) is performed, but since this bus arbitration takes a considerable amount of time, this bus arbitration is not necessary. A multi-byte burst transfer method has been adopted to reduce the number of transfers and increase transfer efficiency.

[Problem that the invention seeks to solve]

However, in the conventional multi-byte burst transfer method,
Transfer starts when a specified plurality of bytes (N bytes) of data are collected, so if N bytes are not collected, the transfer will not start and will stop in a data waiting state.

FIG. 3 is a diagram showing an example of a conventional data transfer control method.

In the figure, 1 is an N-byte conversion circuit, 2 is a data transfer counter, 3 is a message notification circuit, 5 is an input/output device, 6 is a data bus, 7 is a data bus for input/output devices, 8 is a common bus, and 9 is main memory The device 10 is a processor.

N byte conversion circuit 1 converts N bytes into byte units,
Alternatively, it converts 1-byte data into N-byte data and controls the data flow.

The data transfer counter 2 specifies the number of data transfers to the input/output device 5 and notifies the input/output device 5 of the number of data transfers.

The message notification circuit 3 notifies the processor 10 of a termination message (including error signals, etc.) from the input/output device 5.

Note that data is transferred in units of N bytes on the data bus 6 and common bus 8, and data for input/output devices is transferred in units of 1 byte in the input/output device data.

When transferring data from the main storage device 9 to the input/output bag N5,
When data transfer is permitted by the processor 10, N-byte data in the storage device 9 is sent to the N-byte conversion circuit 1 via the common bus 8 and the data bus 6, and is stored therein.

Next, the N-byte conversion circuit 1 transfers data one byte at a time to the input/output device 5 via the input/output device data bus 7. When the input/output device 5 receives this 1-byte data, it returns a transfer request ■.

In response to this request, the N-byte conversion circuit 1 transfers the next 1 byte of data. Transfer is performed N times in this manner, and when all accumulated data has been transferred, a transfer request (3) is issued to the processor 10.

Based on this transfer request (2), the next N bytes of data are sent from the main storage device 9 to the N byte conversion circuit 1.

Although data is transferred sequentially in this manner, the data finally sent from the main memory device 9 to the N-byte conversion circuit 1 is not necessarily N-bytes.

In this state, the N-byte conversion circuit 1 enters a data waiting state and stops data transfer. In order to avoid this, conventional processing has been carried out to predefine the number of data transfers to a value divisible by N bytes (referred to as an N-byte boundary).

When the input/output device 5 receives a predetermined number of data in this way, it sends the end signal ■ to the message notification circuit 3, and the message notification circuit 3 reports this to the processor 10. moves on to other processing.

As you can see from the above explanation, if it is not an N byte boundary, then N
The byte conversion circuit 1 has a disadvantage in that it continues to wait for data.

There is a method that monitors the time interval of data transfer and assumes that the data transfer has ended if the next data transfer does not occur after a certain period of time, but the time interval of data transfer is guaranteed. This method cannot necessarily be used for data transfer with input/output devices that cannot be used.

An object of the present invention is to provide a multi-byte burst transfer method that can reliably transfer data even when not in an N-byte boundary state.

[Means for solving problems]

The above problem can be solved by the processor 10 as shown in the principle diagram in Figure 1.
An N-byte conversion circuit 1 is provided between the common bus 8 connected to the input/output device bus 7 and the input/output device bus 7, which converts and inversely converts transfer data into N-byte units.
In the burst transfer method, this problem is solved by providing a bus management circuit 4 that controls whether the N-byte conversion circuit 1 communicates with the common bus 8 side or the input/output device bus 7 side.

[Effect]

According to the present invention, from the common bus 8 side to the input/output device bus 7
When data is transferred to the side, even when the N-byte conversion circuit 1 is not in the N-byte boundary state, when the bus management circuit 4 receives an end signal from the processor 10, the N-byte conversion circuit 5 is initialized to end the data transfer.

Similarly, when data is transferred from the input/output device bus 7 side to the common bus 8 side, even if the N-byte conversion circuit 1 is not in the N-byte boundary state, when the bus management circuit 4 receives the end signal from the processor 10, the N-byte conversion is performed. The data stored in the circuit 1 is transferred to the common bus 8 side and the process is completed.

〔Example〕

In the present invention, when a data transfer request other than the N-byte boundary occurs, the data transfer request is temporarily stopped at the data limit, but at the same time a termination message is received, so the bus management uses this as a trigger to forcefully compensate for the data limit. The circuit is accessed and the data transfer is stopped due to the apparent upper N-byte boundary.

FIG. 2 is a diagram showing an embodiment of the data transfer control method according to the present invention.

In the figure, 4 is a bus management circuit.

(A) First, the case of data transfer from the main storage device 9 to the input/output device 5 will be described.

First, the bus management circuit 4 instructs the N-byte conversion circuit 1 to take a state in which it communicates with the common bus 8 side.

When data transfer is permitted by the processor 10, N-byte data is stored in the N-byte conversion circuit 1 via the common bus 8 and the data bus 6.

At this time, the bus management circuit 4 instructs the N-byte conversion circuit 1 to communicate with the input/output device data bus 7 side.

Next, the N-byte conversion circuit 1 transfers 1 byte of data to the input/output device 5 via the input/output device data bus 7. When the input/output device 5 receives this 1-byte data,
Returns transfer request ■. In response to this request, the N-byte conversion circuit 1 transfers the next 1 byte of data. Transfer is performed N times in this manner.

When the N-byte conversion circuit 1 has finished transferring all the accumulated data, it issues a transfer request (■) to the processor 10, and based on this transfer request (■), the next N-byte data is transferred from the main storage device 9 to the N-byte conversion circuit 1. sent to. In this way, data is transferred sequentially as in the conventional method.

The data finally sent from the main memory device 9 to the N-byte conversion circuit 1 is not necessarily N-bytes.

Assume that the number of bytes of data currently stored in the N-byte conversion circuit 1 is Nl (N>Nl).

In this case, when the N-byte conversion circuit 1 transfers data of 1 byte each N times, it does not issue a transfer request ■ as in the case of the conventional method, but the end signal ■ is sent as a message from the input/output device 5. It is transmitted to the notification circuit 3.

The message notification circuit 3 reports this to the processor 10, and based on this report, the processor 10 checks the value of the data transfer counter 2 and finds that the number of transfers from the N byte conversion circuit 1 to the input/output device 5 is N1. I understand.

Therefore, the processor 10 issues an end signal to the bus management circuit 4, and initializes the N-byte conversion circuit 1 with the output signal 2 of the bus management circuit 4. At this time, the N-byte conversion circuit 1 is again able to communicate with the common bus 8 side, and the transfer ends.

(B) Next, the case of data transfer from the input/output device 5 to the main storage device 9 will be described.

When a data transfer request is issued from the input/output device 5, the bus management circuit 4 instructs the N-byte conversion circuit 1 to become ready for communication with the data bus 7 side.

When each Hide is transferred N times from the input/output device 5 and stored in the N-byte conversion circuit 1, the N-byte conversion circuit 1 transfers the N-byte data to the main storage device 9 via the data bus 6 and the common bus 8. .

When the process is completed, the bus management circuit 4 makes the N-byte conversion circuit 1 ready to communicate with the data bus 7 side again.

By repeating such operations, the required number of data is transferred to the main storage device 9.

Similarly, in the end, N2 bytes, which are less than N bytes, are stored in the N-hide conversion circuit 1, and data is not transferred from the N-byte conversion circuit 1 to the main storage device 9 due to the insufficient number of bytes.
The N-byte conversion circuit 1 faces the data bus 7 side and stops at 7S.

However, since the end signal ■ is output from the input/output device 5 to the message notification circuit 3, the processor 10 similarly checks the value of the data transfer counter 2 and finds that the number of transfers from the N byte conversion circuit 1 to the input/output device 5 is N2 times. I understand that.

Therefore, the processor 10 sends an end signal to the bus management circuit 4, and the bus management circuit 4 puts the N-byte conversion circuit 1 in a state where it can communicate with the common bus 8 side, and transfers the N2 bytes stored in the N-byte conversion circuit 1 to the main memory. Transfer to device 9 and end.

It is assumed that the N-byte conversion circuit 1 in the state where the data transfer has been completed is in a state where it can communicate with the common bus 8 side.

〔Effect of the invention〕

As described above in detail, the present invention has the great effect that data can be transferred accurately and quickly even when a data transfer request other than the N-byte boundary occurs.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle of the present invention. FIG. 2 is a diagram showing an embodiment of the data transfer side jl'J according to the present invention. FIG. 3 is a diagram showing an example of a conventional data transfer control method. In the figure, 1 is an N-byte conversion circuit, 2 is a data transfer counter, 3 is a message notification circuit, 4 is a bus management circuit, 5 is an input/output device, 6 is a data bus, 7 is a data bus for input/output devices, and 8 is a data bus for input/output devices. A common bus, 9 a main memory, and 10 a processor. Fig. 1 An embodiment of the data transfer control method according to the present invention Fig. 2 Fig. 3

Claims (1)

[Claims] A common bus (8) connected to a processor (10)
An N-byte conversion circuit (1) that converts and inversely converts transfer data into N-byte units is installed between the I/O device bus (7) and the multi-byte converter for data transfer.
In the burst transfer method, a bus management circuit that controls whether the N-byte conversion circuit (1) transfers data to the common bus (8) side or to the input/output device bus (7) side. (4) is provided, and when the N-byte conversion circuit (1) is not in the N-byte boundary state, the bus management circuit (4) that has received the end signal from the processor (10) via the common bus (8) A data transfer control method characterized by initializing an N-byte conversion circuit (1) or causing the N-byte conversion circuit (1) to send out remaining data.