JPS631633B2 - - Google Patents

Info

Publication number
JPS631633B2
JPS631633B2 JP57083632A JP8363282A JPS631633B2 JP S631633 B2 JPS631633 B2 JP S631633B2 JP 57083632 A JP57083632 A JP 57083632A JP 8363282 A JP8363282 A JP 8363282A JP S631633 B2 JPS631633 B2 JP S631633B2
Authority
JP
Japan
Prior art keywords
processor
mode
data transfer
load
transfer device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57083632A
Other languages
English (en)
Japanese (ja)
Other versions
JPS58200366A (ja
Inventor
Tadashi Naruse
Masato Amamya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP57083632A priority Critical patent/JPS58200366A/ja
Publication of JPS58200366A publication Critical patent/JPS58200366A/ja
Publication of JPS631633B2 publication Critical patent/JPS631633B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/177—Initialisation or configuration control

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
JP57083632A 1982-05-18 1982-05-18 デ−タ転送方式 Granted JPS58200366A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57083632A JPS58200366A (ja) 1982-05-18 1982-05-18 デ−タ転送方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57083632A JPS58200366A (ja) 1982-05-18 1982-05-18 デ−タ転送方式

Publications (2)

Publication Number Publication Date
JPS58200366A JPS58200366A (ja) 1983-11-21
JPS631633B2 true JPS631633B2 (US07541385-20090602-C00001.png) 1988-01-13

Family

ID=13807836

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57083632A Granted JPS58200366A (ja) 1982-05-18 1982-05-18 デ−タ転送方式

Country Status (1)

Country Link
JP (1) JPS58200366A (US07541385-20090602-C00001.png)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6227856A (ja) * 1985-07-30 1987-02-05 Agency Of Ind Science & Technol 負荷分散装置
WO2009131007A1 (ja) * 2008-04-22 2009-10-29 日本電気株式会社 Ｓｉｍｄ型並列計算機システム、ｓｉｍｄ型並列計算方法及び制御プログラム

Also Published As

Publication number Publication date
JPS58200366A (ja) 1983-11-21

Similar Documents

Publication Publication Date Title
Kitsuregawa et al. Bucket Spreading Parallel Hash: A New, Robust, Parallel Hash Join Method for Data Skew in the Super Database Computer (SDC).
JP2682770B2 (ja) 仮想計算機システムのｃｐｕ制御方式
KR102539571B1 (ko) 네트워크 온칩 데이터 처리 방법 및 장치
KR102539572B1 (ko) 네트워크 온칩 데이터 처리 방법 및 장치
JPS631633B2 (US07541385-20090602-C00001.png)
KR102539573B1 (ko) 네트워크 온칩 데이터 처리 방법 및 장치
Tuomenoksa et al. Task scheduling on the PASM parallel processing system
Suel Routing and sorting on meshes with row and column buses
KR102539574B1 (ko) 네트워크 온칩 데이터 처리 방법 및 장치
Dongarra et al. Revisiting matrix product on master-worker platforms
Wah et al. Distributed scheduling of resources on interconnection networks
JPH0612395A (ja) マルチプロセサシステムにおけるタスク割り付け方法
JPS6131904B2 (US07541385-20090602-C00001.png)
JPS63223860A (ja) 複数プロセツサ構成装置
Tuomenoksa et al. Analysis of multiple-queue task scheduling algorithms for multiple-SIMD machines.
JPS6227856A (ja) 負荷分散装置
Monien et al. A realizable efficient parallel architecture
Juang et al. Resource sharing interconnection networks in multiprocessors
JPH08185384A (ja) ロードモジュール割り当て方法および割り当て装置
JPH1063607A (ja) Ｄｍａコントローラ
Davis IV et al. The performance analysis of partitioned circuit switched multistage interconnection networks
Keshk et al. Amon: A parallel slice algorithm for wire routing
JPS61279959A (ja) 主記憶退避出力方式
JP2000010934A (ja) マルチｃｐｕシステムのバス調停システム
Nandy Geometric Design Rule Check of VLSI Layouts in Distributed Computing Environment