JPS63163175A - Peak value holding circuit - Google Patents

Abstract

PURPOSE:To achieve a reduction in holding errors due to the discharge of a peak holding valtage, by breaking a first switch for charging a peak value holding capacitor based on a peak value holding output voltage. CONSTITUTION:With the inputting of a signal at an input terminal 30, a potential difference thereof from, a peak value holding output terminal 31 reaches a level more than enough to conduct a Tr1, the Tr1 as first switch is made to conduct. A Tr2 and a Tr3 composes a current switch and current of a current of current source 9 is switches over to the Tr2 or Tr3 s second switch according to a potential difference between a voltage obtained by level shifting of a voltage at a peak value holding output terminal 31 with a Tr12, a diode 13 and a resistance 14 and a voltage obtained by level shifting of an input signal voltage of the input terminal 30 with a Tr4 and diodes 5 and 6. A current source 10 feeds a bias current to the Tr4 and the diodes 5 and 6 while a current source 15 feeds a bias current to the Tr12, the diode 13 and the resistance 14. A capacitor 8 is connected to a terminal 31 and the Tr1 is charged during the conduction to hold a peak value.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a peak value holding circuit.

[Conventional technology]

FIG. 4 shows six examples of conventional peak value holding circuits.

This restored example has a power supply 11, a signal is input to an input terminal 30, and the voltage between the base and emitter is such that the potential difference between the input terminal 30 and the peak value holding output terminal 31 is sufficient for the transistor 1 to conduct. When the voltage is higher than that, transistor 1 becomes conductive.

Transistor 2 and transistor 3 are transistor 3
A current switch is configured to switch the current of the current source 9 to the transistor 2 or the transistor 3 based on the potential difference between the voltage of the reference voltage source 7 connected to the base of the transistor 2 and the base voltage of the transistor 2.

Transistor 4, diode 5 and diode 6 level shift the input signal voltage to a voltage that the current switch of transistor 2.3 can compare with reference voltage source 7. The current source 10 includes a transistor 4, a diode 5, and a diode 6.
It is used to pass a bias current through. The capacitor 8 is connected to the peak value holding output terminal 31, and is charged by the current from the transistor 1 when the transistor 1 becomes conductive, and holds the peak value.

FIG. 5 shows waveforms at various parts in FIG. The input signal of the input terminal 30 is transmitted to the transistor 4. The pace voltage of the transistor 2 level-shifted by the diode 5 and the diode 6 is shown in waveform S5, and the voltage of the reference voltage source 7 is shown in the waveform S5.
The peak value holding output terminal 31 is shown in waveform S6 on the same voltage axis as
The output waveform of is shown in waveform S7, and the collector current waveform of transistor 2 is shown in waveform S8.

The operation of the conventional peak value holding circuit will be explained using FIGS. 4 and 5. At time T5 in FIG. 5, the input signal voltage at the input terminal 30 becomes higher than the voltage at the peak value holding output terminal 31, the transistor 1 becomes conductive, and the content v8 is charged in proportion to the input signal voltage. . Charging of content +j8 is completed at time T5 in FIG.
At 6, the transistor 1 becomes non-conductive, and the charge stored in the content +j8 is discharged as the collector current of the transistor 2.

Let the impedance seen from the emitter of transistor 1 when it is off be "5offs", the impedance seen from the collector of transistor 2 when it is on be R'con, the capacitance of capacitor 8 be C, and both ends of capacitor 8 charged at time T5. The peak value of the voltage is Vp-.

Then, the transient response of the voltage across content v8 ■T6
is expressed by equation (1) as an exponential function of time t.At time T7, transistors 1 and 2 are in a non-conducting state, and Rcoff is the impedance seen from the collector of transistor 2 when it is non-conducting. If the voltage across content+j8 up to time T6 is 6, then the transient response VT7 of the voltage across content+j8 is expressed by equation (2).

At time T8, transistor 1 is in a non-conducting state and transistor 2 is in a non-conducting state.If the voltage across content +j8 up to time T7 is v7, content +j8
The transient response of the voltage across the terminal ■T8 is the equation (1) of the time T6
It is expressed by an exponential function equation (3) with an exp term equal to .

Equations (1), (2), and (3) represent discharge, but the impedance seen from the collector of the transistor is usually R6on when conducting is several tens of Ω to several hundreds Ω, and R6off when non-conducting is from several tens of Ω to several hundreds of Ω, and the relationship shown in equation (4) holds true.

Rcoff':> Rcon・
......(4) Equation (41, Equation (1) 1 Equation (
2) and the exp term in equation (3) have the relationship shown in equation (5).

Rsoff // Rcon-C<< Rsoff /
'Rcoff・C・・・・・・・・・(5) From equation (5), equation + 11, equation (2) and equation (3) are transformed into equation (
6).

VT6 + VT8) VT7...
(6) In other words, the amount of charge charged in content v8 during time T5 is dominated by the amount discharged at time T6 and time T8 compared to the amount discharged at time T7. be.

[Problem that the invention seeks to solve]

In the above-mentioned conventional peak value holding circuit, since the electric charge charged in the capacitor 8 at time T5 makes the transistor 2 conductive at time T6 and time T8, equations (1) and (3) are satisfied.
The disadvantage is that the discharge occurs according to an exponential function shown by , and the peak value holding error is large.

In contrast to the above-described conventional peak value holding circuit, the present invention uses the peak value holding output as a reference voltage to shorten the period of time that is dominant for discharge and reduce holding errors due to discharge during peak value holding. It has original content.

[Means for solving problems]

The peak value holding circuit of the present invention includes a capacitor for holding the peak value of an input signal, and a first switch that charges the capacitor when the potential of the input signal is higher than the potential of one electrode of the capacitor. , a second switch that shuts off the first switch when the potential of one electrode of the capacitor is higher than the potential of the input signal, and obtaining a peak value holding output from the one electrode of the capacitor. Features.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit connection diagram of a first embodiment of the present invention. Components that are the same as in FIG. 4 are given the same reference numerals.

When a signal is input to the input terminal 30 and the potential difference between the input terminal 30 and the peak value holding output terminal 31 exceeds the base-emitter voltage sufficient to make the transistor 1 conductive, the transistor that is the first switch 1 is conductive. The transistor 2 and the transistor 3 constitute a current switch, and the voltage of the peak value holding output terminal 31 is transferred to the transistor 12,
The current of the current source 9 is changed to the second voltage by the potential difference between the voltage level-shifted by the diode 13 and the resistor 14 and the voltage level-shifted by the transistor 4, the diode 5, and the diode 6.
The switch is switched to transistor 2 or transistor 3. A current source 10 causes a bias current to flow through the transistor 4, the diode 5, and the diode 6, and the current source 15
For example, the transistor 12, the diode 13, and the resistor 14 are provided with a bias current to flow therein. The capacitor '+j8 is connected to the peak value holding output terminal 31, and is charged when the transistor 1 is conductive to hold the peak value.

FIG. 2 shows waveforms at various parts in FIG. 1. The waveform S1 shows the base voltage waveform of the transistor 2 in which the input signal of the input terminal 30 is level-shifted by the transistor 4, the diode 5, and the diode 6, and the peak value holding output waveform is level-shifted by the transistor 12, the diode 13, and the resistor 14. The shifted transistor 30 base voltage waveform is shown in waveform S2 along the same voltage axis as waveform S1. The base voltage of the transistor 3 shown by the waveform S2 is adjusted by the resistor 14 so that the voltage difference between the base voltage of the transistor 2 and the base voltage of the transistor 2 shown by the waveform S1 becomes sufficient to make the transistor 2 conductive. Waveform S3 shows the output waveform of the peak value holding output terminal 31, and waveform S3 shows the collector current waveform of transistor 2.
4.

Time TI, time T2 in FIG. The transient response of the voltage across the capacitor 8 at time T3 and time T4 is as shown in FIG.
5. Time T6. It is expressed by an exponential function with an exp term equal to time T7 and time T8, respectively.

The difference between this embodiment and the conventional peak value holding circuit is that the reference voltage is a voltage obtained by level-shifting the peak value holding output voltage shown by waveform S3 in FIG. 2 to the voltage shown by waveform S2 in the same figure. By using this, the reference voltage follows the potential of the peak value holding output terminal 31 shown in FIG. As a result, the second
The times T2 and T4 in the figure are shorter than the times T6 and T8 in FIG. 5, and the amount of charge from the capacitor 8 in FIG. Holding errors due to discharge during peak value holding can be reduced.

FIG. 3 is a circuit connection diagram of a second embodiment of the present invention. The circuit configuration is such that the resistor 14 of the circuit shown in FIG. 1 of the first embodiment described above is replaced with a diode 16. In FIG. 2, the voltage of the peak value holding output terminal 31 is changed to the voltage of the transistor 12.
The level is shifted by diode 13 and diode 16, and the voltage is transferred to transistor 2. This is used as a reference voltage for a current switch constituted by a transistor 3 and a current source 9. The circuit operation is similar to that of the first embodiment shown in FIG. 1, and the effects that are different from the conventional peak value holding circuit are also the same as those of the first embodiment.

〔Effect of the invention〕

As described above, the present invention has the effect of reducing holding errors due to discharge during peak value holding by continuously opening and closing the first switch based on the peak value holding output voltage.

[Brief explanation of the drawing]

1 and 2 are a circuit connection diagram and a waveform diagram of a first embodiment of the peak value holding circuit of the present invention, respectively, and FIG. 3 is a circuit connection diagram of a second embodiment of the present invention, and a fourth 5 and 5 are a circuit connection diagram and a waveform diagram of a conventional peak value holding circuit, respectively. 1 to 4...transistor, 5.6...diode,
7...Reference-power supply, 8...Capacitor, 9.10.
... Current source, 11... Power supply, 12... Transistor, 13... Diode, 14... Resistor, 15...
Current source, 16... diode, 30... input terminal,
31...Peak value holding output terminal. Agent Patent Attorney Susumu Uchihara −゛1st concave 1111−−−−−−−−−−−−−−−−−111−−−−−−→−1 4 Figure 5 Figure 5

Claims (1)

[Claims] a capacitor for holding the peak value of an input signal; a first switch that charges the capacitor when the potential of the input signal is higher than the potential of one electrode of the capacitor; A peak value holding circuit comprising a second switch that shuts off the first switch when the potential is higher than the potential of an input signal, and obtaining a peak value holding output from one electrode of the capacitor.