JPS63162520U

JPS63162520U -

Info

Publication number: JPS63162520U
Application number: JP5436587U
Authority: JP
Priority date: 1987-04-10
Filing date: 1987-04-10
Publication date: 1988-10-24

Description

[Brief explanation of the drawing]

第１図ａは本考案の第１の実施例を示すチツプ
型電子部品の斜視図、第１図ｂは同側断面図、第
２図ａは本考案の第２の実施例を示すチツプ型電
子部品の斜視図、第２図ｂは同側断面図、第３図
ａは本考案の第３の実施例を示すチツプ型電子部
品の斜視図、第３図ｂは同正面断面図、第４図ａ
，ｂおよび第５図は本考案のチツプ型電子部品を
得るための手段を示す概略図、第６図ａは従来の
チツプ型電子部品の斜視図、第６図ｂは同側断面
図、第７図は積層セラミツクコンデンサの電極を
塗布する前の斜視図、第８図は振動送り器による
チツプ型電子部品の搬送状態を示す模式図、第９
図はチツプ型電子部品を真空吸着でチヤツクする
状態を示す模式図である。１……素体、２……電極、２１……内部電極、
３１，３２，３３……（電極の）平坦部、４１，
４２……型、５１，５２……ローラ、６……振動
送り器、７……ベース、８……トラフ、９……ノ
ズル。 FIG. 1a is a perspective view of a chip-type electronic component showing a first embodiment of the present invention, FIG. 1b is a sectional view of the same side, and FIG. 2a is a chip-type electronic component showing a second embodiment of the present invention. FIG. 2b is a perspective view of the electronic component; FIG. 3a is a perspective view of a chip-type electronic component showing a third embodiment of the present invention; FIG. Figure 4a
, b and FIG. 5 are schematic diagrams showing means for obtaining a chip-type electronic component of the present invention, FIG. 6a is a perspective view of a conventional chip-type electronic component, FIG. 6b is a sectional view of the same side, and FIG. Figure 7 is a perspective view of a multilayer ceramic capacitor before electrodes are applied, Figure 8 is a schematic diagram showing the state of transport of chip-type electronic components by a vibration feeder, and Figure 9
The figure is a schematic diagram showing a state in which a chip-type electronic component is chucked by vacuum suction. 1... Elementary body, 2... Electrode, 21... Internal electrode,
31, 32, 33... (of the electrode) flat part, 41,
42...Mold, 51, 52...Roller, 6...Vibration feeder, 7...Base, 8...Trough, 9...Nozzle.

Claims

[Scope of utility model registration request]

Apply paste-like electrode material to the outer periphery of both ends,
1. A chip-type electronic component formed into an electrode by solidification treatment, characterized in that a flat portion is provided on at least the upper and lower surfaces of the electrode.