JPS63161457U - - Google Patents

Info

Publication number
JPS63161457U
JPS63161457U JP5247087U JP5247087U JPS63161457U JP S63161457 U JPS63161457 U JP S63161457U JP 5247087 U JP5247087 U JP 5247087U JP 5247087 U JP5247087 U JP 5247087U JP S63161457 U JPS63161457 U JP S63161457U
Authority
JP
Japan
Prior art keywords
digital
digital signal
analog
recording
reproducing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5247087U
Other languages
Japanese (ja)
Other versions
JPH0643900Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987052470U priority Critical patent/JPH0643900Y2/en
Priority to US07/177,616 priority patent/US4903025A/en
Publication of JPS63161457U publication Critical patent/JPS63161457U/ja
Application granted granted Critical
Publication of JPH0643900Y2 publication Critical patent/JPH0643900Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Signal Processing For Digital Recording And Reproducing (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図、第2図はそれぞれ本考案の実施例の構
成図、第3図、第4図、第5図は本考案の説明に
供する構成図をそれぞれ示す。 1……デジタル入力端子、2……DAIF復調
器、3……変調記録再生部、4……DAIF復調
器、5……デジタル出力端子、6……アナログ入
力端子、7……入力ボリウム、8……ローパスフ
イルタ、9……A/D変換部、10……D/A変
換部、11……アナログ出力端子、SW1〜SW
4……スイツチ、24……操作スイツチ部、25
……スイツチ制御回路。
FIGS. 1 and 2 are block diagrams of an embodiment of the present invention, and FIGS. 3, 4, and 5 are block diagrams for explaining the present invention, respectively. 1...Digital input terminal, 2...DAIF demodulator, 3...Modulation recording/reproducing section, 4...DAIF demodulator, 5...Digital output terminal, 6...Analog input terminal, 7...Input volume, 8 ...Low pass filter, 9...A/D converter, 10...D/A converter, 11...Analog output terminal, SW1 to SW
4...Switch, 24...Operation switch section, 25
...Switch control circuit.

補正 昭63.2.17 考案の名称を次のように補正する。 考案の名称 信号経路設定回路 実用新案登録請求の範囲を次のように補正する
Amendment February 17, 1983 The name of the invention is amended as follows. Title of the invention: Signal path setting circuit The scope of the claim for utility model registration is amended as follows.

【実用新案登録請求の範囲】 (1) 少なくとも第1のアナログ信号をA/D変
換するA/D変換手段と、 第1のデジタル信号と前記A/D変換手段から
出力される第2のデジタル信号のうち一方を選択
し、記録媒体を介してデジタル記録再生を行う記
録再生手段に前記選択したデジタル信号を出力す
る第1のスイツチ手段と、 前記記録再生手段から出力される第3のデジタ
ル信号と前記第1のデジタル信号のうち一方を選
択して出力する第2のスイツチ手段と、 該第2のスイツチ手段から出力される前記デジ
タル信号をD/A変換して第2のアナログ信号を
出力する
D/A変換手段を含むことを特徴とする
信号経路設定回路。 (2) 前記A/D変換手段は、前記第1のアナロ
グ信号と前記D/A変換手段から出力される前記
第2の
アナログ信号とのうち一方を選択する第3
のスイツチ手段を備え、選択されたアナログ信号
をA/D変換する
ことを特徴とする実用新案登録
請求の範囲第1項記載の信号経路設定回路。 図面の簡単な説明を次のように補正する。 明細書第20頁第14行目の「4……DAIF
復調器」の記載を「4……DAIF変調器」に補
正する。
[Claims for Utility Model Registration] (1) A/D conversion means for A/D converting at least a first analog signal, and a first digital signal and a second digital signal output from the A/D conversion means. a first switch means for selecting one of the signals and outputting the selected digital signal to a recording and reproducing means for performing digital recording and reproducing via a recording medium; and a third digital signal output from the recording and reproducing means. and a second switch means for selecting and outputting one of the first digital signals; D/A converting the digital signal output from the second switch means and outputting a second analog signal. It is characterized by including a D/A conversion means for
Signal routing circuit . (2) The A/D conversion means selects one of the first analog signal and the second analog signal output from the D/A conversion means.
2. The signal path setting circuit according to claim 1 , further comprising a switch means for A/D converting a selected analog signal . The brief description of the drawing has been amended as follows. “4...DAIF” on page 20, line 14 of the specification
The description of "Demodulator" is corrected to "4...DAIF modulator".

Claims (1)

【実用新案登録請求の範囲】 (1) 少なくともアナログ入力端子に入力するア
ナログ信号をA/D変換するA/D変換手段と、 デジタル入力端子を経由する第1のデジタル信
号と前記A/D変換手段から出力される第2のデ
ジタル信号のうち一方を選択し、記録媒体を介し
てデジタル記録再生を行う記録再生手段に前記選
択したデジタル信号を出力する第1のスイツチ手
段と、 前記記録再生手段から出力される第3のデジタ
ル信号と前記第1のデジタル信号のうち一方を選
択して出力する第2のスイツチ手段と、 該第2のスイツチ手段から出力される前記デジ
タル信号をD/A変換してアナログ出力端子に出
力するD/A変換手段を含むことを特徴とするデ
ジタルレコーダ。 (2) 前記A/D変換手段は、前記アナログ入力
端子に入力するアナログ信号と前記D/A変換器
から出力されるアナログ信号とのうち一方を選択
する第3のスイツチ手段を備えることを特徴とす
る実用新案登録請求の範囲第1項記載のデジタル
レコーダ。
[Claims for Utility Model Registration] (1) A/D conversion means for A/D converting at least an analog signal input to an analog input terminal, and a first digital signal via the digital input terminal and the A/D conversion. a first switch means that selects one of the second digital signals outputted from the means and outputs the selected digital signal to a recording and reproducing means that performs digital recording and reproducing via a recording medium; and the recording and reproducing means. a second switch means for selecting and outputting one of the third digital signal output from the second digital signal and the first digital signal; and D/A converting the digital signal output from the second switch means. A digital recorder comprising a D/A conversion means for outputting the digital signal to an analog output terminal. (2) The A/D conversion means includes third switch means for selecting one of the analog signal input to the analog input terminal and the analog signal output from the D/A converter. A digital recorder according to claim 1 of the utility model registration claim.
JP1987052470U 1987-04-07 1987-04-07 Signal path setting circuit Expired - Lifetime JPH0643900Y2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP1987052470U JPH0643900Y2 (en) 1987-04-07 1987-04-07 Signal path setting circuit
US07/177,616 US4903025A (en) 1987-04-07 1988-04-05 Signal path setting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987052470U JPH0643900Y2 (en) 1987-04-07 1987-04-07 Signal path setting circuit

Publications (2)

Publication Number Publication Date
JPS63161457U true JPS63161457U (en) 1988-10-21
JPH0643900Y2 JPH0643900Y2 (en) 1994-11-14

Family

ID=30877666

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987052470U Expired - Lifetime JPH0643900Y2 (en) 1987-04-07 1987-04-07 Signal path setting circuit

Country Status (1)

Country Link
JP (1) JPH0643900Y2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS601662A (en) * 1983-06-18 1985-01-07 Sony Corp Recording and reproducing device
JPS6224474A (en) * 1985-07-24 1987-02-02 Pioneer Electronic Corp Digital audio disc player

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS601662A (en) * 1983-06-18 1985-01-07 Sony Corp Recording and reproducing device
JPS6224474A (en) * 1985-07-24 1987-02-02 Pioneer Electronic Corp Digital audio disc player

Also Published As

Publication number Publication date
JPH0643900Y2 (en) 1994-11-14

Similar Documents

Publication Publication Date Title
JPH0220802U (en)
JPS63161457U (en)
JPH0254972B2 (en)
ES8708079A1 (en) PCM signal recording and/or reproducing apparatus.
JPH01124967U (en)
JPH0548295Y2 (en)
JPS5834439U (en) Digital-to-analog converter output error compensation circuit
JPS55101139A (en) Pcm-system signal recording and reproducing device
JPS6349659U (en)
JPS58141417U (en) Recording/playback device
JPH0381564U (en)
JPS58152042U (en) signal regeneration system
JPS6473563A (en) Compact disk player system
JPS601662A (en) Recording and reproducing device
JPS61202938U (en)
JPS58172340U (en) Switch with multiple operation parts
JPS6426800U (en)
JPS63196126U (en)
JPS6381538U (en)
JPH0148559B2 (en)
JPH025146U (en)
JPS5984975U (en) Noise reduction circuit for reproduced FM luminance signal
JPS6222765U (en)
JPH029825U (en)
JPH0323859U (en)