JPS63161456U - - Google Patents

Info

Publication number
JPS63161456U
JPS63161456U JP5388587U JP5388587U JPS63161456U JP S63161456 U JPS63161456 U JP S63161456U JP 5388587 U JP5388587 U JP 5388587U JP 5388587 U JP5388587 U JP 5388587U JP S63161456 U JPS63161456 U JP S63161456U
Authority
JP
Japan
Prior art keywords
signal transmission
power
recording
turned
time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5388587U
Other languages
Japanese (ja)
Other versions
JPH073497Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987053885U priority Critical patent/JPH073497Y2/en
Publication of JPS63161456U publication Critical patent/JPS63161456U/ja
Application granted granted Critical
Publication of JPH073497Y2 publication Critical patent/JPH073497Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Signal Processing Not Specific To The Method Of Recording And Reproducing (AREA)
  • Amplifiers (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の実施例に係わるテーブレコー
ダの一部を示す回路図、第2図は第1図の第1の
電圧安定化回路の一部を原理的に示す回路図、第
3図は第1図の各部の状態を示す波形図である。 6,7……整流回路、12,13……電圧安定
化回路、14……増幅器、15……伝送路、16
……ミユーテイングスイツチ、19……コイル、
20……トランジスタ、23……ミユーテイング
制御信号発生回路、24……出力電圧オン・オフ
制御信号発生回路。
Fig. 1 is a circuit diagram showing a part of a table recorder according to an embodiment of the present invention, Fig. 2 is a circuit diagram showing a part of the first voltage stabilizing circuit shown in Fig. 1 in principle, and Fig. 3 2 is a waveform diagram showing the state of each part in FIG. 1. FIG. 6, 7... Rectifier circuit, 12, 13... Voltage stabilization circuit, 14... Amplifier, 15... Transmission line, 16
...mutating switch, 19...coil,
20... Transistor, 23... Muting control signal generation circuit, 24... Output voltage on/off control signal generation circuit.

Claims (1)

【実用新案登録請求の範囲】 記録又は再生装置の信号伝送路に直列又は並列
に接続された信号伝送選択遮断スイツチと、 前記記録又は再生装置の電源の投入時点から電
源回路の出力電圧がほぼ安定化する時点までの期
間は前記信号伝送路を信号伝送遮断状態になし、
前記電源のオフ時には電源オフ時点にほぼ同期し
て前記信号伝送路を信号伝送遮断状態になすよう
に前記スイツチを制御するスイツチ制御回路と から成る記録又は再生装置の信号伝送制御回路。
[Claims for Utility Model Registration] A signal transmission selection cutoff switch connected in series or parallel to a signal transmission line of a recording or reproducing device, and an output voltage of a power supply circuit that is almost stable from the time when the power of the recording or reproducing device is turned on. The signal transmission path is kept in a signal transmission cutoff state for a period up to the time when
A signal transmission control circuit for a recording or reproducing apparatus, comprising a switch control circuit that controls the switch so that when the power is turned off, the signal transmission path is placed in a signal transmission cutoff state substantially in synchronization with the time when the power is turned off.
JP1987053885U 1987-04-09 1987-04-09 Signal transmission control circuit for recording or reproducing device Expired - Lifetime JPH073497Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987053885U JPH073497Y2 (en) 1987-04-09 1987-04-09 Signal transmission control circuit for recording or reproducing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987053885U JPH073497Y2 (en) 1987-04-09 1987-04-09 Signal transmission control circuit for recording or reproducing device

Publications (2)

Publication Number Publication Date
JPS63161456U true JPS63161456U (en) 1988-10-21
JPH073497Y2 JPH073497Y2 (en) 1995-01-30

Family

ID=30880357

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987053885U Expired - Lifetime JPH073497Y2 (en) 1987-04-09 1987-04-09 Signal transmission control circuit for recording or reproducing device

Country Status (1)

Country Link
JP (1) JPH073497Y2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5590023U (en) * 1978-12-13 1980-06-21

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5590023U (en) * 1978-12-13 1980-06-21

Also Published As

Publication number Publication date
JPH073497Y2 (en) 1995-01-30

Similar Documents

Publication Publication Date Title
JPS63161456U (en)
JPH0648581Y2 (en) Cue signal recording circuit
JPS61130072U (en)
JPS5853689Y2 (en) Tape recorder muting device
JPS6176559U (en)
JPH0177018U (en)
JPH0171316U (en)
JPS6248029U (en)
JPS6399411U (en)
JPS62153660U (en)
JPS63130959U (en)
JPS61187110U (en)
JPS6298005U (en)
JPS61121506U (en)
JPH0235363U (en)
JPS6267307U (en)
JPS6316601U (en)
JPH0349633U (en)
JPS6378365U (en)
JPH0260903U (en)
JPH0249212U (en)
JPS6215108U (en)
JPS59185734U (en) tape recorder
JPS5843696U (en) Beat erasure circuit for magnetic recording/playback device with radio receiver
JPS6255204U (en)