JPS63130959U - - Google Patents

Info

Publication number
JPS63130959U
JPS63130959U JP2303287U JP2303287U JPS63130959U JP S63130959 U JPS63130959 U JP S63130959U JP 2303287 U JP2303287 U JP 2303287U JP 2303287 U JP2303287 U JP 2303287U JP S63130959 U JPS63130959 U JP S63130959U
Authority
JP
Japan
Prior art keywords
time
recording
circuit
recording start
setting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2303287U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP2303287U priority Critical patent/JPS63130959U/ja
Publication of JPS63130959U publication Critical patent/JPS63130959U/ja
Pending legal-status Critical Current

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  • Signal Processing Not Specific To The Method Of Recording And Reproducing (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案のミユート回路を示す回路図、
第2図及び第3図は第1図の各部波形を示すタイ
ミングチヤートである。 5,6…タイマー設定回路、18…微分回路、
24…判別回路、32…増幅器、34…外部スピ
ーカ、43…制御回路。
Figure 1 is a circuit diagram showing the mute circuit of the present invention.
2 and 3 are timing charts showing waveforms of various parts in FIG. 1. 5, 6...Timer setting circuit, 18...Differentiating circuit,
24...Discrimination circuit, 32...Amplifier, 34...External speaker, 43...Control circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 音声信号を増幅すると共に外部スピーカと接続
される増幅器を内蔵した電子機器において、現在
時刻を記録開始時刻とすると共に記録開始以降の
時刻を記録終了時刻として設定し、該記録開始時
刻から記録終了時刻まで音声信号を記録媒体に記
録させる第1のタイマー設定回路と、現在以降の
時刻を記録開始時刻とすると共に記録開始以降の
時刻を記録終了時刻として設定し、該記録開始時
刻から記録終了時刻まで音声信号を記録媒体に記
録させる第2のタイマー設定回路と、前記第1、
第2のタイマー設定回路の設定状態に応じた電源
電圧の変動を検出する検出回路と、前記第1、第
2のタイマー設定回路を設定した際に得られる設
定信号、及び前記検出回路にて得られる検出信号
によつて、前記第1、第2のタイマー設定回路の
何れか一方の設定状態を判別する判別回路と、該
判別回路にて得られる判別信号によつて、前記増
幅器の前段の音声信号をミユート制御する制御回
路より成ることを特徴とするミユート回路。
In an electronic device that has a built-in amplifier that amplifies the audio signal and is connected to an external speaker, the current time is set as the recording start time, and the time after the recording start is set as the recording end time, and the recording end time is set from the recording start time. A first timer setting circuit that records an audio signal on a recording medium until the current time, and a time after the current time as a recording start time, and a time after the recording start as a recording end time, and from the recording start time to the recording end time. a second timer setting circuit for recording the audio signal on a recording medium;
a detection circuit that detects fluctuations in power supply voltage according to the setting state of the second timer setting circuit; a setting signal obtained when setting the first and second timer setting circuits; A determination circuit that determines the setting state of either the first or second timer setting circuit based on a detection signal obtained by the determination circuit; A mute circuit comprising a control circuit that mute-controls a signal.
JP2303287U 1987-02-19 1987-02-19 Pending JPS63130959U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2303287U JPS63130959U (en) 1987-02-19 1987-02-19

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2303287U JPS63130959U (en) 1987-02-19 1987-02-19

Publications (1)

Publication Number Publication Date
JPS63130959U true JPS63130959U (en) 1988-08-26

Family

ID=30820973

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2303287U Pending JPS63130959U (en) 1987-02-19 1987-02-19

Country Status (1)

Country Link
JP (1) JPS63130959U (en)

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