JPS63160469A - Clamping circuit - Google Patents

Abstract

PURPOSE:To prevent fluctuation in a clamp voltage by serially inserting a diode between the collector of a clamp transistor and a capacitor in sequential polarity. CONSTITUTION:The diode 9 is serially inserted in sequential polarity between the collector of the clamp transistor 6 and the capacitor 5. Then, a part between the base and the collector of the clamp transistor 6 is prevented from being sequentially biased in a period except a clamp period. Accordingly, irrespective of the largeness of an input signal, the clamp voltage VE is not fluctuated. Thereby, when the input signal (c) lower than (VB-VBC) in level is inputted during the period except the clamp period T, a clamp circuit in which the clamp voltage VE is not fluctuated is obtained. VBC indicates a voltage between the base and the collector of the transistor 6 and VB indicates the base voltage of the transistor 6.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to improving the performance of a clamp circuit.

[Conventional technology]

FIG. 4 is a diagram showing a conventional clamp circuit, in which (1) is an input terminal for input signal a (shown in FIG. 2 (a)), and (2) is a timing signal for clamping (hereinafter referred to as "clamp signal"). (3) is the output terminal of the clamped output signal (shown in Figure 2 (C));
(4) is an input terminal to which the clamp reference voltage EO is applied;
(5) is a capacitor that blocks the DC component of input signal (a), (6) is an NPN transistor for clamping, (7
) is a resistor for keeping the voltage Vm of the signal output terminal (3) constant during non-flushing, and (8) is a power supply terminal to which a voltage EO sufficiently higher than the clamp reference voltage EO is applied.

Next, the operation will be explained.

In the clamp circuit configured in this way, the input terminal (2
), and when input signal a is input from input terminal (1), output terminal (
The voltage of 3) is sEO9, and the capacitor (5) is charged to E. Here, input terminal (2).

When a multi-clamp signal is input, transistor (6)
The transistor (6) conducts during the period T when the clamp signal is high compared to the conduction level V, and the capacitor (5)
The charging voltage, that is, the voltage at the output terminal (3) is Vm=E
+Vα (Vα is the collector-emitter voltage drop Vex when the transistor (6) is conductive). Resistor (7) is set to a sufficiently large value, so
Until the next clamp signal is input, the output terminal (
The voltage Vl of 3) is maintained at a substantially constant value. As a result,
As shown in FIG. 2(C), the output signal C has a voltage level equal to the clamp voltage V during the period T during which the clamp signal was input.
The signal held at i+ is output from the output terminal (3).

[Problem that the invention seeks to solve]

However, in the conventional clamp circuit configured as described above, the minimum level Vmin (second factor (
a) In the period other than the Kufunpu period T, VBO < (
VB - Vmin ) (where, vna is the voltage between the base and collector of transistor (6), and the turtle is the base Min of transistor (6)), then the voltage between the base and collector of transistor (6) is There is a problem that the capacitor (5) is biased and conductive, and during that time charge is accumulated in the capacitor (5), and it is clamped at the voltage (VB-Vmc), causing the clamp voltage E to fluctuate and the waveform of the output signal C to change. Ta.

This invention was made to solve the above-mentioned problems.
) An object of the present invention is to obtain a clamp circuit in which the clamp voltage Vl does not change even when an input signal C of a lower level is input.

[Means for solving problems]

The clamp circuit according to the present invention has a diode inserted in series with forward polarity between the collector of a clamp transistor and a capacitor.

[Effect]

The diode in this invention prevents the base and collector of the clamp transistor from being forward biased during periods other than the clamp period.

Therefore, the clamp voltage WE does not vary regardless of the magnitude of the input signal.

[Embodiments of the invention] An embodiment of the present invention will be described below with reference to the drawings.

In Fig. 1 Ki3, the same symbols as in Fig. 4 indicate the same components, and (9) is inserted in series with forward polarity between the collector of the transistor (6) and the capacitor (5). It is a diode.

In the clamp circuit configured in this way, as shown in Fig. 2 (
b) When the clamp signal indicating K is not input to the input terminal (2), when the input signal a shown in Fig. 2 (a) is input from the input terminal (1), The voltage is E, and the capacitor (5) is charged to E.

Here, when the clamp signal S is input from the input terminal (2), the clamp signal S is higher than the conduction level Vm of the transistor (6) for a period T.
) becomes conductive, the diode (9) becomes forward biased, the charge in the capacitor (5) is discharged, and the charging voltage of the capacitor (5), that is, the voltage at the output terminal (3) becomes V, = E + V.
Until the next clamp signal is input,
It is held at the clamp voltage Vl as in the conventional clamp circuit. However, Vβ is the sum of the collector-emitter drop voltage VOE when the transistor (6) is conductive and the forward direction drop voltage vn of the diode (9).

Next, in a period other than the clamp period T, the minimum level vmin of the input signal a is VBO< (VB −Vmin)
In this case, the base-emitter of the transistor (6) becomes forward biased, but the diode (9) becomes reverse biased, so that no charge is accumulated in the capacitor (5).

In this way, in this embodiment, the capacitor (5) is not charged or discharged outside the kufunpu period T, and the clamp voltage v1A does not fluctuate.

FIG. 8 is a diagram showing another embodiment of the present invention, in which a PNP junction clamp transistor (6) is used.

In this embodiment, the diode (6) is inserted in series between the collector of the transistor (6) and the capacitor (5) with different polarity than in the embodiment of FIG. As shown in FIG. 2(d), the input signal is inputted with the opposite polarity, and the input signal a is also inputted with the opposite polarity from that of FIG. 2(a).

The operation of this embodiment is similar to that of the embodiment shown in FIG. 1, so detailed explanation will be omitted.

〔Effect of the invention〕

As described above, according to the present invention, a diode with forward polarity is inserted in series between the collector of the Kumpfungister and the capacitor, so that the input signal forward biases the clamp transistor during periods other than the clamp period. However, since the diode is reverse biased, there is an advantage that the clamp voltage VM does not fluctuate.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of one embodiment of the present invention, FIG. 2 is a waveform diagram for explaining the operation of the clamp circuit, FIG. 8 is a circuit diagram of another embodiment of the present invention, and FIG. The figure shows a conventional clamp circuit. (5)...Capacitor, (6)...Transistor, (7
)...Resistance, (9]...Diode, E...Clamp reference voltage. In each figure, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] (1) A capacitor that blocks the DC component of the input signal, a power supply connected to the output side of this capacitor via a resistor, a collector connected to the output side of the capacitor, and a clamp signal input from the base, and 1. A clamp circuit comprising a transistor to which a clamp reference voltage is input from an emitter, the clamp circuit comprising a diode inserted with forward polarity between the collector of the transistor and the capacitor.