JPS63160418A - Logic circuit - Google Patents

Abstract

PURPOSE:To contrive to reduce the number of required components by connecting each base and other emitter of a couple of same conduction type bipolar transistors (TRs) and connecting collectors. CONSTITUTION:An emitter of a PNP TR Q11 whose base is connected to an input terminal A via a resistor R11 is connected to an input terminal B. Moreover, an emitter of a PNP TR Q12 whose base is connected to the input terminal B via a resistor R12 is connected to the input terminal A. Moreover, collectors of the TRs Q11, Q12 are connected to the output terminal C in common and the connecting point is connected to ground via a resistor R13. Thus, the circuit constitution is simplified, the number of components is decreased and the degree of circuit integration is improved.

Description

[Detailed Description of the Invention] [Industrial Field of Application] [Prior Art] Conventionally, this basic logic system, for example, an exclusive OR circuit,
As shown in FIG. 9, it had input terminals A, B, and an output terminal C, and was constructed by combining four NAND gates G11 and 14 tubes. NAND G11 to G14 have ``1'' and @1'' in their inputs and output ``0'' only at 9 o'clock, and output @1'' for other inputs. Next, the operation of the logic circuit shown in FIG. 9 will be explained using the truth table of this logic circuit shown in FIG. 10.

When the human power A is 10" and the human power B is 10", the human power of NAND gate Gll is 90" and "0", so the output of NAND gate Gll is '1', and NAND gate 012
Since the inputs are "o" and "■", the output #li of NAND gate G12 is "l", and the input i@l of NAND gate G13
”!-”O'ID is NANl)G13's output is @
1" and NAND game) G14 input is '1" and 11
", so the output of the NAND gate G14 becomes O'". Therefore, the output of output terminal C will be @O". When person A is "0" and input B is 11, it is an AND game) Gll's human power is "O" and '"1, so it is a VD game) The output of Gl 1 is 1''9, D gate G12 to NA
Since the inputs are '0'' and @l'', it is a NAND game) ()12
The output of is 11", the human power of NAND gate G13 is @l"
and 11'', the output of the NAND gate G13 becomes '0', and the output of the NAND gate G14 becomes 'l' and 'o', so the output of the NAND gate G14 becomes @l''.

Therefore, the output of output terminal C becomes 51''.

When human power A is ``1'' and human power B is o'', NAN[)
The inputs of gate Gll are @l” and ``0'', so NANL
)Gl The output of Gl is 'l', and the NAND gate G120 inputs are '1' and 11', so AΔDG)
The output of Gl 2 is 1″0″, NANI) gate t)13
0 man power is @l" and '"O" so NAN D game) G1
3 becomes @1'I, and the human power of NAND gate G14 becomes vi '''O'' and '''l'', so the output of NAND gate ()14 becomes 1''. Therefore, the output of output terminal C is It becomes 1”.

When the human power A is "1" and the human power B is @1", the output of the MARD gate Gll becomes @0", and the output of the NAND gate Gl is "1".
I) The inputs of gate G12 are @1″ and @O″, so NAN
D game) Gl 2 output is 11", NAND gate G1
The inputs of 3 are @O'' and 11'', so NAND gate G13
The output of is ``l'', and the input of D gate G14 to NA;
K) The output of G14 becomes "O". Therefore, output terminal C
The output of will be @O″.

As explained above, with respect to the inputs A and B, the output C is an exclusive sum as shown in the truth table of FIG. 1θ.

In addition, as a conventional logic circuit, for example, a coincidence circuit has input terminals A, B, and all output terminals, as shown in Fig. 11, and is constructed by combining four NOR games) 021 to G24. . 021~G24Fi, outputs "1" only when @O" and O'" are input to the input, and outputs @0 for other inputs.Next, Using the truth table of this logic circuit shown in Figure 12, the 11th
Operation f of the logic circuit shown in the figure will be explained.

When human power A is @O" and input B is @θ", the inputs of NOR gate G21 are @0" and 10", so NOR gate G2
The output of 1 is ``1m.'' Since the human power of L gate G22 is ``0'' and 11'', the output of NOR gate G22 is ``o'', and the input of gate G23 is @l'' and 10''. Therefore, the output of NOR gate G23 becomes '0'', and N(J
The inputs of the R gate G24 are ``0'' and ``RO'', and the output of the N(J) gate G24 is ``1''. Therefore, the output of the output terminal C is ``1''.

When the human power is 10'' and the input B is 11'', the human power of NOR gate G21 is ``O'' and ``1'', so the output of NOR gate G21 is ``O''.jj), N0RJ)'
- is 10″ and 11″, so the output of NOR gate G23/
/i″'0″ and N (the input of JR gate G24 is “
1'' and ``O'', the output of the NOR gate G24 becomes ``0m.'' Therefore, the output of output terminal C becomes @O'.

When input A is @1'' and human power B is 10'', NUI (because the human power of JR gate 021 is “1” and “0”).

The output of the gate (J21 is ``O'', and the manual power of the NO gate G220 is ``1'' and ``O'', so the output of the i'J (J game) 022 is 10'', and the output of the N (J game) gate G23O is
Human power u”0”m and ’”0”. The output of TE N01'-G23 is 11''9, and the input of NOR gate G24 is ``0'' and 11'', so NOR gate G24
The output of output terminal C becomes @0". Therefore, the output of output terminal C becomes "o
"become.

When human power A is @l'' and human power B is ``1'', the inputs of N(JR gate G21 are ``l'' and 1'', so the output of N(JR game) G21 is ``O'', N (Jf is also gate G2
The input of 2 is “1” and ’”On, so υ几Game)G22
The output of is II O#, the human power of NOR gate G23 is 10
” and @1”, so NOR, gate GZ (output is ’”0
"tona, j), N01 (The human power of gate G24 is "o" and @O", so the output of N (JR gate ()24 is @
Therefore, the output of the output terminal C becomes ``1''.

As explained above, the output Crc'''1'' is output only when the human power A and the input B match.

[Problem that the invention seeks to solve]

The conventional logic circuit described above, for example, the exclusive OR circuit, is constructed by combining four NAs with a D gate.
In addition, the matching circuit is constructed by combining four NOR gates9, and each gate requires at least two to three transistors and several resistors, so the disadvantage is that the number of I elements increases. I was disappointed.

[Means for solving problems]

In the logic circuit of the present invention, the bases of a pair of bipolar transistors of the same conductivity type and the emitters of the other are connected to each other, each connection point is used as an input terminal, and the collectors of the pair of bipolar transistors are connected to each other. The connection point is used as an output end, and this output end is connected to a reference potential via a resistance means.

〔Example〕

FIG. 1 shows a first embodiment of the present invention. P whose base is connected to input terminal A through a resistance ratio of 11t-
The emitter of the NP transistor Qll is connected to the input terminal B, the emitter of the PNP transistor Q12 whose base is connected to the input terminal B through a resistance ratio of 12f is connected to the input terminal AK, and the collectors of the transistors Qll and Q12 are connected to the output terminal B. They are commonly connected to terminal C, and their connection point is grounded via resistor R13.

Next, the operation of the logic circuit shown in FIG. 1 will be explained using the truth table shown in FIG. Here, the logic is 2"o" when it is low level, and 1" when it is high level.When the input power is 0" and the power B is 10', the transistor Q,
11. The base and emitter of Q12 are both zero biased, and transistor 11. Both Q12 are turned off and the output of output terminal C becomes @O''. When input A is O'' and input B is 11', 1. Base of transistor Qll
The emitter is forward biased, and the transistor Q1
Since the base-emitter of transistor 2 is biased in the opposite direction, transistor 11 is on.

Transistor Q12 is turned off. Therefore, the signal given to the input terminal B is the transistor Ql l? is output to the output terminal C, and the output of the output terminal C becomes 11".When the human power A is 1" and the input B is O", the base and emitter of the transistor Q11 are biased in the opposite direction, and the output of the transistor Q12 is biased in the opposite direction. Since the base-emitter is forward biased, transistor Qll is off and transistor Q1
2! Turns on. Therefore, the signal applied to the input terminal A passes through the transistor Ql2e and is output to the output terminal C, and the output of the output terminal C becomes 1''.

When input A is ``1'' and input B is @1'', the base and emitter of transistors Qll and Q12 are both at zero bias, so both transistors Ql1 and Q12 are turned off, and the output terminal C is The output becomes ``O''.

As explained above, with respect to inputs A and B, output C becomes an exclusive OR as shown in the truth table of FIG.

FIG. 3 shows a second embodiment of the invention. The configuration between input terminals A, B and terminal C is the same as the circuit shown in the first embodiment. The base of the transistor Q4, whose collector is connected to the power supply ■cc and whose emitter is connected to the output terminal via a diode Dl, is connected to the power supply V via a resistor R4t. C and the collector of the transistor Q3, the base of this transistor Q3 is connected to the terminal C, and when the emitter is grounded through the resistor R5, it is connected to the base of the transistor Q5. The collector of is connected to the output terminal, and the emitter is grounded.

Next, the operation of the logic circuit shown in FIG. 3 will be explained using the truth table shown in FIG. Input terminal A.

The circuit operation between terminal B and terminal C is exactly the same as in the first embodiment, so a description thereof will be omitted.

In Figure 3, when the logic at the terminal C point is "O", the base potential of the transistor Q3 is @O", so the transistor Q
31QIS is turned off and the base potential of transistor Q4 rises almost to the power supply voltage ■cc, transistor Q4 is turned on and the output from the output terminal becomes 'l'.
When the a principle at point is @1''', the base-emitter of transistor Q3 is biased in the J@ direction, and transistor Q
3 is not turned on, and transistor Q5 is also turned on.

At this time, the base potential of transistor Q4 is approximately the base-emitter voltage of transistor Q5 (1fX), 7V)
become. Therefore, since the transistor Q4 is turned off, the output from the output terminal becomes "O"K.

As explained above, for inputs A and Bvc, the output is M
An output indicating a match is obtained as shown in Figure 4: A truth value. Figure 5 shows a third embodiment of the present invention. NP whose base is connected to input terminal A via resistor R21
The emitter of the N-type transistor Q21 is connected to the input terminal B, the emitter of the NPN-type transistor Q22 whose base is connected to the input terminal B through the resistor 22't- is connected to the input terminal A, and the The collectors are commonly connected to the output terminal C, and their grounding point is connected to the power supply VccVc via a resistor Rja.

Next, the operation of the nine logic circuits shown in FIG. 5 will be explained using the -A logic table of FIG. 6. Here, the logic is similar to the explanation of the first and second embodiments, when the logic is low level, t-@o
'', and when it is at a high level, it is set to ``1''.
When the human power B is 10" at "O'", the transistor Q21
．． The base and emitter of Q22 are both at zero bias, and both transistors Q21 and Q22 are off.
The output of output terminal C becomes ``1''. The input person is 'mO'
When the human power B is 11", the base and emitter of the transistor Q21 are biased in the opposite direction, and the transistor Q21 is biased in the opposite direction.
Since the base-emitter of transistor Q22 is biased in the +a direction, transistor Q21 is turned off and transistor Q22 is turned on.

Therefore, the signal seen at input terminal AK4 is transmitted to transistor Q
22ft and is output to the output terminal C, and the output of the output terminal C becomes 'mO'. When the input A is @1" and the input B is "O", the base-emitter of the transistor Q21 is biased in the forward direction. , since the base and emitter of transistor Q22 are biased in the opposite direction, transistor Q22 is biased in the opposite direction.
21 is on.

Transistor Q22 is turned off. Therefore, the signal applied to the input terminal B is outputted to the output terminal C through the transistor Q21, and the output of the output terminal C becomes 10''.

When input A is 1'' and input B is 11'', transistor Q21. Since zero bias is applied between the base and emitter of Q22, both transistors Q21 and Q22 are turned off, and the output from the output terminal C becomes "1".

As explained above, 'l' is output to the output C only when the logic of the human power A and the input B match.

FIG. 7 shows an embodiment of the roar 4 of the present invention. The configuration between the input layers A and B and the terminal C is the same as the circuit shown in the third embodiment, and the configuration between the terminal C and the output terminal is the same as the circuit shown in the second embodiment. The circuit configuration between the terminal C and the output terminal in the circuit shown in FIG. 2 is similar.

Next, the operation of the logic circuit shown in FIG. 7 will be explained using the truth table shown in FIG. Input terminal A.

The circuit operation between terminal B and terminal C is exactly the same as in the third embodiment, so a description thereof will be omitted.

In Fig. 8, when the terminal a at point C is @O'', the base potential of transistor Q3 is 'mO'', so transistor Q
3. Q5 is turned off and the base potential of transistor Q!40 rises to almost the power supply [8:V, .
is turned on and the output terminal becomes output ``1''. Further, when the logic at the terminal C is ``1'', the base-emitter BiJ of the transistor Q3 is biased toward the internal direction, the transistor Q3 is not turned on, and the transistor Q5 is also roughly turned on. At this time, the base potential of transistor Q4 is approximately the base-emitter voltage of transistor Q5 (approximately o,
7V). Therefore, since the transistor Q4 is turned off, the output from the output terminal becomes '0'.

As explained above, for human power A and B, the output is 8th
As shown in the truth table in the figure, it becomes a tJF curved disjunction.

〔Effect of the invention〕

As explained above, the present invention has made it possible to realize a simple circuit configuration that has conventionally been configured by a combination of NAND gates or a combination of FiNO gates. The circuit configuration is simple, so the number of elements is about 1/1 compared to conventional ones.
4, increasing the degree of integration by four times. Further, there is an effect that circuit verification etc. can be easily performed, and circuit design and layout design can be performed in a short time.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a logic circuit in the first embodiment of the invention, FIG. 2 is a diagram showing a truth table of the logic circuit in the first embodiment of the invention, and FIG. A circuit diagram showing a logic circuit in the second embodiment, FIG.
FIG. 5 is a circuit diagram showing the logic circuit in the third embodiment of the present invention, and FIG. 6 is a diagram showing the truth table of the logic circuit in the third embodiment of the present invention. FIG. 7 is a circuit diagram showing a logic circuit in a fourth embodiment of the present invention; FIG. 8 is a diagram showing a truth table of a logic circuit in a fourth embodiment of the present invention; 9 and 10 are a circuit diagram of a conventional exclusive-ground circuit and A
FIG. 11 and FIG. 12 are diagrams showing a conventional matching circuit and a four-way table, respectively. Qll, see 12...)'NP) transistor, see G22. G3. G4. G5...Nf'l'J
) u/distor, υ1... diode, 11.
Ordinary 12.几13゜■also21. R22, Le23. R4,l
L5...Resistance, G11, 1J12. ()13.
(j14...NAND gate, (j21.(j
22. G23. ()24...N (Jl Maru Gate. Agent '5P Burial Officer Susumu Uchihara '3rd
Figure VCCCC system Figure 7 No. 6

Claims (1)

[Claims] The bases of a pair of bipolar transistors of the same conductivity type and the emitters of the other are connected to each other, and each connection point is used as an input terminal, and the collectors of the pair of bipolar transistors are connected to each other, and the connection point is used as an input terminal. 1. A logic circuit characterized in that the output terminal is connected to a reference potential via a resistance means.