JPS63160353A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To measure the characteristic of a transistor while a first and a second switches are turned on and to actuate an inverter as an ordinary inverter while a third and a fourth switches are turned on by a method wherein the four switches are connected to gates of PMOS and NMOS constituting the inverter and these four switches are turned on and off complementarily. CONSTITUTION:An inverter 13 is constructed by a PMOS-FET 13-1 and an NMOS-FET 13-2 which are connected in series; a power-supply voltage VCC is applied to a source of the FET 13-1; the source of the FET 13-2 is kept at a grounding potential VSS; furthermore, each drain of the FET 13-1 and the FET 13-2 is connected to a common output terminal 11. In addition, a first switch 14-1 is connected between a gate of the FET 13-1 and a first input terminal 10-1; a second switch 14-2 is connected between the gate of the FET 13-2 and a second input terminal 10-2; a third switch 14-3 is connected between the gate of the FET 13-1 and a signal terminal 12; a fourth switch 14-4 is connected between the gate of the FET 13-2 and the signal terminal 12, respectively. The switches 14-1 and 14-2 and the switches 14-3, 14-4 are turned on and off repellingly by a signal which is fed to a control terminal 15. By this method, it is not necessary to install a transistor for measurement use for the express purpose; the number of external extraction terminals can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor integrated circuit for measuring transistor characteristics of a semiconductor device.

(Prior Art) Conventionally, there have been technologies in this field, such as those shown in FIGS. 2 and 3, for example. The configuration will be explained below.

FIGS. 2 and 3 are principal circuit diagrams showing an example of a conventional semiconductor integrated circuit.

When measuring the transistor characteristics of a semiconductor device, a P-channel MOS transistor for testing (hereinafter referred to as PH03) as shown in Fig. 2 and an N-channel MOS transistor for testing as shown in Fig. 3 are installed in the semiconductor integrated circuit. (hereinafter referred to as N)IO8).

When measuring the static characteristics of PHO'S in a semiconductor integrated circuit, as shown in FIG. A voltage v2 is applied to 1S. By measuring the current flowing through the drain terminal 1D at this time, the drain-source current at the gate-source voltage V1 and the drain-source voltage V2 can be measured.

Similarly, when measuring the static characteristics of NHO3 in a semiconductor integrated circuit, apply a voltage v1 to the gate terminal 2G of NHO32 with respect to the source terminal 2S, and apply a voltage v2 to the drain terminal 2D with respect to the source terminal 2S. do.

At this time, by measuring the current flowing through the drain terminal 20, the measured value of the drain-source current at the gate-source voltage V and the train-source voltage V2 can be obtained.

In this way, in conventional semiconductor integrated circuits, when measuring the transistor characteristics of a device, the PMO31 and NHO for parameter measurement provided inside the semiconductor chip are used.
32 static characteristics were measured.

(Problems to be Solved by the Invention) However, in the semiconductor integrated circuit having the above configuration, since the p+osi and NHO32 for transistor characteristic measurement are provided inside the device for transistor characteristic measurement, The source voltage (source pad), train electrode, and gate electrode of
3 and N) Required for each 103 characteristic measurement circuit. Therefore, there is a problem in that the chip size increases due to the reduction in the area of the external lead terminal. In addition, in order to measure the transistor characteristics of a transistor with a large transistor size, it is necessary to provide a circuit with a large transistor size inside the device, but this increases the chip size of the device, making it difficult to Moreover, it has been difficult to measure the characteristics of transistors with large transistor sizes.

The present invention solves the problems of the prior art, in that the circuit for measuring transistor characteristics increases the chip size of the device, and that the circuit for measuring transistor characteristics of a large transistor leads to an increase in the chip size. The present invention provides a semiconductor integrated circuit which solves the problem that it is difficult to incorporate it inside a chip.

(Means for Solving the Problems) In order to solve the above problems, the present invention provides a semiconductor integrated circuit for measuring transistor characteristics of a semiconductor device, in which PMO3 and N)IO3 are connected in series and their connection point is is connected to the output terminal, and the inverter ρ8 is connected to the output terminal.
a first switch connected between the gate of 08 and the first input terminal and controlled on and off by a control signal;
a second switch connected between the gate of HO3 and a second input terminal and controlled to be turned on and off in synchronization with the first switch by the control signal; and between the gate of PH08 and the gate of the previous stage thereof; a third switch connected to and controlled to be turned on and off in opposition to the first and second switches by the control signal; and a third switch connected between the gate of NHO3 and the gate of the previous stage. and a fourth switch that is controlled on and off in synchronization with the fourth switch.

(Function) According to the present invention, since the semiconductor integrated circuit is configured as described above, the first and second switches and the third and fourth switches perform on and off operations in a complementary manner. 1
．． When the second switch is turned on, the input side of the inverter is connected to the first
．． It connects to the second input terminal and makes it possible to measure the transistor characteristics in P) 103 and NHO 3 that constitute the inverter, and also connects the inverter to the inverter of the normal circuit when the third and fourth switches are turned on. operate as This eliminates the need to provide a transistor for measurement, and also reduces the number of external lead-out terminals. Therefore, the above-mentioned problem can be eliminated.

(Embodiment) FIG. 1 is a circuit diagram of a main part of a semiconductor integrated circuit showing an embodiment of the present invention.

This semiconductor integrated circuit is the first. Second input terminal 10-1.
10-2, output terminal 11, signal terminal 12 of the previous stage gate
, output inverter 13, first . Second. Third and fourth switches 14-1 to 14-4 and a control terminal 15 are provided. Inverter 13 is PH0313-1 and NHO3
Consists of 13-2 series circuits, whose P) +0313-
A power supply voltage vCC is applied to the source of the PMO 313-1, the source of the NHO 313-2 is held at the ground potential VSS, and the drains of the PMO 313-1 and the NHO 313-2 are commonly connected to the output terminal 11.

In addition, the gate of P) 10513-1 and the first input terminal 1
Between 0 and 1, the first switch 14-1 switches the NHO313
A second switch 14-2 is connected between the gate of PMO313-1 and the second input terminal 10-2, a third switch 14-3 is connected between the gate of PMO313-1 and the signal terminal 12,
A fourth switch 14 is connected between the gate of -2 and the signal terminal 12.
-4 are connected to each other.

The control terminal 15 is a terminal for generating a control signal for turning on and off the switches 14-1 to 14-4, and the signal supplied to this control terminal 15 causes the switch 10-
1.10-2 and switch 14-3.14-4 are configured to perform on/off operations in opposition to each other.

FIG. 4 is a circuit diagram showing a specific example of the configuration of FIG. 1.

In this circuit, each switch 14-1 to 14-4 in FIG.
are composed of transfer gates 24-1 to 24-4, respectively, and a pull-a-tub resistor 25 and an inverter 26 are further connected to the control terminal 15.

Here, the first to fourth transfer gates 24-1 to 24-2
4-4, the first transfer gate 24-1 is
It has PMO82AP and NHO324N, their sources are commonly connected and their drains are commonly connected, and the source and drain are turned on and off by complementary signals MA and X given to each gate of PMO324P and NHO324N. It is a switch that performs an operation.

That is, the first transfer gate 24-1 has its P
)lO824P gate has an L level signal, N)l
When the H level signal X is input to the gate of each O324N, the O324N turns on, and when the signal M is at the H level and the signal X is at the L level, the O324N turns off.

The second transfer gate 24-2 has the same configuration as the first transfer gate 24-1. Second. The third transfer gate 24-3, 24-4 has the same structure as the first transfer sheet 24-1, but performs an on/off operation opposite to that of the transfer gate 24-1.
This switch is turned off when the signal M is at the L level and the signal X is at the H level, and is turned on when the signal M is at the H level and the signal X is at the L level.

Further, the pull-up resistor 25 connected to the control terminal 15 has a PMO3, and the source of the PMO3 is connected to the power supply voltage V.
CC is applied, and the drain is connected to the control terminal 15 and the gate is connected to the ground, respectively, and is always on to raise the potential of the control terminal 15 to a certain level.

The control terminal 15 outputs a signal M, and the signal M is inverted by an inverter 26 to output a signal X.

Next, the operation shown in FIG. 4 will be explained using the circuit shown in FIG. 4, and the operation shown in FIG. 1 will also be explained. In addition, below, (
1) P using an output inverter 13 of a semiconductor integrated circuit
Static characteristics measurement method of MO313-1, (2) Same < NH
The method for measuring static characteristics of O313-2 and (3) normal operation of the output inverter 13 will be explained separately.

(1) Transistor static characteristics measurement method in PMO313-1 When an L level signal is supplied to the control terminal 15, the signal
level, signal X becomes H level, transfer gate 24-3.24-4 (switch 14-3.14-4)
is off, transfer gate 24-1.24-2
(switch 14-1.14-2) is in the on state,
The output terminal 13 is separated from the internal circuit of the semiconductor integrated circuit. By applying an L-level voltage to the second input terminal 10-2, the NHO 313-2 is turned off.

The voltage of Vl is input to the input terminal 10-1 with respect to the power supply voltage VCC.
At the same time, a voltage of v2 is applied to the output terminal 11 with respect to the power supply voltage vCC. The current flowing through the output terminal 11 at this time is measured. This is the gate-source voltage V1 and drain-source voltage v in PMO313-1.
This means that the drain-source current at the time of 2 was measured.

Here, by changing the voltages of Vl and V2, P
The static characteristics of MO513-1 can be measured.

(2) N) Transistor static characteristic measurement method in 10313-2 Apply L level voltage to control terminal 15 and transfer gate 24-3.24-4 (switch 14-3.14-
4> is turned off, and the first input terminal 10-1
Apply an H level voltage to P) to turn off the IO 313-1.

A voltage of V2 is applied to the output terminal 11 with respect to the ground potential VSS, and a voltage of vl is applied to the second output terminal 11 with respect to the ground potential VSS.
is applied to the output terminal 10-2 of. At this time, the current flowing through the output terminal 11 is measured. This means that the train-source current was measured when the gate-source voltage V1 and the drain-source voltage V2 in N) 10313-2. By changing these voltages Vl and V2, the static characteristics of N)lO313-2 can be measured.

(3) When an H level signal is applied to the normal operation control terminal 15 of the output inverter 13, the signal
becomes L level, and transfer gate 24-1.24
-2 (switch 14-1.14-2) turns off, and transfer gate 24-3.24-4 (
The switches 14-3, 14-4> are turned on, and the output inverter 13 is connected to the internal circuit. As a result, the output inverter 13 operates as a normal output inverter, inverts the signal applied from the signal terminal 12, and outputs it to the output terminal 11.

According to this embodiment, compared to a semiconductor integrated circuit including a conventional transistor characteristic measuring circuit, the number of external lead-out terminals is reduced, so the chip size can be reduced.

FIG. 5 is a circuit diagram showing a specific example of the configuration of the pond shown in FIG. This circuit shows an example of a circuit for measuring the static characteristics of a plurality of, for example three, output inverters 13-11 to 13-31 in a semiconductor integrated circuit.

In this circuit, the first. Second input terminal 10-1゜10-
2, and three output inverters 13 shown in FIG. 4 are connected in parallel between the input terminals 10-1 and 10-2. That is, the first stage is PH0313-1 and NHO31
It has an inverter 13A consisting of 3-12, and its PMO
Transfer game to the gate of 313-11) 24-11
The first input terminal 10-1 is connected through the transfer gate 24-13, and the signal terminal 12-1 is connected through the transfer gate 24-13.
is connected, and the second input terminal 10- is connected to the gate of the NHO 313-12 via the transfer gate 24-12.
2 is connected to the signal terminal 12-1 via the transfer gate 24-14, and the output terminal 11-1 is further connected to the output side of the inverter 13A. Similarly, the second stage is P) (0313-21 and NHO3
Inverter 13B consisting of 13-22,) transfer gates 24-21, 24-22.

24-23, 24-24, a signal terminal 12-2, and an output terminal 11-2, and the third stage is PMO3.
Inverter 1 consisting of 13-21 and NHO313-32
3C, transfer gate 24-31, 24-32
, 24-33, 24-34, a signal terminal 12-3, and an output terminal 11-3.

Further, on the control terminal 15 side, a signal X and a signal M obtained by inverting the signal The structure is such that

Next, three such output inverters 13A.

5 (i >
When an L level signal is input to the static characteristic measurement method control terminal 15 of the PMO 313-11, 13-21, 13-31, an L level signal X and an H level inverted signal M from the inverter 26 are output. Transfer gates 2413, 24
-14, 24-23, 24-24, 24-33
.

24-34 is off and each in park 138-1
3C is separated from the signal terminals 12-1 to 12-3, and the transfer gates 24-11 and 24-12
, 24-21.

24-22, 24-31, and 24-32 are turned on, and each inverter 13A to 13G is in the first. It is connected to second input terminals 10-1 and 10-2.

1 to the second input terminal 10-2. Apply level voltage, NH
Turn off O313-12, 13-22, and 13-32.

Then, the voltage v2 is applied to each output terminal 1 with respect to the power supply voltage vCC.
1-1 to 11-3, and also applies a voltage of Vl to the first input terminal 10-1 with respect to the power supply voltage vCC,
By reading the current flowing through each output terminal 11-1 to 11-3 at this time, each PMO 313-11, 13-21,
13-31 gate-source voltage V1 and drain
The drain-source current can be measured with respect to the source-to-source voltage V2. This voltage V1. By changing V2, it becomes possible to simultaneously measure the static characteristics of P) 10313-11, 13-21, and 13-31.

(ii) NHO313-12, 13-22, 13-
An L level signal is input to the static characteristic measurement method control terminal 15 of 22, and the transfer gates 24-13, 24-14, 24-23, 24
-24.

24-33, 24-34 in off state, transfer gates 24-11, 24-12, 24-21, 24
-22, 24-31.

24-32 is turned on, the first input terminal 10-
1 by applying an H level voltage to P) IO313-11.

13-2i and 13-31 are turned off.

Then, a voltage of vl with respect to the ground potential VSS is applied to the second input 10-2, and a voltage of V2 with respect to the ground potential vSS is applied to the second input 10-2.
voltage is applied to each output terminal 11-1 to 11-3. At this time, by measuring the current flowing through each output terminal 11-1 to 11-3, NHO313-12, 13-22, 1
The train-source current at the gate-source voltage v1 and drain-source voltage v2 in 3-32 can be measured. By changing these voltages Vl and V2,
Simultaneous measurement of static characteristics in NHO313-12, 13-22, and 13-32 becomes possible.

(iii) Output inverter 13A, 138, 1
When an H level signal is applied to the normal operation control terminal 15 of the 3C, an H level signal X and its L level signal MA are generated, and the signal X,
Transfer gate 24-11 by X.

24-12, 24-21, 24-22, 24-3
1, 24-32 are turned off, and inverters 138, 138, 13C are input/output terminals 10-1, 10-2.
The transfer gate 24-1 is separated from the transfer gate 24-1.
3, 24-14, 24-23, 24-24.

24-33, 24-34 are turned on, and the inverters 13A, 138, 13C are connected to each signal terminal 12-1.
~12-3. Therefore, each of the inverters 138 to 13C operates as a normal circuit inverter, inverts the signals from the signal terminals 12-1 to 12-3, and outputs the inverted signals from the output terminals 11-1 to 11-3.

In this embodiment, the chip size can be reduced by reducing the number of external lead-out electrodes, as in the above embodiments. Furthermore, by using the circuit of this embodiment, it is also possible to simultaneously measure the output characteristics of the output inverters 138 to 13G. Therefore, in the past, the output current characteristics (TOH/
When measuring the pin (P) or output voltage characteristics (VOH/VOL), a certain pattern is used to measure the pin (P).
The transistor characteristics were measured by setting the IOH/IOL characteristics of all output inverters 138 to 13C at the same time using the measurement method of this embodiment.
O1l/VOL measurement becomes possible.

Note that the present invention is not limited to the illustrated embodiment, and various modifications are possible. For example, switches 14-1 to 14 in FIG.
-4 may be a switch using a gate circuit or the like other than a transfer gate.

In addition, the inverter 13 is P)10s13-1 and NHO
The connection state of the inverter 313-2 may be reversed, and the number of stages of the inverter 13 may be two, four or more.

(Effects of the Invention) As described above in detail, according to the present invention, the first, second and third gates are connected to the gates of the PMO3 and the gates of the inverter O8.
The third and fourth switches are connected and the first and second switches and the third and fourth switches are turned on and off in a complementary manner. By turning on the second switch, the transistor characteristics can be measured, and the third switch is turned on. By turning on the fourth switch, it can be operated as a normal inverter. Therefore, there is no need to newly provide a transistor for measuring transistor characteristics, and the number of external lead-out terminals is reduced, so a reduction in chip size can be expected.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram of a main part of a semiconductor integrated circuit showing an embodiment of the present invention, Figures 2 and 3 are circuit diagrams of a main part of a conventional semiconductor integrated circuit, and Figure 4 is a specific example of the circuit shown in Figure 1. FIG. 5 is another specific circuit diagram of FIG. 1. 10-1.10-2... 1st. Second input terminal, 11°11-1 to 11-3... Output terminal, 1
2.12-1 to 12-3...signal terminals, 13.
138-13C...Inverter, 13-1. 13-11, 13-21, 31-31...
PH03, 13-2, 13-12. 13-22, 13-32...NHe5.14
-1 to 14-4... 1st ° 2nd. Third. Fourth switch, 15... Control terminal, 24-1 to 24
-4.24-11~24-14, 24-21~24-
24. 24-31 to 24-34...Transfer gate. Applicant's agent Kyo Kakimoto Specific circuit diagram of acid figure 1 Figure 4

Claims (1)

[Claims] P-channel MOS transistor and N-channel MOS
an inverter in which transistors are connected in series and a connection point thereof is connected to an output terminal; a first switch connected between the gate of the P-channel MOS transistor and a first input terminal and controlled on and off by a control signal; , a second switch connected between the gate of the N-channel MOS transistor and a second input terminal and controlled to turn on and off in synchronization with the first switch by the control signal; a third switch connected between the gate of the N-channel MOS transistor and the gate of the previous stage and controlled on and off by the control signal in opposition to the first and second switches; and a fourth switch connected between the gates and controlled to turn on and off in synchronization with the third switch.