CN103165168A - Double-mode reading device and circuit - Google Patents
Double-mode reading device and circuit Download PDFInfo
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- CN103165168A CN103165168A CN2011104288476A CN201110428847A CN103165168A CN 103165168 A CN103165168 A CN 103165168A CN 2011104288476 A CN2011104288476 A CN 2011104288476A CN 201110428847 A CN201110428847 A CN 201110428847A CN 103165168 A CN103165168 A CN 103165168A
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- 239000003990 capacitor Substances 0.000 claims abstract description 59
- 238000005070 sampling Methods 0.000 claims abstract description 18
- 238000012423 maintenance Methods 0.000 claims description 12
- 230000010354 integration Effects 0.000 claims description 10
- 230000005669 field effect Effects 0.000 claims description 4
- 230000003287 optical effect Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000007600 charging Methods 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000005693 optoelectronics Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
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Abstract
A double-mode reading device and a circuit are suitable for reading sensing current generated by a current type sensor. The double-mode reading circuit comprises a capacitive transimpedance amplifier, a sampling holder and a switcher. The capacitive transimpedance amplifier comprises an integrating capacitor which is used for converting the sensing current to integrating voltage, a first transistor and a second transistor. The sampling holder is used for conducting sampling holding to voltage of the integrating capacitor and providing output voltage, and the switcher is electrically connected with capacitive transimpedance amplifier. By means of the double-mode reading circuit, a first mode and a second mode are operated through the switcher, the first mode and the second mode are respectively used for reading two different types of sensors, and a proper circuit reading mode is adjusted on account of the type of the sensor.
Description
Technical field
The present invention relates to a kind of circuit, particularly relate to a kind of double mode reading device and circuit.
Background technology
Consult Fig. 1, in US Patent No. 6121843, disclose a kind of existing reading circuit 1.This reading circuit 1 is used for reading the current sensor of an OPTICAL SENSORS 10, and exports an output voltage VO UT who is proportional to this current sensor size.
This OPTICAL SENSORS 10 is opto-electronic conversion diodes 10, and has the negative electrode of reception one a reference bias COM, and an anode.This OPTICAL SENSORS 10 can produce the current sensor that this size is relevant to this light signal strength according to this when sensing light signal (as infrared signal).
This reading circuit 1 has a transistor 11, one first electric capacity 12, one second electric capacity 13, one the 3rd electric capacity 14, one first switch 15, a second switch 16 and one the 3rd switch 17.
This transistor 11 has a grid, that is electrically connected to the anode of opto-electronic conversion diode 10 and drains and one source pole.This first electric capacity 12 is electrically connected between the grid and drain electrode of this transistor 11, and this second electric capacity 13 is electrically connected between the source electrode and ground connection of this transistor 11, and the 3rd electric capacity 14 is electrically connected between the drain electrode and ground connection of this transistor 11.The capacitance ratio of the 3rd electric capacity 14 and the second electric capacity 13 is exactly the loop gain of opening of reading circuit 1.This current sensor will charge to this first electric capacity 12, and convert an integral voltage that is proportional to this current sensor size and integral time to.
This first switch 15 has a first end that receives one first voltage VDD, and second end that is electrically connected to the drain electrode of this transistor 11, and controlled its first and second end that makes switches between conducting and not conducting.This second switch 16 has one and receives a reset voltage V
RESETFirst end, and second end that is electrically connected to the anode of the grid of this transistor 11 and this OPTICAL SENSORS 10, and controlled its first and second end that makes switches between conducting and not conducting.
The 3rd switch 17 has the second end that a first end and that is electrically connected on the drain electrode of this transistor 11 provides this output voltage VO UT.Above-mentioned switch 15～17 sequential operations of reading circuit 1 of resetting again can be consulted US6121843, therefore no longer describe in detail.
Yet generally, OPTICAL SENSORS 10 can be along bias voltage (N-on-P) type sensor or reverse blas (P-on-N) type sensor, and both reference bias COM sizes and current sensor direction are neither same.As reading circuit in Fig. 11, can only read from the current sensor along bias voltage (N-on-P) type sensor, can't read the current sensor from reverse blas (P-on-N) type sensor, therefore existing reading circuit 1 does not have the function that reads two kinds of bias voltage type sensors.
Summary of the invention
The object of the present invention is to provide a kind of double mode reading circuit that can read two kinds of bias voltage type sensors.
Another object of the present invention is to provide a kind of double mode reading device that can read two kinds of bias voltage type sensors.
Double mode reading circuit of the present invention is applicable to read the current sensor that a sensor produces, and comprises a condenser type and turn impedance amplifier and a Sample ﹠ hold device, and wherein, this condenser type turns impedance amplifier and comprises:
An integrating capacitor has one and is electrically connected to this sensor to receive the first end of this current sensor, reaches second end;
A first transistor has one and is electrically connected to the first end of first voltage source, the second end of second end that is electrically connected to this integrating capacitor, and a control end; And
A transistor seconds has one and is electrically connected to the first end in a second voltage source, the second end of second end that is electrically connected to this integrating capacitor, and a control end;
This Sample ﹠ hold device is electrically connected to the second end of this integrating capacitor, and the voltage of the second end of this integrating capacitor is taken a sample and kept;
This double mode reading circuit also comprises a switch, and this switch is electrically connected to the control end of this first transistor, the control end of this transistor seconds, the first end of this integrating capacitor, a tertiary voltage source and the 4th voltage source;
This double mode reading circuit switches between a first mode and second pattern, in this first mode, this switch is electrically connected to the control end of this first transistor the first end of this integrating capacitor, and the control end of this transistor seconds is electrically connected to the 4th voltage source, in this second pattern, this switch is electrically connected to this tertiary voltage source with the control end of this first transistor, and the control end of this transistor seconds is electrically connected to the first end of this integrating capacitor.
Double mode reading device of the present invention comprises the sensor of aforesaid double mode reading circuit and two kinds of different bias voltage types, and each sensor is for generation of a current sensor.
Beneficial effect of the present invention is: this double mode reading circuit and device operate in first mode and the second pattern by this switch, can be respectively used to read the sensor of two kinds of different bias voltage types.
Description of drawings
Fig. 1 is a kind of circuit diagram of existing reading device;
Fig. 2 is the circuit diagram of the preferred embodiment of the double mode reading circuit of the present invention;
Fig. 3 is that this preferred embodiment operates in the circuit diagram under a first mode;
Fig. 4 is that this preferred embodiment operates in the circuit diagram under one second pattern;
Fig. 5 is that this preferred embodiment operates in the sequential chart under this first mode;
Fig. 6 is that this preferred embodiment operates in the sequential chart under this second pattern.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, below in conjunction with accompanying drawing, the specific embodiment of the present invention is elaborated.At first need to prove, the present invention is not limited to following embodiment, and those skilled in the art should understand the present invention from the spirit that following embodiment embodies, and each technical term can be done the most wide in range understanding based on Spirit Essence of the present invention.In figure, same or analogous member uses the same reference numerals to represent.
Consult Fig. 2, the preferred embodiment of the double mode reading device of the present invention comprises the sensor 61,62 of two kinds of different bias voltage types and a pair of mode reads sense circuit 5.
In this preferred embodiment, sensor 61,62 is infrared sensor, after sensing infrared ray, will produce the photocurrent of corresponding size.Sensor 61 is a reverse blas type sensor, and sensor 62 is a suitable bias voltage type sensor.This sensor 61 has a negative electrode that receives a contrary reference bias COMPN, and the anode that current sensor output is provided.This sensor 62 has one and receives a negative electrode along reference bias COMNP, and the anode that current sensor output is provided. Sensor 61,62 also can be other current mode sensor elements, and for example the biological sensor of sensing variety classes biological ion, produce according to corresponding biological ion the current sensor that a size is proportional to the concentration of this biological ion.
This double mode reading circuit 5, be electrically connected on the sensor 61,62 of these two kinds of different bias voltage types, and read these two sensors 61,62 one of them these current sensor that produce, and this double mode reading circuit 5 comprises a condenser type and turns impedance amplifier 3, a Sample ﹠ hold device 4 and a switch 2.
This condenser type turns impedance amplifier 3 and comprises that an integrating capacitor 33, an integration reset switch 34, a first transistor 31 and a transistor seconds 32.This integrating capacitor 33 has first end and second end of anode to receive this current sensor that is electrically connected to this sensor 61 (or 62).This integration is reseted switch 34 and is parallel to this integrating capacitor 33, and controlled and switch between conducting or not conducting, and the electric charge that this integrating capacitor 33 is stored is removed when conducting.This first transistor 31 has one and is electrically connected to the first end of one first voltage source V 1, the second end of second end that is electrically connected to this integrating capacitor 33, and a control end.This transistor seconds 32 has one and is electrically connected to the first end of a second voltage source V2, the second end of second end that is electrically connected to this integrating capacitor 33, and a control end.In this preferred embodiment, this the first transistor is a p type field effect transistor, and the first end of this first transistor, the second end, control end are respectively source electrode, drain electrode, grid, and this transistor seconds is a n type field effect transistor, and the first end of this transistor seconds, the second end, control end are respectively source electrode, drain electrode, grid.This second voltage source V2 can provide common ground or other fixing current potentials.
This Sample ﹠ hold device 4 is used for the voltage of the second end of this integrating capacitor 33 is taken a sample and kept.This Sample ﹠ hold device 4 comprises that a sampling switch 41, one keep electric capacity 42, a maintenance to reset switch 43 and an output switch 44.This sampling switch 41 has the first end and second end that are electrically connected to the second end of this integrating capacitor 33.This keeps electric capacity 42 to connect with this sampling switch 41, and has a first end that is electrically connected to the second end of this sampling switch 41, and second end that is electrically connected to this second voltage source V2.This maintenance is reseted switch 43 and is parallel to this maintenance electric capacity 42, and controlled and switch between conducting or not conducting, and will keep the stored electric charge of electric capacity 42 to remove when conducting.This output switch 44 has a first end that is electrically connected to the second end of this sampling switch 41, and second end that this output voltage VO UT is provided, and controlled and switch between conducting or not conducting.
This switch 2 has first switch 21, a second switch 22, the 3rd switch 23 and the 4th switch 24.This first switch 21 has the first end and second end that are electrically connected to a tertiary voltage source V3.This second switch 22 has the first end of second end that is electrically connected to this first switch 21 and the second end of a first end that is electrically connected to this integrating capacitor 33.The common joint that this first switch 21 and this second switch are 22 is electrically connected to the control end of this first transistor 31.The 3rd switch 23 has the first end and second end that are electrically connected to the 4th voltage source V 4, and the 4th switch 24 has the first end of second end that is electrically connected to the 3rd switch 23 and the second end of a first end that is electrically connected to this integrating capacitor 33.The common joint that the 3rd switch 23 and the 4th switch are 24 is electrically connected to the control end of this transistor seconds 32.
This preferred embodiment is switched between a first mode and one second pattern, for sensor 61 and 62 one of them input and adjust suitable circuit read mode.When operating in first mode, be applicable to read reverse blas type sensor 61, and when operating in the second pattern, be applicable to read along bias voltage type sensor 62.
Consult Fig. 3 and Fig. 5, when operating in first mode, this second switch 22 and the 3rd switch 23 conductings, this first switch 21 and the 4th switch 24 not conductings (switch of not conducting and sensor 62 are not shown on figure).Therefore this switch 2 is electrically connected to the control end of this first transistor 31 first end of this integrating capacitor 33, and the control end of this transistor seconds 32 is electrically connected to the 4th voltage source V 4.The control end current potential of this first transistor 31 is for fixing, and this transistor seconds 32 is operating as an active load so that a current path to be provided.Before reading this current sensor, the remaining electric charge on integrating capacitor 33 is reseted 34 a period of times of switch by this integration of conducting in advance and is removed, and therefore when reading the action beginning, the first end of this integrating capacitor 33 and the second terminal potential are identical.The A direction of current sensor this moment in figure, current sensor will to integrating capacitor 33 chargings, cause the current potential of the second end of this integrating capacitor 33 to descend.The value that the current potential of the second end of this integrating capacitor 33 descends is equal to the cross-pressure of these integrating capacitor 33 2 ends, integral voltage Vint namely, shown in (one):
Wherein, parameters C int is this integrating capacitor value, and I (t) is current sensor, and parametric t I is the integral time of setting.
Integration is after a period of time, this 41 one sample times of conducting of sampling switch and this integral voltage is taken a sample.When sampling switch 41 conducting, this the first transistor 31 will provide electric current to keeping electric capacity 42 chargings, make to keep the first end current potential of electric capacity 42 to be promoted at short notice the identical current potential of the second end of integrating capacitor 33, and make two end spaies pressures of this maintenance electric capacity 42 be equal to this integral voltage.Then, change sampling switch 41 into not conducting after having taken a sample, and integration is reseted switch 34 and is changed the action that conducting one Preset Time is reset to carry out integrating capacitor 33 into.These output switch 44 conductings afterwards also provide this output voltage VO UT, and then, this maintenance is reseted switch 43 conductings one and removed sample time to remove the cross-pressure that keeps electric capacity 42.
Consult Fig. 4 and Fig. 6, when operating in the second pattern, this first switch 21 and the 4th switch 24 conductings, this second switch 22 and the 3rd switch 23 not conductings (switch of not conducting and sensor 61 are not shown on figure).Therefore this switch 2 is electrically connected to this tertiary voltage source V3 with the control end of this first transistor 31, and the control end of this transistor seconds 32 is electrically connected to the first end of this integrating capacitor 33.The control end current potential of this transistor seconds 32 is for fixing, and this first transistor 31 is operating as an active load so that a current path to be provided.Before reading this current sensor, the remaining electric charge on integrating capacitor 33 is reseted 34 a period of times of switch by this integration of conducting in advance and is removed, and therefore when reading the action beginning, the first end of this integrating capacitor 33 and the second terminal potential are identical.Current sensor this moment B direction in figure, current sensor will cause the current potential of the second end of this integrating capacitor 33 to rise to integrating capacitor 33 chargings, and the current potential rising value will be according to shown in formula ().
Integration is after a period of time, and this sampling switch 41, integration are reseted switch 34, output switch 44 and kept reseting switch 43 and will sequentially move according to the mode of above-mentioned first mode.The operation of this first mode and the second pattern is separately independently, thus all will complete the complete action of reading under the cycle separately, and the cycle of first mode and the second pattern does not overlap.
Double mode reading circuit of the present invention is above-mentioned double mode reading circuit 5.
In sum, when above-described embodiment operates in first mode, be applicable to read reverse blas type sensor 61, and when operating in the second pattern, be applicable to read along bias voltage type sensor 62, therefore really can reach purpose of the present invention.
Claims (10)
1. a double mode reading circuit, be applicable to read the current sensor that a sensor produces, and comprise a condenser type and turn impedance amplifier and a Sample ﹠ hold device, it is characterized in that, this condenser type turns impedance amplifier and comprises:
An integrating capacitor has one and is electrically connected to this sensor to receive the first end of this current sensor, reaches second end;
A first transistor has one and is electrically connected to the first end of first voltage source, the second end of second end that is electrically connected to this integrating capacitor, and a control end; And
A transistor seconds has one and is electrically connected to the first end in a second voltage source, the second end of second end that is electrically connected to this integrating capacitor, and a control end;
This Sample ﹠ hold device is electrically connected to the second end of this integrating capacitor, and the voltage of the second end of this integrating capacitor is taken a sample and kept;
This double mode reading circuit also comprises a switch, and this switch is electrically connected to the control end of this first transistor, the control end of this transistor seconds, the first end of this integrating capacitor, a tertiary voltage source and the 4th voltage source;
This double mode reading circuit switches between a first mode and second pattern, in this first mode, this switch is electrically connected to the control end of this first transistor the first end of this integrating capacitor, and the control end of this transistor seconds is electrically connected to the 4th voltage source, in this second pattern, this switch is electrically connected to this tertiary voltage source with the control end of this first transistor, and the control end of this transistor seconds is electrically connected to the first end of this integrating capacitor.
2. double mode reading circuit as claimed in claim 1 is characterized in that this switch comprises:
First switch and a second switch of series connection, this first switch is electrically connected to this tertiary voltage source, this second switch is electrically connected to the first end of this integrating capacitor, and a common joint between this first switch and this second switch is electrically connected to the control end of this first transistor; And
The 3rd switch and the 4th switch of series connection, the 3rd switch is electrically connected to the 4th voltage source, the 4th switch is electrically connected to the first end of this integrating capacitor, and a common joint of the 3rd switch and the 4th switch room is electrically connected to the control end of this transistor seconds;
In this first mode, this second switch and the 3rd switch conduction, this first switch and the 4th not conducting of switch, in this second pattern, this first switch and the 4th switch conduction, this second switch and the 3rd not conducting of switch.
3. double mode reading circuit as claimed in claim 1, it is characterized in that this first transistor is a p type field effect transistor, the first end of this first transistor is source electrode, the second end of this first transistor is drain electrode, the control end of this first transistor is grid, and this transistor seconds is a n type field effect transistor, and the first end of this transistor seconds is source electrode, the second end of this transistor seconds is drain electrode, and the control end of this transistor seconds is grid.
4. double mode reading circuit as claimed in claim 1 is characterized in that this condenser type turns impedance amplifier and comprises that also an integration in parallel with this integrating capacitor resets switch.
5. double mode reading circuit as claimed in claim 1 is characterized in that this Sample ﹠ hold device comprises:
Sampling switch of series connection and one keep electric capacity, and this sampling switch is electrically connected to the second end of this integrating capacitor, and this maintenance electric capacity is electrically connected to this second voltage source.
6. double mode reading circuit as claimed in claim 5 is characterized in that this Sample ﹠ hold device also comprises:
Switch is reseted in a maintenance, is parallel to this maintenance electric capacity.
7. double mode reading circuit as claimed in claim 5 is characterized in that this Sample ﹠ hold device also comprises:
An output switch is electrically connected to a common joint between this sampling switch and this maintenance electric capacity.
8. double mode reading device comprises the sensor of two different bias voltage types, a condenser type turns impedance amplifier and a Sample ﹠ hold device, and each sensor is characterized in that for generation of a current sensor, and this condenser type turns impedance amplifier and comprises:
An integrating capacitor has one and is electrically connected to these two sensors to receive the first end of these two one of them these current sensors that produced of sensor, reaches second end;
An integration in parallel with this integrating capacitor is reseted switch;
A first transistor has one and is electrically connected to the first end of first voltage source, the second end of second end that is electrically connected to this integrating capacitor, and a control end; And
A transistor seconds has one and is electrically connected to the first end in a second voltage source, the second end of second end that is electrically connected to this integrating capacitor, and a control end;
This Sample ﹠ hold device is electrically connected to the second end of this integrating capacitor, and the voltage of the second end of this integrating capacitor is taken a sample and kept;
This double mode reading device also comprises a switch, and this switch is electrically connected to the control end of this first transistor, the control end of this transistor seconds, the first end of this integrating capacitor, a tertiary voltage source and the 4th voltage source;
This double mode reading device switches between a first mode and second pattern, in this first mode, this switch is electrically connected to the control end of this first transistor the first end of this integrating capacitor, and the control end of this transistor seconds is electrically connected to the 4th voltage source, in this second pattern, this switch is electrically connected to this tertiary voltage source with the control end of this first transistor, and the control end of this transistor seconds is electrically connected to the first end of this integrating capacitor.
9. double mode reading device as claimed in claim 8 is characterized in that this switch comprises:
First switch and a second switch of series connection, this first switch is electrically connected to this tertiary voltage source, this second switch is electrically connected to the first end of this integrating capacitor, and a common joint between this first switch and this second switch is electrically connected to the control end of this first transistor; And
The 3rd switch and the 4th switch of series connection, the 3rd switch is electrically connected to the 4th voltage source, the 4th switch is electrically connected to the first end of this integrating capacitor, and a common joint of the 3rd switch and the 4th switch room is electrically connected to the control end of this transistor seconds;
In this first mode, this second switch and the 3rd switch conduction, this first switch and the 4th not conducting of switch, in this second pattern, this first switch and the 4th switch conduction, this second switch and the 3rd not conducting of switch.
10. double mode reading device as claimed in claim 9 is characterized in that this Sample ﹠ hold device comprises:
A sampling switch is electrically connected to the second end of this integrating capacitor;
One keeps electric capacity, connects with this sampling switch, and is electrically connected to this second voltage source;
Switch is reseted in a maintenance, is parallel to this maintenance electric capacity; And
An output switch is electrically connected to a common joint between this sampling switch and this maintenance electric capacity.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011104288476A CN103165168A (en) | 2011-12-19 | 2011-12-19 | Double-mode reading device and circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011104288476A CN103165168A (en) | 2011-12-19 | 2011-12-19 | Double-mode reading device and circuit |
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| CN103165168A true CN103165168A (en) | 2013-06-19 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109728813A (en) * | 2017-10-27 | 2019-05-07 | 瑞昱半导体股份有限公司 | Can elastic handoff candidate capacitor sample and hold |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63160353A (en) * | 1986-12-24 | 1988-07-04 | Oki Electric Ind Co Ltd | Semiconductor integrated circuit |
| US6121843A (en) * | 1999-06-04 | 2000-09-19 | Raytheon Company | Charge mode capacitor transimpedance amplifier |
| US7492399B1 (en) * | 2004-02-17 | 2009-02-17 | Raytheon Company | High dynamic range dual mode charge transimpedance amplifier/source follower per detector input circuit |
| WO2010135709A1 (en) * | 2009-05-21 | 2010-11-25 | Qualcomm Incorporated | Output circuit with integrated impedance matching, power combining and filtering for power amplifiers and other circuits |
-
2011
- 2011-12-19 CN CN2011104288476A patent/CN103165168A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63160353A (en) * | 1986-12-24 | 1988-07-04 | Oki Electric Ind Co Ltd | Semiconductor integrated circuit |
| US6121843A (en) * | 1999-06-04 | 2000-09-19 | Raytheon Company | Charge mode capacitor transimpedance amplifier |
| US7492399B1 (en) * | 2004-02-17 | 2009-02-17 | Raytheon Company | High dynamic range dual mode charge transimpedance amplifier/source follower per detector input circuit |
| WO2010135709A1 (en) * | 2009-05-21 | 2010-11-25 | Qualcomm Incorporated | Output circuit with integrated impedance matching, power combining and filtering for power amplifiers and other circuits |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109728813A (en) * | 2017-10-27 | 2019-05-07 | 瑞昱半导体股份有限公司 | Can elastic handoff candidate capacitor sample and hold |
| CN109728813B (en) * | 2017-10-27 | 2022-10-14 | 瑞昱半导体股份有限公司 | Sample-and-hold amplifier capable of flexibly switching candidate capacitor |
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Application publication date: 20130619 |