JPS63158628A - Detection system for duplication of bit pattern - Google Patents

Abstract

PURPOSE:To reduce storage areas and to attain duplication detection economically and at high speed by detecting a duplicated and same bit pattern from significant bit patterns and data bit patterns with respect to respective bit patterns. CONSTITUTION:For checking a same name among respective bit patterns stored in a bit pattern storage part, a data bit pattern D1 and a significant bit pattern S1 are set in a block 30, and a data bit pattern D2 and a significant bit pattern S2 are set in a block 31. Firstly, the bit patterns S1 and S2 are inputted to an AND circuit 21, and their 'AND' 1110 is outputted. The output of the 'AND' is inputted to AND circuits 23 and 25 in which the 'AND' with the bit patterns D1 and D2 are respectively operated and are inputted to a comparator 27 which checks whether both are equal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a bit pattern duplication detection method that efficiently detects the same bit pattern from among a plurality of bit patterns.

BACKGROUND OF THE INVENTION In digital hardware design or computer software design, it is often the case that different operations are performed depending on the value of certain data or the bit pattern of data. For this purpose, it is necessary, for example, to examine all bit patterns of input data and compare them with a predetermined bit pattern to check whether any of them are the same. Here, the format of the bit pattern of the input data is simply one bit pattern, a set of bit patterns within a specified interval, and a number of bit patterns when considered as a binary bit pattern. It is conceivable that only the bit in a particular position is specified, and the other bits are redundant bits, that is, include don't cares as represented by don't care bits, but in any case, such bits It is necessary to check whether the same bit pattern exists in a set of patterns, or to check that such a set of bit patterns does not contain the same value.

In order to perform this check, conventionally, if the maximum length of the input bit pattern is n, then 2n bit storage areas each corresponding to all possible bit patterns of n bits, that is, 21 bit patterns, are stored. , and for each bit pattern entered, set "1" to the bit position of the bit storage area corresponding to the binary number.
is stored and marked as registered, and it is checked whether the same bit pattern exists by duplication of this registered mark.

In this method, however, when n becomes large, 21
The storage area for one bit becomes very large, making it difficult to secure this area, and it also takes a considerable amount of time to generate all the individual bit patterns contained in a bit pattern that includes many don't cares. Become.

In addition, in the case of a set of intervals with a bit pattern that does not include don't cares, the lower limit fln and upper limit un of each interval are memorized, and the lower limit and upper limit of a given interval are set as f(, u) to detect overlap. , fLn <
If you check whether there are overlapping sections by checking that u or un < fl, sections that satisfy this condition will not overlap, and sections that do not satisfy this condition will not include duplicates. I can see that it is.

In order to extend this method to bit patterns that include don't cares, it is necessary to convert the bit patterns that include don't cares into several sets of intervals and apply it, but if there are n don't care bits, generally 2n Therefore, it takes time to generate these 2n intervals, and it is also difficult to secure an area to store these intervals.

(Problems to be Solved by the Invention) As described above, each of the above-mentioned methods has the problem of being uneconomical because the storage area becomes considerably large and it takes a long time.

The present invention has been made in view of the above, and its purpose is to provide a bit pattern duplication detection method that can detect duplicate bit patterns at high speed with a small storage area, economical and simple configuration. It's about doing.

[Structure of the Invention] (Means for Solving the Problems) In order to solve the above problems, a second set including a second bit pattern is selected from a first set including a plurality of first bit patterns. A bit pattern duplication detection method for detecting a bit pattern that is the same as a bit pattern in each set, the present invention includes a first converting means for converting each bit pattern in each set into a bit pattern including redundant bits. and a second converting means for converting each of the bit patterns into a significant bit pattern in which redundant bits are replaced with O's and other bits are replaced with 1's, and only the redundant bits are replaced with O's and the other bits are left unchanged. third converting means for converting each of the bit patterns into a data bit pattern, and converting the significant bit pattern and data bit pattern for each bit pattern of the first set and the second set into the same bit pattern. The gist is to have a detection means for detecting.

(Operation) In the bit pattern duplication detection method of the present invention, each bit pattern is converted into a bit pattern including redundant bits, and the redundant bits of each bit pattern are replaced with O's and the other bits are replaced with 1's. Convert each bit pattern into a bit pattern, and convert each bit pattern into a data bit pattern in which only redundant bits are replaced with 0 and other bits remain unchanged, and from the significant bit pattern and data bit pattern for each bit pattern. Duplicate and identical bit patterns are detected.

(Example) Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a block diagram showing a circuit configuration of a bit pattern duplication detection method according to an embodiment of the present invention. The bit pattern duplication detection method shown in the figure includes an overall control section 1, a bit pattern manual buffer 2, a bit pattern conversion section 3,
It is composed of a bit pattern detection section 4, a bit pattern registration section 5, an input number storage buffer 76, a converted bit pattern output buffer 7, and a bit pattern storage section 8.
Before explaining each of these parts, the basic principle of the present invention will be explained.

The basic principle of the bit pattern duplication detection method of the present invention is:
The latter method of the conventional methods described above, that is, the method of expanding to a bit pattern that includes don't cares, is the opposite of converting a bit pattern specified by an interval into a string of bit patterns that includes don't cares, and converting the bit pattern that includes this don't care. This method converts a pattern into a significant bit pattern and a data bit pattern as described later, and attempts to detect logically overlapping and identical bit patterns from the significant bit pattern and data bit pattern.

Now, assuming that the given interval is [1, u], this can be expressed as a set of sums of subintervals that do not overlap with each other as follows.

, and the lower ni bits of fLi are all O.

To give a specific example, for example, 2 bits of 4 bits.
There are nine numbers defined in the interval [2,101] between base 2 and 10: 2.3.4, 5.6.7.8.9.10,
Considering these in binary numbers, 0010.0011.01
00.0101゜oiio, o1'z, 1ooo, 1o
oi.

This is a 9-bit pattern. Divide these bit patterns into subintervals using the general expression described above,
In order to clearly show the definition of division, common parts that are not considered don't care are underlined.

[QO0,0101,LLIO, Company 111゜[1000
,1001], [10101 or [2,3], [4,5,6,7], [8,9]
.

[10] It can be divided into four partial subintervals as shown in [10], and is expressed by the union set shown in the following equation.

[2,10]-[2,3]U [4,5,6,7]U[
8,9]U[10] Such a subinterval [ii, ui] defines love i as d H
・dki O...O (O is n1), ui is d
Since it can be expressed as l...dki 1...1,
If the don't care bits represented by "0" and "1" are expressed as "?", then d1・dki? =・? (?
can be expressed as one bit pattern of the form ni).

Therefore, the union equation [2, 10] becomes as follows.

[2,10]-001? UO1? ? U100? That is, if we express the union using don't care in this way, for example, a set of 9 numbers such as [2, 10] becomes 0017. as expressed by the expression of this union. 0
1? ? , 100? .

It can be represented by four pieces consisting of 1010, and the number can be reduced. When this is converted into a -film, the number of such partial subintervals for arbitrary l and u is expressed by the following equation.

1+210(12(u-love+1)) Therefore, the storage area required to store an interval as a sum of partial subintervals including don't cares can be sufficiently small, making it economical.

Furthermore, since the time required to convert into partial subintervals including don't cares in this way is proportional to the number of partial subintervals to be converted, the conversion time is naturally increased.

After converting into a set of bit patterns that include don't cares as described above, in order to detect whether or not the same bit pattern as a predetermined bit pattern exists redundantly in the set of bit patterns, it is necessary to First, each bit pattern containing .

That is, the data bit pattern Di for each bit pattern including don't care bits is
The significant bit pattern 3i is created by replacing the don't care with O and leaving the other bits as is.
It is created by replacing the other bits with 1 and replacing the other bits with 1. - As an example, the bit pattern rlo? containing a don't care "?" ? 1? The data bit pattern of J is “10
0010J, and the significant bit pattern is “11001
It becomes 0J.

In this way, each bit pattern is converted into data bit pattern D
After converting into a pair of bit patterns consisting of i and significant bit pattern 3i, now the data bit pattern of one bit pattern P1 inputted from the outside to be detected for duplication is set to 01, the significant bit pattern to 81, In addition, the data bit pattern of the other bit pattern P2 is set to D.
2. Assuming that the significant bit pattern is 82, both bit patterns S+ and 82 are (D+, S+) and (D2
When expressed as ゜32〉, both pit patterns P+,
The condition that P2 is the same in duplicate is the first logical product S+
&S2 &DI and second logical product 81 &S2 &D2
are the same. That is, expressed as the following equation.

81 &S2 &DI -8+ &S2 &D2...
(1) Here, & represents a logical product for each bit.

That is, as shown in the above equation, when the first AND and the second AND are equal, it is possible to determine that both bit patterns are the same. It is believed that this logical product relationship will be more clearly understood from the explanation of FIG. 2, which will be described later.

In the bit pattern duplication detection method shown in FIG. 1 of the present invention, which is implemented according to the basic principle as explained above, each part is controlled as a whole under the control of the overall control section 1, and duplication is detected. The bit pattern input from the outside is temporarily stored in the bit pattern manual buffer 2. The type of the bit pattern represented by an interval stored in the bit pattern manual buffer 72 is determined by the overall control unit 1, and if it is a bit pattern represented by an interval,
As described above, the bit pattern converter 3 converts the string into a bit pattern including don't cares, and temporarily stores it in the changed bit pattern output buffer, and in other cases, outputs the converted bit pattern directly from the bit pattern manual buffer 2. It is stored in buffer 7. In either case, a bit pattern including don't care is represented and stored as a pair of bit patterns consisting of the data bit pattern and the significant bit pattern. In order to identify the bit pattern input to the bit pattern manual buffer 72, an input number is added and stored in the input number storage buffer 6. In this case, the input number storage buffer 7
6 is 0 in the initial state, and is incremented by 1 each time a bit pattern is given from the outside. In addition, all the bit patterns that have been input so far are stored in the bit pattern storage unit 8, and the bit patterns stored in this bit pattern storage unit 8 correspond to input numbers as shown in the memory configuration in the following table. Each correspondingly consists of a data bit pattern and a significant bit pattern.

As described above, each bit pattern converted into a bit pattern including don't care and stored in the converted bit pattern output buffer 7 is sequentially processed in the bit pattern detection unit 4 with each bit pattern stored in the bit pattern storage unit 8. That is, they are compared to see if they are equal according to the logical operation of equation (1) described above, and when it is detected that both bit patterns are equal, this is notified to the overall control unit 1 along with the corresponding input number. It will be done. When the overall control unit 1 receives the notification of detection, it notifies the outside, and if not, that is, if they are not equal, the bit pattern registration unit 5 uses the bit pattern stored in the converted bit pattern output buffer 77. and the corresponding input number stored in the input number storage buffer 6 are registered in the bit pattern storage section 8, and the registration is notified to the outside.

In this way, the bit pattern detection unit 4 compares both bit patterns according to the logical operation of equation (1) and identifies whether or not they are the same bit pattern. The operation will now be explained with reference to FIG.

The bit pattern detection section 4 shown in FIG. 2 compares the first bit pattern P1 from the bit pattern storage section 8 and the second bit pattern P2 from the converted bit pattern output puffer 7, and finds that both bit patterns are equal. In order to determine whether or not the data bit pattern D1 and the significant bit pattern S1 of the first bit pattern P1 and the second
The logical operation of the previous formula (1), that is, 31 &S2 &D+ =S+ &S2 &D2, is performed on the data bit pattern D2 and the significant bit pattern P2 of the bit pattern P2, and it is determined whether the two bit patterns are equal. be.

For this reason, the bit pattern detection unit 4 in FIG. The logical product output S of the AND circuit 21 of
+ &S2 and the first data bit pattern D1
The second AND circuit 23 that calculates the logical product Sl &S2 &D1 and the logical product output 81 of the first AND circuit 21
A third AND circuit 2 that calculates the second logical product S1&S2 &D2 of &S2 and the second data bit pattern D2
5 and the first logical product 81 &S2 from the second circuit 23
&D1 and the second logical product 8 from the third AND circuit 25
Comparator 2 that compares whether 1 &S2 &D2 are equal.
7, and when it is determined that both bit patterns are the same as a result of the comparison in the comparator 27, the comparator 2
7 outputs a signal of "1". In FIG. 2, the rectangular blocks indicated by 30 to 34 are shown simply to clearly show the target bit patterns and calculation results, and do not require any particular hardware circuit elements. Although it may be connected directly, depending on the case, a resistor or the like may be used.

The operation of the device configured as described above will be explained by giving a specific example.

As an example, a bit pattern of n=4 bits [2,4]
, [7, IOJ, 011? A case will be described in which the overlap between the two is detected.

The interval [2,4] is 2 (0010), 3 (○011 >
, 4 (0100), and these are treated as don't care (
? ), 001? ,oi.

It is represented by the union of O, and the ward HE7, 10] is
7 (0111), 8 (1000), 9 (1001
), 10 (1010), expressed using don't care, 0111.100? , 1010.

Now, here we have already checked for overlap between [2,4] and [7,10] and found that there is no overlap, and the decomposed or transformed data bit pattern and significant bits of each bit pattern. It is assumed that the pattern is stored in the bit pattern storage section 8 shown in FIG. 2 as shown. Then, the 1.2 bit pattern, which is each bit pattern of [2.4], [7, and 10 bits, decomposed into a data bit pattern and a significant bit pattern and stored in the bit pattern storage unit 8 in this way. On the other hand, the third bit pattern 011? Which duplicates are checked in the bit pattern detection section 4.

In this state, the first and second bit patterns from the bit pattern storage section 8 are sequentially set in the block 30 shown in FIG. 2, and the third bit pattern 011? is set in the block 31. is set, and both bit patterns are checked for overlap by the bit pattern detection section 4.

In addition, to explain the bit pattern decomposed into a data bit pattern and a significant bit pattern and stored in the bit pattern storage unit 8, first, the input number (1
), the bit pattern 00 of [2°4]
1? A data bit pattern 0010 and a significant bit pattern 1110 for the input number (2) are stored, and a data bit pattern 0100 and a significant bit pattern 1111 for the bit pattern 0100 of [2,4] are stored in the location corresponding to the input number (2). In the place corresponding to number (3), data bit pattern o111 and significant bit pattern 11 for bit pattern 0111 of [7, 10]
11 is memorized, and in the place corresponding to the input number (4), [
7, 10] bit pattern 100? A data bit pattern 1000 and a significant bit pattern 1110 are stored, and furthermore, [7] is stored at the location corresponding to the input number (5).
, 10], a data bit pattern 1010 and a significant bit pattern 1111 are stored.

Then, each bit pattern stored in the bit pattern storage unit 8 in this way is sequentially processed by the bit pattern detection unit 4 from the input number (1) to the third bit pattern 011? is compared to check for duplicates. Input number (1) among the bit patterns stored in the bit pattern storage unit 8.

The comparison result for (2) is that the two are not the same, so
The output from the comparator 27 of the bit pattern detection section 4 is rO
J, the next input number is (3), and from among the bit patterns stored in the bit pattern storage unit 8, the bit pattern 0111 of the input number (3) and the third bit pattern 011? When it comes to checking for overlap, that is, identity, the data bit pattern D1 (0111) for the bit pattern 0111 of input number (3) and the significant bit pattern 82 (1111) are stored in the block 30 as shown in the figure. set and also block 31
The third bit pattern O11? data bit pattern D2 (0110) and significant bit pattern 82 (
1110) is set. First, the bit patterns S1 and 82 are input to the first AND circuit 21, and the logical product 81 &S2 of the two, rllllc)J, is output.

This AND output is input to the second AND circuit 23 and the third AND circuit 25, and the bit pattern D1
The logical product of and D2 is calculated. That is, the second AND circuit 23 outputs rolloJ, which is the first logical product 81 &S2 &Dt, and the third AND circuit 25 outputs rolloJ, which is the second logical product S+ &S2 &D2.
oJ is output, and each of these AND outputs is input to a comparator 27, and it is checked whether the two are equal or not.

As a result, since the filling outputs of both wheels are equal, a signal of "1" is output from the comparator 27, and the existence of overlap is detected.

[Effects of the Invention] As described above, according to the present invention, each bit pattern is converted into a bit pattern including redundant bits, and the redundant bits of each bit pattern are replaced with O's and the other bits are replaced with 1's. At the same time, each bit pattern is converted into a data bit pattern in which only redundant bits are replaced with 0 and other bits remain unchanged, and the significant bit pattern and data bits for each bit pattern are converted into a data bit pattern. Since we are detecting duplicate and identical bit patterns from the pattern,
By converting the bit pattern to a bit pattern that includes redundant bits in this way, the number of subintervals to be expanded can be significantly reduced, so it requires less storage space and can detect duplicate identical bit patterns economically and quickly. can do.

[Brief Description of the Drawings] Fig. 1 is a block diagram showing the circuit configuration of a bit pattern duplication detection method according to an embodiment of the present invention, and Fig. 2 shows bits used in the bit pattern duplication detection method of Fig. 1. FIG. 3 is a circuit diagram of a pattern detection section. 3...Bit pattern conversion section 4...Bit pattern detection section 8...Bit pattern storage section

Claims (2)

[Claims] (1) A bit pattern duplication detection method that detects a bit pattern that is the same as a bit pattern in a second set that includes a second bit pattern from a first set that includes a plurality of first bit patterns; a first converting means for converting each bit pattern in each set into a bit pattern including redundant bits; and a first converting means for converting each bit pattern in each set into a bit pattern including redundant bits; a second converting means for converting a bit pattern; and a third converting means for converting each bit pattern into a data bit pattern in which only redundant bits are replaced with 0 and other bits remain unchanged.
and a detection means for detecting the same bit pattern from the significant bit pattern and data bit pattern for each bit pattern of the first set and the second set, respectively. Detection method. (2) The detection means detects a first logic of a significant bit pattern of the first set of bit patterns, a significant bit pattern of the second set of bit patterns, and a data bit pattern of the first set of bit patterns. when the product is equal to a second logical product of the significant bit patterns of the first set of bit patterns, the significant bit patterns of the second set of bit patterns, and the data bit patterns of the second set of bit patterns; 2. The bit pattern duplication detection method according to claim 1, further comprising identification means for identifying that both bit patterns are the same.