JPS5842892B2 - error correction device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides an error correction device, particularly a soil correction device that performs one-burst block error correction/two-burst block error detection, in which an error exists in one block. The present invention relates to an error correction device that is capable of automatically correcting the error in the remaining one block when a two-burst block error including the block occurs when the block is known.

Conventionally, error correction devices have used SEC/DEC Hamming codes that perform 1-bit error correction and 72-bit error detection.

However, in the case where a plurality of bits are stored in one memory element, the plurality of bits are made into one block, and one word is constituted by such plural blocks, the above SEC/DEC code If a failure occurs in a unit, error correction cannot be performed.

For this purpose, the "b-adjacent error correction code J (D-C, Bossens") is used as a code that can correct any error in one block (b bits).
djacent error correction”
IBMJ-Res Develop, vol.
14, &4 + pp 402-409.1970
) has been developed.

Furthermore, a code has been developed that can correct any error in one block and detect any error in two blocks (Japanese Patent Laid-Open No. 49-22057).

The present invention focuses on the fact that when a memory device is configured with a plurality of memory elements, there is a high possibility that one memory element will permanently become a failure. The purpose is to automatically correct errors in two blocks including the block when the block is known.

Therefore, the error correction device of the present invention employs a 1-burst block error correction/2-burst block error detection code for a code word having multiple blocks, each block consisting of b bits. ,
In an error correction device that applies a check matrix to given data to extract syndrome information and perform error correction/detection, when it is known that an error exists in one block, the position information of that block is stored. An error pointer, a syndrome generator that applies a check matrix to the given data to extract syndrome information, and receives syndrome information from the syndrome generator to perform correction for one burst block error; Further, a one-block error correction device receives error block position information from the error pointer and generates pattern information determined based on the error block position information and the supplied syndrome information. , an error block number determination device, and error block position information from the error pointer; syndrome information from the syndrome generator; and pattern information from the one-block error correction device; By performing predetermined arithmetic processing, the error patterns of the block given by the contents of the error pointer and the remaining error block are extracted, and the position information of the remaining error block is extracted and the error pattern is extracted. A 2-block error correction device is provided to perform error correction for the other 1 block that has generated 1 burst block error, and performs 1 burst block error correction/2 burst block error detection. The system is characterized in that it is configured to automatically correct a two-burst block error that includes a given block.

This will be explained below with reference to the drawings.

FIG. 1 is an explanatory diagram summarizing relational expressions corresponding to errors spanning two blocks when the first type of inspection matrix used in the present invention is applied, and FIG. 2 is an overall diagram of one embodiment of the present invention. 3 shows the configuration of an embodiment of the 1-block error correction device used in the present invention, FIG. 4 shows the configuration of an embodiment of the 2-block error correction device used in the present invention, and FIG. 5 shows the configuration of an embodiment of the 2-block error correction device used in the present invention. FIG. 6 shows the configuration of another embodiment of the two-block error correction device, FIG. 6 shows the configuration of one embodiment of the error block number discriminating device, and FIG. Figures 8 to 10
The figures each show an embodiment of the configuration in which slight changes are made from the above-mentioned FIGS. 2 to 7 when other types of inspection matrices used in the present invention are applied.

A scheme using two types of test matrices is disclosed herein.

First, a method using the first type of inspection matrix will be explained.

The following matrix is used as the first type of inspection matrix (hereinafter referred to as H matrix).

That is, it is given by.

In the above, αi represents a vector created modulo a specific primitive polynomial of order b.

For example, syndrome information S is obtained by applying the above H matrix to data read from a storage device, and the syndrome information is generally expressed as follows.

Suppose that a two-block error is detected by the error block number discriminating device as shown in FIG. 2, which will be described later.
It goes without saying that the error correction device performs one burst block error correction/two burst block error detection.

Since this point is well known, the explanation will be omitted. For example, it is known that an error exists in the first block, and when an error occurs in two blocks including this block, in the remaining jth block (j is unknown). ) Describes error correction.

In addition, in the above, O≦1≦2b+1. O≦j≦2b+
1. Let i be the main j.

Then, the error in the first block at that time
Let the pattern be ei, and the error pattern in the j-th block be ej.

Now suppose that two error blocks are in the information bit part, that is, O≦i≦2b−2゜O≦j≦2b−
2, the following equation holds.

Incidentally, the relational expression including the case where two error blocks are in the check bit portion will be described later with reference to FIG.

That is, if two error blocks are in the information bit part, then in the above relational expression, the known numbers are i, So, and Sl.

Since it is S2, u i *V i is found, therefore, X that satisfies equation (8) is found, and the unknown value j is found from the α-th wipe.

Once X is found, ej is found from equation (9), and 64 is found from the αth equation.

By determining each of these, it becomes possible to automatically correct an error spanning two blocks including a known error block.

Note that instead of the above equation (8), T”u > ” v i
, it goes without saying that e·=r2XvH can be used instead of Equation (9).

A similar relational expression is obtained when one or two of the two error blocks are in the check bit portion.

This relational expression is summarized in FIG.

In the figure, when the error block position is i≦2b-2 and j≦2b-2, the above (8) to α
I am responding to my people.

set and i or j is 2b-1 or 2b or 2b+1
, it represents the case where one or two of the error blocks are in the check bit part.

When constructing an error correction device, if the configuration does not require error correction for check bits, it is sufficient to use only part of the relational expression shown in FIG.

Furthermore, when using an H matrix in which check bits are not separated, as in the specific example described below, processing can be performed simply by using equations (8) through α-th above.

We will continue to explain the specific example (44, 32) code when using the first type of H matrix.

The following H matrix is used for this code.

To encode this code, an H matrix is used in which the check bit portion is separated by performing an operation between the rows of the H matrix α.

FIGS. 2 to 7 show the configuration of an embodiment of the present invention in the case of using the H matrix shown in the above-mentioned test a.

FIG. 2 shows the overall configuration, in which 1 is the main memory, 2 is an error pointer created by the present invention, and when it is known that an error exists in one block, the position information of the block, i.e. The one where the value "i" is stored,
3 is a syndrome generator which generates syndrome information S by applying the above-mentioned H matrix to the data read from the main memory 1; 4 is a 1-block error correction device which corrects conventionally known errors; 5 corresponds to a device for performing 1-burst block error correction/2-burst block error detection in a correction device; 5 is a 2-block error correction device produced according to the present invention;
Reference numeral 6 is an error/block number discriminator that determines "no error", "11 block error" and "2 block error".
and 7 is an error data inversion device which inverts error bits in the data read from the main storage device 1 based on the information from the devices 4 and 5. It represents what you do.

The syndrome generator 3 is composed of a tree circuit composed of exclusive OR (XOR).

In the error pointer 2, the position information of the plot when an l-block fault actually exists is stored as one address, and is used when a two-block error is detected.

Although not shown in the diagram, when a 1-block error is detected, comparing the block position with the contents of error pointer 2 can be useful for determining whether it is a 1-block failure or a 2-block failure. can.

An overview of the processing performed by the configuration shown in FIG. 2 is as follows.

That is, (1) using the data read from the main memory 1, the syndrome generator 3 generates syndrome information.

(2) The error/block number determining device 6 determines "no error", "1 block error", and "2 block error" based on the above syndrome information.

(3) The 1-block error correction device 4
In case of an error, the corresponding 1 block address and 1 block error pattern are generated and supplied to the error data inverter 7.

In the case of the present invention, the 1-block error correction device 4 receives the i address from the error pointer 4, generates pattern information J and Vt when there is a 2-block error, and
2 block error correction device 5.

(4) The two-block error correction device 5 has a memory address,
“2 block error J signal, syndrome S.

, receives the above pattern information ui and V4, and detects the error.
When a 2-block error occurs, including the block indicated by the contents of pointer 2, the information necessary for error correction is 1sei.
*j*ej is supplied to the error data inverter 7.

(5) The error data inversion device 7 corrects the data a read from the main storage device 1 based on the supplied information, and outputs "corrected data".

The configuration of the illustrated one-block error correction device 4 is shown in FIG.

The illustrated symbols 10, 11, 12, 13, and 14 correspond to those in FIG.

When an l block error exists, the signal 11-
One of 0 to 11-10 is a logic "1".

Also, when an l block error actually exists, pattern information ui, V, etc. is selected by one of the signals 10-0 to 10-10 from error pointer 2 and output to output line 13.14. .

The figure shows a system in which circuits corresponding to blocks #0 to #10 are provided in parallel, that is, a parallel processing system.

However, by using shift registers etc.
It is also possible to adopt a serial processing method for each block.

The configuration of the error block number determining device shown in FIG. 2 is shown in FIG.

Reference symbols 11°, 12.20, and 21.22 in the figure correspond to those in FIG.

When the syndrome information S is all logic "O", it is determined that there is no error, and bits 11-0 to 11-
When there is a logic “1” in any of the 10, “1 block
If all bits 11-0 to 11-10 are logic "0" and a part of the syndrome information is logic "1", it is determined to be a "two-block error".

Although not shown, it is possible to perform other combinations of the syndrome information S and the output 11 of the one-block error correction device 4 to further improve the ability to determine the number of error blocks.

The configuration of the two-block error correction device 5 shown in FIG.
This is shown in FIG. 4 or FIG.

FIG. 4 shows an embodiment corresponding to serial processing, and the fifth
The figure shows an embodiment that supports parallel processing.

Codes in the diagram: 10.12, 13, 14, 15° 16.17
corresponds to Fig. 2.

In FIG. 4, an exclusive OR circuit 44 and a NOR circuit 4
Step 5 determines whether equation (8) holds.

That is, the latch 41 receives the pattern information v1 and obtains T-Xvi via the multiplier circuit 43, and the exclusive OR circuit 44 obtains T-Xvi.
).

On the other hand, the output of the latch circuit 40 shows an error pattern ej according to equation (9).

Further, the output of the exclusive OR circuit 46 shows an error pattern ei due to the αQth element.

Also, 51* shift registers are x' + x + 1
A circuit that multiplies X with
The location of the remaining error block is determined and one of the location information 17-b to 17-10 is accessed.

In FIG. 5, the circuit shown in FIG. 4 is provided for each block, with an exclusive OR circuit 62 and a NOR circuit 6.
4, it is determined whether equation (8) holds.

Then, operations similar to those in the case of using the shift register 51 in FIG. 4 are performed in parallel for each block.

The configuration of the error data inversion device shown in FIG. 2 is shown in FIG.

FIG. 7 shows data a of the Oth block read from the main storage device 1.

shown as against.

And the symbols shown are 10°11, So, 15, 16.1
7 corresponds to FIG.

In the case of one block error, the data corrected by the AND circuit 90-0 and the exclusive OR circuit 91-0 is "corrected a.

” is obtained. Furthermore, in the case of a 2-block error that includes the block designated by error pointer 2, the exclusive OR circuit 95-0 finally obtains the corrected acLJ.

Next, a case where the second type of H matrix is used will be explained.

When using the first type of H matrix, the word length is determined based on the number of bits per block,
This is not always sufficient when the word length is large.

Therefore, in the second type H matrix, the number of check bits is increased by one block in the first type H matrix, so that it can correspond to twice the word length.

That is, the second type H matrix is, so to speak, an expanded H matrix with respect to the first type H matrix.

The second type H matrix is expressed as follows.

That is, although Equation 0 creates an H matrix by shifting the unit matrices in the first half and the second half of the information bit portion, it goes without saying that it can be used similarly for H matrices created by shifting other parts.

That is, even if the second type H matrix is used, error correction can be easily performed by using an H matrix that does not separate the check bit portion, as in the case of using the first type H matrix.

An example of the (88, 72) code for the second example will be shown below.

The H matrix used in this code is expressed as follows.

A case in which an H matrix (base) is used will be specifically explained below.

The block positions will be described as #0 to #21 from the left end.

When using the second type of H matrix, upper = aA)
Each relational expression between rx and 0 holds true.

To encode this code, an H matrix is used in which check bits are separated by performing an operation between the rows of the H matrix (15).

The configuration using the second type of H matrix also has the same configuration as shown in FIG.

In order to deal with each of the above cases (A) to 0, it is sufficient to make some changes to the configurations shown in FIGS. 3 to 7.

First, in FIG. 3, input S.

(12-0) as an input as shown in Figure 8.
.

(2) S/(12-3) is used.

In the figure, the signal 101 becomes logic (1) when the error pointer 2 shown in FIG. It's a signal.

Also, signal 102 is an error. This signal becomes logic "1" when pointer 2 indicates "no error block" or "11th to 21st blocks are in error".

Furthermore, when using the second type of H matrix (15), when error pointer 2 indicates that "the 0th block or the 11th block is in error", the bit signal 10-0 shown in FIG. When the bit signal 10-1 becomes logic "1" indicating that "the first block or the twelfth block is in error", the bit signal 10-1 shown in FIG. 3 becomes logic "1", and so on.

When using the second type H matrix (15),
The discriminating device shown in FIG. 9 is used instead of the discriminating device shown in FIG. 6 above.

Furthermore, in the configurations shown in FIGS. 4 and 5, the signals 10-b to 10-10 are changed as shown in the explanation of the changes to FIG. 3 above.

That is, when indicating that "the first block or the 11th+l block is in error", the bit signal 10-1 becomes the logic "
1”.

Further, S shown in FIGS. 4 and 5.

S instead of (12-0). ■Sj is used.

Whether each data block is to be corrected is controlled by outputs 110-120 shown in FIG.

For example, the OR circuit network 52 in FIG. 4 or the OR circuit network 72 in FIG. 5 is changed so that when the output 113 shown in FIG. 9 is logic "1", it becomes logic r01.

Further, instead of the configuration shown in FIG. 7, the configuration shown in FIG. 10 is used.

As explained above, according to the present invention, when it is known in advance that an error exists in one block, even if it becomes a two-block error, it is possible to automatically correct each of the two blocks. becomes possible.

In the above description, an H matrix is shown in which the number of bits in one block is "4", but b is not necessarily limited to the value "4".

It is free to change the configurations shown in FIG. 2 and later to use an H matrix with a check bit part added.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram summarizing relational expressions corresponding to errors spanning two blocks when the first type of inspection matrix used in the present invention is applied, and FIG. 2 is an overall diagram of one embodiment of the present invention. 3 shows the configuration of an embodiment of the 1-block error correction device used in the present invention, FIG. 4 shows the configuration of an embodiment of the 2-block error correction device used in the present invention, and FIG. 5 shows the configuration of an embodiment of the 2-block error correction device used in the present invention. Another embodiment of the configuration of the 2-block error correction device, FIG. 6 shows the configuration of an embodiment of the error block number discriminating device, and FIG. 7 shows the configuration of an embodiment of the error data inversion device used in the present invention. , Figures 8 to 10
The figures each show an embodiment of the configuration that is slightly modified from the above-mentioned FIGS. 2 to 7 when other types of inspection matrices used in the present invention are applied. In the figure, 1 is the main memory, 2 is the error pointer, 3 is the syndrome generator, 4 is the 1-block error correction device, and 5
2 represents a block error correction device, and 6 represents an error block number determination device.

Claims (1)

[Claims] 1. A 1-burst block error correction/2-burst block error detection code is adopted for a code word having multiple blocks, each block consisting of b bits. In an error correction device that extracts syndrome information and performs error correction/detection by applying a check matrix to the data, when it is known that an error exists in one block, the error correction device stores the position information of the block. A pointer, a syndrome generator that extracts syndrome information by applying a test matrix to the given data, and a syndrome generator that receives the syndrome information from the syndrome generator and generates one burst block.
Correcting the error, receiving error block position information from the error pointer, and generating pattern information determined based on the error block position information and the supplied syndrome information. l block error correction device, error block number determination device, and error correction device from the above error pointer.
By receiving the block device information, the syndrome information from the syndrome generator, and the pattern information from the one-block error correction device, and performing predetermined arithmetic processing on these pieces of information, the error pointer is given by the contents of the error pointer. The error patterns of the error block and the remaining error block are extracted, and the error pattern of the remaining error block is extracted.
It has a 2-block error correction device that extracts the position information of one error block and performs error correction for the other block that has an error, and performs 1-burst block error correction/2-burst block error correction. An error correction device characterized in that it is configured to detect and automatically correct a two-burst block error that includes a block given by the contents of the error pointer. 2 The syndrome generator is configured to generate syndrome information using a test matrix suitable for performing 1-burst block error correction/2-burst block error detection, or a matrix in which a part of the test matrix is omitted. An error correction device according to claim 1, characterized in that the error correction device is constructed as follows. 3 The syndrome generator generates a syndrome by using an extended test matrix suitable for 1-burst block error correction/2-burst block error detection, or a matrix in which a part of the extended test matrix is omitted. Error correction device according to claim 1, characterized in that it is arranged to generate information.