JPS63157934U - - Google Patents
Info
- Publication number
 - JPS63157934U JPS63157934U JP5007187U JP5007187U JPS63157934U JP S63157934 U JPS63157934 U JP S63157934U JP 5007187 U JP5007187 U JP 5007187U JP 5007187 U JP5007187 U JP 5007187U JP S63157934 U JPS63157934 U JP S63157934U
 - Authority
 - JP
 - Japan
 - Prior art keywords
 - pad
 - bond pad
 - board
 - bare chip
 - semiconductor bare
 - Prior art date
 - Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
 - Pending
 
Links
- 239000000919 ceramic Substances 0.000 claims description 6
 - 239000004065 semiconductor Substances 0.000 claims description 4
 - 239000011248 coating agent Substances 0.000 claims description 2
 - 238000000576 coating method Methods 0.000 claims description 2
 - 239000011347 resin Substances 0.000 claims description 2
 - 229920005989 resin Polymers 0.000 claims description 2
 - 239000000758 substrate Substances 0.000 description 2
 - 239000000463 material Substances 0.000 description 1
 
Classifications
- 
        
- H—ELECTRICITY
 - H01—ELECTRIC ELEMENTS
 - H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
 - H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
 - H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
 - H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
 - H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
 - H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
 - H01L2224/321—Disposition
 - H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
 - H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
 - H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
 
 - 
        
- H—ELECTRICITY
 - H01—ELECTRIC ELEMENTS
 - H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
 - H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
 - H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
 - H01L2224/42—Wire connectors; Manufacturing methods related thereto
 - H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
 - H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
 - H01L2224/4805—Shape
 - H01L2224/4809—Loop shape
 - H01L2224/48091—Arched
 
 - 
        
- H—ELECTRICITY
 - H01—ELECTRIC ELEMENTS
 - H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
 - H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
 - H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
 - H01L2224/42—Wire connectors; Manufacturing methods related thereto
 - H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
 - H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
 - H01L2224/481—Disposition
 - H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
 - H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
 - H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
 
 - 
        
- H—ELECTRICITY
 - H01—ELECTRIC ELEMENTS
 - H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
 - H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
 - H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
 - H01L2224/42—Wire connectors; Manufacturing methods related thereto
 - H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
 - H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
 - H01L2224/481—Disposition
 - H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
 - H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
 - H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
 - H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
 
 - 
        
- H—ELECTRICITY
 - H01—ELECTRIC ELEMENTS
 - H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
 - H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
 - H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
 - H01L2224/732—Location after the connecting process
 - H01L2224/73251—Location after the connecting process on different surfaces
 - H01L2224/73265—Layer and wire connectors
 
 - 
        
- H—ELECTRICITY
 - H01—ELECTRIC ELEMENTS
 - H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
 - H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
 - H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
 - H01L2924/191—Disposition
 - H01L2924/19101—Disposition of discrete passive components
 - H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
 
 
Landscapes
- Wire Bonding (AREA)
 - Die Bonding (AREA)
 
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title | 
|---|---|---|---|
| JP5007187U JPS63157934U (en:Method) | 1987-04-02 | 1987-04-02 | 
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title | 
|---|---|---|---|
| JP5007187U JPS63157934U (en:Method) | 1987-04-02 | 1987-04-02 | 
Publications (1)
| Publication Number | Publication Date | 
|---|---|
| JPS63157934U true JPS63157934U (en:Method) | 1988-10-17 | 
Family
ID=30873089
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date | 
|---|---|---|---|
| JP5007187U Pending JPS63157934U (en:Method) | 1987-04-02 | 1987-04-02 | 
Country Status (1)
| Country | Link | 
|---|---|
| JP (1) | JPS63157934U (en:Method) | 
- 
        1987
        
- 1987-04-02 JP JP5007187U patent/JPS63157934U/ja active Pending