JPS63157350A - Tracking controller - Google Patents

Abstract

PURPOSE:To control good tracking by varying a detecting reference value in order to make a regenerative detection probability of synchronizing signal fall in within the most suitable range. CONSTITUTION:Reproducing signals from two head are binarized by a comparator for digital conversion and then sampling processed by a clock pulse from a terminal 17 at a synchronizing pattern detecting circuit 19 which in turn outputs a pattern detecting signal Pc'. A counter 20 counts the detecting pulse Pc' for every period of a certain time and outputs a discrete value signal A. A comparator 22 compares the signal A with a detecting reference value B' from a reference value generating circuit 27, and when the discrete value of the signal A is >=B', a detecting signal C of the synchronizing signal is sent to a control circuit 23, and from the circuit 23 sampling pules SPa and SPb are outputted. A counter 25 is reset by a reset pulse from a counter 24 and outputs a discrete value signal D of the signal SPb. A control circuit 26 takes a load pulse from the counter 24 together with the signal D and sends a variable control signal to the circuit 27 which in turn outputs the reference value signal B' by which a generative detection probability is fallen into the most suitable range.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention provides tracking control by controlling the running phase of a tape using a pilot signal and a synchronization signal for tracking control of each track of a magnetic tape included in a reproduction signal. The present invention relates to a tracking control device for a magnetic recording/reproducing device such as a rotary head type digital audio tape recorder.

[Conventional technology]

Conventionally, a rotary head type digital audio tape recorder (hereinafter referred to as R-DAT) has a rotary cylinder with 18
A pair of rotating heads installed 0 apart,
A magnetic tape running with 90 windings wrapped around the rotating cylinder is alternately helically scanned.

For example, as stated in the specification and drawings of Japanese Patent Application No. 108753/1983, at the time of recording,
PCM such as audio information is recorded on each track of the tape formed by one scan of both rotary heads.
A digital recording information signal consisting of a signal, a pilot signal for tracking control, and a synchronization signal are time-divisionally recorded in a predetermined format, that is, a four-track complete tracking format.

By the way, in the aforementioned 4-trunk complete tracking control format, a tracking area of a certain length is provided at the beginning and end of the trace of each track on the tape, in which a pilot signal, a synchronization signal, and an erase signal for tracking control are recorded. Additionally, the area between both tracking areas is set as an area for recording the PCM signal.

In addition, the synchronization signal for tracking control is 1i for each track.
: 522-67KH2,784,0OKHzii: Changes alternately, tracking pilot signal and cancellation signal are L 30-67KHz and 1.568MHz
The synchronization signal and pilot signal are fixed to each PC.
The frequency is set to be sufficiently lower than the frequency band of the M signal.

As for the recording pattern of the tracking area, the same pattern appears every four tracks, and the sampling of the pilot signal of each of the two adjacent tracks of the trace track included in the playback signal is performed based on the detection of playback of the synchronization signal. The recording lengths and recording positions of the synchronization signal, pilot signal, and erasure signal are set to be different to enable this.

In other words, the recording pattern of the R-DAT tape is as shown in Figure 3)), (sometimes shown in Figure 3), (a) and (b).
)), (1) is a magnetic tape, (2a), (2
b) The tape (1
) Tracks with different azimuths formed alternately in (8a)
, (8b) are the tracking areas at the beginning and end of each track (2a), (2b), which are set to the length of 5 broncs of the PCM signal. (4) is for each track (2a), (
Area (3a) of 2b).

(3b) This is an area provided in between for recording PCM signals.

Also, (51) and (S2) are 522.67KH2,78
Recording position of each 4.0 OKHz synchronization signal, (P)
, (E) indicate the recording positions of the pilot signal and the erase signal, respectively.

Note that if the length of one block of the PCM signal is τ, then the third
As is clear from figure (b), the recording length of the synchronization signal is 1
τ or 0.5τ, and the recording length of the pilot signal is always lτ.

Furthermore, the recording position (SL) or (S2) of the synchronization signal of each track (2a), (2b) is adjacent to the recording position (P) of the pilot signal of the adjacent track on the trace preceding side, and the synchronization signal The recording position CP) of the pilot signal of the adjacent track on the trailing side of the trace is adjacent to the position traced with a delay of 2 from the start of the recording position.

During reproduction, the tracking control device having the configuration shown in FIG. 4 performs tracking control so that both rotary heads are on-track, and the tape is reproduced.

Next, the tracking control device shown in FIG. 4 will be explained.

In Fig. 4, (5) is the input terminal for the reproduction signal of both rotary heads, and every 180 rotations of the rotary cylinder, 9
The reproduction signal is input only during the 0- period. (6) l is an input terminal for a head switching signal.

(7) is a playback amplifier connected to the input terminal (5), (8
) is a low-pass filter for pilot signal extraction connected to the amplifier (7), and (9) is an envelope detection circuit connected to the filter (8).

0Q is the first sample and hold circuit connected to the detection circuit (9), αυ is a subtracter that subtracts the output signals of the detection circuit (9) and sample and hold circuit 01, and (2) is connected to the subtracter αυ. The second sample and hold circuit 03 is a sample and hold section consisting of a sample and hold circuit GO (2) and a subtracter 0υ.

α→ is an equalizer circuit for waveform equalization connected to the amplifier (7), α9 is a comparator for digital conversion that binarizes the output signal of equalizer circuit α→, and α0 is a detection process connected to comparator α itself. The circuit is composed of a microcomputer, etc., and is based on the head switching signal at the input terminal (6) and the detection clock pulse at the input terminal αη.
The reproduction of the synchronizing signal is digitally detected from the output signal of , and the sampling pulses SPa and SPb of the pilot signals of the two adjacent tracks are outputted to the sample and hold circuits Q0 and (2), respectively. (7) is equalizer circuit Q41,
This is a synchronization detection section consisting of a comparator α and a processing circuit aQ.

By the way, the detection processing circuit α0 is configured as shown in Figure @5, in which 01 is a synchronization pattern detection circuit connected to the comparator α9, and the clock pulse of the input terminal (I7) causes the comparator a9 to The output signal is sampled and the inversion period of the output signal of the comparator αG is detected.
, 784.00KHz) R1 outputs a pattern detection pulse Pi of the synchronization pattern every second.

The handle is a synchronous signal detection counter whose clock terminal (ck) is connected to the detection circuit Q1, which counts the detection pulses Pi every fixed period (α5τ) set by the reset control of the control circuit described later, and calculates the count value. Outputs signal A.

Ql) is a reference value generation circuit consisting of a ROM, etc., and is a detection standard whose contents are switched according to the head to be scanned, that is, according to the frequency of the synchronization signal to be reproduced, based on the head switching signal at the input terminal (6). Outputs value signal B.

(A) is a synchronous signal detection comparator connected to the detection circuit 2 generating circuit 12υ, which outputs a synchronous signal detection signal C when the count value of signal A is greater than or equal to the detection reference value of signal B. .

(c) shows the detection pulse Pi, the detection signal C and the input terminal (
6) is a detection processing control circuit to which the α force head switching signal and clock signal are input, and supplies a reset signal to the reset terminal (rst) of the counter (A), and forms sampling pulses SPa and SPb. Output.

In addition, the clock signal of input terminal αη is 9.408MHz
is set to .

The playback signals alternately output from both heads are input to the amplifier (7) via the input terminal (5), and the amplifier (
The reproduced signal amplified by step 7) is input to the filter (8) and the equalizer circuit α, respectively.Since the frequency of the pilot signal included in the reproduced signal is the lowest, the filter (8) extracts the pilot signal component from the reproduced signal. is extracted.

Further, the output No. 1 of the filter (8) is input to the detection circuit (9), and the extracted pyro and throat signal components are converted into DC by the detection circuit (9).

Then, from the detection circuit (9) to the sample hold circuit (1
A detection signal of the level of the pilot signal included in the reproduced signal is output to the subtracter 01).

On the other hand, the reproduced signal whose waveform has been equalized by the equalizer circuit αa is input to the comparator 09, and the re-signal is binarized and digitized by the comparator α9.

Then, the digital signal output from the comparator α9 and the head switching signal at the input terminal (6) are processed by the processing circuit a! is input to the detection circuit 01, and the detection circuit 0 flaw is based on the clock pulse of the input terminal α force! , 9.408MH2 (7)
At the same time as sampling digital No. 1 of comparator Q9 at the sampling frequency, the level of the digital signal at each sampling time is held in a built-in shift register, etc., and the inversion period is detected, and the inversion period is equal to the period of the frequency of the synchronization signal. Each time, a detection pulse Pi is output to the counter (1) and the control circuit.

By the way, the length lτ of one block of the PCM signal is 38
．． It is set to 2 μsec.

Also, when the synchronization signal is reproduced, the period of the detection pulse Pi is 0.96μ depending on the frequency of the synchronization signal to be reproduced.
SeC(=1/(522,67KHzX2) l,
0-64 μ5ec (=1/(784KHzx2) )
The output period of the detection pulse Pi is 0.5τ, lτ depending on the recording length of the synchronization signal to be reproduced.
It will be one of the following.

Then, when the detection pulse Pi starts to be input, the control circuit (to) determines the frequency of the synchronization signal from its period, and determines the time required for three detection pulses Pi to be input in succession.
That is, only when two or more detection pulses Pi are input during a maximum time of 3μ5ec (medium 0.96μ5ecX3), a sampling pulse SPa is formed and output at the input timing of the second detection pulse Pi, and the sampling pulse SPa is output at the input timing of the second detection pulse Pi. 5
The internal formation of the first winto gate 1-Wa for recording length detection is started, and the reset terminal (rs
Stop outputting the reset signal to the counter (a).
Cancel the reset.

Therefore, the counter counter counts the number of detection pulses Pi during 0.5 from the output timing of the sampling pulse SPa.

Furthermore, the frequency of the synchronization signal to be reproduced is 522.67KH.
z, 784KHz, if there are no omissions, the number of detection pulses Pi output during 0.5τ (L9.1μ5ec) is 20 (out of 19, 110, 96), (19,, 110, (out of 64) will be 30 pieces each.

Furthermore, the signal A of the counter is input to the comparator (E), and the count value of the signal A is set corresponding to the detection reference value of the signal B of the generation circuit (C), that is, the 20 and 30 points described above. When the detected reference value is exceeded, a detection signal C is output from the comparator (a) to the control circuit.

Then, the control circuit detects whether or not the detection signal C of the comparator (a) is input at the timing of the terminal end of the first window gate Wa. is instantaneously reset, internal formation of the second wind gate wb for detecting the record length of the sail 5τ is started, and the counter is again counted for the detection pulse Pi during 0.5τ.

Note that at the end of the first wind gate Wa, the detector (
If the detection signal C of (b) is not input, the control circuit (c)
resets the internal state to the initial state and supplies a reset signal to the counter (1) until the sampling pulse SPa is generated.

By the way, when the detection signal C is input at the time of the termination of the first window gate Wa, the control circuit detects whether or not the detection signal C is input at the timing of the termination of the second window gate Wb. When the recorded length of the reproduced synchronization signal is identified and the reproduced synchronization signal is specified, and the identified synchronization signal matches the synchronization signal expected from the 4-track complete format shown in FIG. 8(b). Only then, it determines that the reproduced signal is a synchronization signal, forms and outputs the sampling pulse Pb 1τ after the end of the second window gate Wb, resets the inside to the initial state, and starts the next sampling pulse SPa. A reset signal is supplied to the counter until formation.

That is, the equalizer circuit 0ψ, the comparator α9, and the detection circuit Q9 form a synchronization pattern detection means, and for example, the 1r near 84KHz of ta-ztb in FIG. 6(a)
When the synchronization signal of =0.64μ5ec), the detection circuit 00 continuously outputs the detection pulse Pi.

Further, the counter 9 generation circuit Q1), the comparator (A) and the control circuit @ form a synchronizing signal detection processing means, and when the detected pulse Pi starts to be input to the control circuit @, as shown in FIG.
As shown in C) and (d), the control circuit @forms and outputs the sampling pulse SPa to the input %ta' of the second detection Hals Pi, and also outputs the sampling pulse SPa to the input %ta' of the second detection Hals Pi.
) Start internal formation of Wa.

When the detection signal C is input at the terminal ta of the @l wind gate Wa, the control circuit (c) sets the detection flag in the internal flag register and the second Internal formation of the window gate Wb is started.

Furthermore, when the detection signal C is input at the terminal end tb of the second window gate Wb, the control circuit □□□ again sets the detection flag in the internal flag register as shown in FIG. 6(e). Presence of detection flag set.

The reproduced synchronization signal is specified based on the absence of information, and it is determined whether the reproduced signal is a synchronization signal or not.

Then, only when the playback signal is a synchronization signal, the control circuit @
As shown in FIG. 6(f), the second wind gate Wb
1τ after the end of the sampling pulse SPa
A sampling pulse SPb is formed and output at tc 2τ after the output of .

Therefore, the sampling pulse SPa is a maximum of 3μ5ec (ki 0.96μsec
3) is output at a timing delayed by a minute time,
Sampling pulse SPb is output with a delay of 2τ from sampling pulse SPa only when reproduction of the synchronization signal is detected.

Then, the sampling pulse SPa is supplied to the sample and hold circuit 0Q, and the sample and hold circuit α0 is connected to the detection circuit (9) every time the sampling pulse SPa is input.
) is sampled and held.

In addition, since the output signals of the detection circuit (9) and the sample and hold circuit αQ are input to the subtracter αυ, the detection signal of the detection circuit (9) and the sample and hold circuit α0 are sent from the subtracter αη to the sample and hold circuit. A signal with a level difference from the output signal of is output.

Furthermore, since the sampling pulse SPb is supplied to the sample and hold circuit (2), the sample and hold circuit @
is the detection signal of the detection circuit (9) when the sampling pulse SPb is input only when the reproduction of the synchronization signal is detected, that is, the pilot signal of the adjacent track on the trailing side included in the reproduction signal, Sampling pulse SPa
The detection signal of the detection circuit (9) held in the sample and hold circuit αQ, that is, the tracking error signal having a level difference from the pilot signal of the preceding adjacent track included in the reproduced signal, is sampled and held.

That is, the sample hold section α] forming the sample hold means samples the biloft signals of two adjacent tracks included in the playback signal based on the sampling pulses SPa and spb and with reference to the detection of playback of the synchronization signal, A tracking error signal of the level difference between both pilot signals, that is, the pilot level difference, is generated and held.

Note that both sample-and-hold circuits αcp and (12) each consist of a well-known sample-and-hold circuit using an operational amplifier, a sample-and-hold switch, a capacitor, etc., and when the pilot level difference is 0, the level of the error signal changes within the range. The on-track level is the midpoint of .

Then, a phase control signal proportional to error No. 1 of the sample and hold circuit (6) is supplied to the capstan motor drive circuit, and based on the phase control signal, the error signal is adjusted to the on-track level. The rotational phase of the capstan motor is controlled to control the running phase of the tape so that the pilot level difference becomes 0, and the so-called ATF tracking control is used to perform tracking control so that both rotating heads are pulled into a proper on-track state. be done.

That is, when both rotary heads are tracked to a proper on-track state, the pilot level difference becomes O and the error signal becomes on-track level, and when both rotary heads go off-track due to tracking deviation, the off-track direction and The pilot level difference changes from 0 depending on the amount, and the error signal changes from the on-track level.

Therefore, during playback, the tracking control device loop-controls the rotational phase of the capstan motor so that the error signal becomes on-track level, that is, so that the biloft level difference becomes 0, and both rotating heads are properly on-track. drawn into the state.

By the way, when the operation is unstable, such as immediately after switching to playback by switching the operation mode, and when the C/N of the playback signal is
(carrier power/noise) deteriorates, the detection circuit Ql cannot perform the detection reliably due to disturbances in the waveform of the reproduced signal, causing a delay in the start of output of the detection pulse Pi, etc. 1. 2nd wind gate Wa,
Detection pulse Pi between 0 and 5τ set by Wb
is reduced from 20 or 30 in the ideal case.

Therefore, the smaller the detection reference value of the generation circuit (company) is, the easier it becomes to output the detection signal C from the comparator (a) even if the number of detection pulses Pi is small, and the probability of detecting reproduction of the synchronization signal increases. .

However, the smaller the detection reference value is, the higher the probability of false detection of synchronization signal reproduction becomes.
, Wb is delayed, and the detection delay in reproduction of the synchronization signal (hereinafter referred to as synchronization detection delay) becomes large.

For example, when detecting the reproduction of a synchronization signal with a frequency of 748 KHz, if the detection reference value is set to 20% of the maximum number of detections of 30, that is, 6, the synchronization signal will not be parked even if the detection start of the detection pulse Pi is delayed by about 16 μsec. It becomes possible to detect the sampling pulse SPb and output the sampling pulse SPb, which may cause a synchronization detection delay of about 16 μsec at maximum.

Note that the detection standard value is set to 50% of the maximum number of detections, that is, 15
When set to 1, the maximum synchronization detection delay is shortened to about 10 μsec.

Then, 10μ is used for sampling the pilot signal based on each of the sampling pulses SPa and SPb.
sec and the tape recording pattern jitter (fluctuation) is IOμsec, as is clear from Figure 3(b), the limit value of the synchronization detection delay described above is (88, l). -10-11) It becomes about 18μsec, and at this time, if the detection reference value is set to 6 pieces of 20%, the margin time for sampling is (18-L6= )
Only about 2 μsec remains.

That is, if the detection reference value of the generation circuit Q) is increased, the reproduction detection probability decreases, and conversely, if it is decreased, the synchronization detection delay increases.

Therefore, the detection reference value of the generation circuit CI) is determined based on experiments and the like to be an appropriate value that allows average tracking control in each playback state, that is, a maximum detection number of 20 to 50.
It is set to an appropriate value of %.

[Problem that the invention seeks to solve]

Incidentally, the disturbance in the waveform of the reproduced signal changes depending on the reproduction state f.

Furthermore, in order to accurately sample and detect the pilot signal, accurately form an error signal, and perform good tracking control, it is desirable to increase the reproduction detection probability as much as possible and minimize the synchronization detection delay.

However, in the case of conventional tracking devices, as mentioned above, the detection reference value of the originating circuit (2η) is fixed.
There is a problem that an error signal cannot be accurately formed by optimal sampling according to the reproduction state, and good tracking control cannot be performed.

[Means for solving problems]

This invention was made with the above points in mind,
A running magnetic tape is helically scanned by a rotating head, and during recording, tracks in which digital recording information signals, tracking pilot signals, and synchronization signals are recorded in a predetermined format are sequentially formed on the tape, and during playback, tracks are sequentially formed on the tape. By digitally detecting the reproduction of the synchronization signal by the head and sampling the reproduction signal of the head based on the detection, the level difference between the pilot signals of two tracks adjacent to the trace track included in the reproduction signal is determined. provided in a magnetic recording and reproducing apparatus that generates and holds a tracking error signal, and performs tracking control of the head by controlling the rotational phase of a capstan motor for controlling the running of the tape based on the error signal, synchronization pattern detection means that continuously outputs a pattern detection pulse while a digital waveform pattern formed by binarizing a signal becomes a digital waveform pattern of the synchronization signal; and a count value of the pattern detection pulse and the synchronization signal. detecting reproduction of the synchronization signal by determining whether or not the reproduction signal is the synchronization signal based on a comparison with a detection reference value;
In a tracking control device comprising a synchronization signal detection processing means for forming a sampling pulse, and a sample hold means for generating and holding the error signal based on the sampling pulse, Detection number counting means for repeatedly counting the number of detected synchronization signals, and the counted value of the number of detections is a value within an optimal range set based on the detection probability of the synchronization signal and the detection delay of the synchronization signal. detection reference value varying means for varying the detection reference value so as to pull the counted value of the number of detections to a value within the optimum range based on the determination by the detection number discrimination means; A tracking control device comprising:

[Effect]

Therefore, the detection probability of synchronization signal reproduction is detected by counting the number of synchronization signal detections, and the detection reference value is varied so that the detection probability is within the optimal range. For example, the detection probability is within the optimal range. If the detection probability is smaller than the value within the optimal range, the detection reference value becomes larger and control is performed to shorten the detection delay of the synchronous G signal, that is, the synchronous detection delay.If the detection probability is smaller than the value within the optimal range, the detection reference value becomes smaller. It is controlled so that the detection probability is increased.

Therefore, the detection reference value is varied to the optimum value for each playback state that increases the detection probability and minimizes the synchronization detection delay.The pilot signal is accurately sampled by the best sampling according to the playback state, and the error signal is detected. is formed accurately and good tracking control is performed.

〔Example〕

Next, a second case showing one embodiment of the present invention will be shown. In the same figure, the same symbols indicate the same or equivalent things, and (c) counts the head switching signal of the input terminal (6). This is a period setting counter for the rotating cylinder.
Outputs reset pulse and load pulse every rotation. (to) is a detection number counter that counts sampling pulses SPb, and is reset by the reset pulse of counter (c), and outputs a signal of the counted value of sampling pulses SPb every fixed period Tn during which the rotating cylinder rotates N. do.

(to) is a detection reference value control circuit consisting of a microcomputer, etc., which takes in the signal of the counter (c) by inputting the load pulse of the counter (c), and
The number of detected reproductions of the synchronization signal every n is determined, and based on the determination, a variable control signal for the detection reference value is output.

The gradient is a reference value generation circuit provided in place of the generation circuit CI in Figure 5. It consists of a ROM, etc., and outputs the detection reference value signal B designated by the variable control signal of the control circuit (c). Output to frame # comparator (a).

Note that the counters (c) and (a) form a detection number counting means, and the control circuit (a) and nine firing circuit (a) form a detection number determination means and a detection reference value variable means.

To simplify the explanation, for example, if the number of rotations N of the cylinder is 10, and the maximum number of detected synchronization signals during the period Tn during which the cylinder rotates 10 times is 40, the maximum number of sampling pulses SPb is Suppose that there are 40 pieces.

In addition, in order to minimize the synchronization detection delay by making the target value of the synchronization signal detection probability larger than 90%, the target minimum value of the synchronization signal detection probability and the target maximum value of the synchronization detection delay are determined through experiments. Based on the target minimum value of detection probability and the target maximum value of synchronization detection delay, the period T
Assume that the range in which the number of detected reproductions of n synchronization signals is 37 to 39 is set as the optimal range.

At this time, the control circuit has a predetermined number of detections of 8 within the optimum range.
7 to 39 are set.

Then, every period Tn during which the cylinder rotates 10 times, a time-series load pulse and a reset pulse are outputted from the counter (c) to the control circuit (a) and the counter (c), respectively.

In addition, the counter (to) inverts the count of the sampling pulse SPb until the reset pulse is input, and counts the number of detected reproductions of the synchronization signal for each period Tn.
Outputs the count value signal.

Then, since the load pulse is input to the control circuit immediately before the reset pulse, the control circuit (E) receives the signal from the counter (C) every period Tn.
The count value of the detected number of synchronization signal reproductions is subjected to variable control processing, which will be described below.

First, it is determined whether the captured count value is greater than 36 or not, and if it is 36 or less, that is, smaller than the optimal range value, the detection probability is increased unless the detection reference value of the generation circuit is not the lower limit value. Therefore, a variable control signal that lowers the detection reference value by one step is output to the generator circuit gradient.

On the other hand, if the captured count value is 37 or more, it is determined whether the count value is 39 or less, and if the count value is 40. In other words, if the value is larger than the optimal range, unless the detection reference value of the generation circuit (5) is not the upper limit, the generation circuit (A) sends a variable control signal to lower the detection reference value by one step in order to reduce the detection delay.
Output to.

Incidentally, the generation circuit (A) stores in advance a plurality of detection reference values within a variable range, which are set based on the upper and lower limits of the detection probability, for each frequency of the synchronization signal.

Then, each stored detection reference value is selectively specified by the variable control signal output from () to the control circuit, and the detection reference value is varied within the range of the upper and lower limit values. Outputs value signal B.

Therefore, the detection reference value of the generation circuit (company) is such that the count value taken into the control circuit (1) is within the optimal range of 37 to 3.
It is variable so that it is pulled in to 9.

Since the count value taken into the control circuit (1) changes depending on the output number of sampling pulses SPb, that is, the detection probability, the detection reference value of the generation circuit gradient is set to a target detection probability according to the reproduction state. It is variable to minimize the detection delay by pulling it down to the minimum value, making it possible to reliably sample the pilot signal and form the error signal accurately, and to achieve the best tracking control according to the playback condition. I can do it.

In the case of the embodiment, since the target minimum value of the detection probability is set to 90% or more, the playback of the synchronization signal is detected very accurately.
It also has the advantage of being able to correctly set standards for after-recording in which only the M signal is rewritten.

By the way, the fixed period Tn, the value of the optimum range, etc. can be set arbitrarily.

Further, the groove bottom of each means may be different from that in the embodiment, and in this case, the sampling pulse SP is used to detect the reproduction of the synchronization signal.
Signals other than b may also be used.

Although the embodiment described above is applied to a tracking control device for an R-DAT, it is of course applicable to tracking control devices for various magnetic recording and reproducing devices other than the R-DAT.

〔Effect of the invention〕

As described above, according to the tracking control device of the present invention, the detection reference value is varied so that the number of detected synchronization signal reproductions for each fixed period is pulled into a value within the optimal range. However, it is possible to accurately sample the synchronization signal to form an error signal and perform good tracking control.

[Brief explanation of the drawing]

1 and 2 show one embodiment of the tracking control device of the present invention, FIG. 1 is a partial block diagram, FIG. 2 is a flowchart for explaining the operation, and FIG. 3(a), Φ) is an explanatory diagram of a recording formant of a rotary head type digital audio tape recorder, FIG. 4 is a block diagram of a conventional tracking device for a rotary head type digital audio tape recorder, and FIG. 5 is a detail of a part of FIG. 4. The block diagram and FIGS. 6(a) to 6(f) are timing charts for explaining the operation of FIG. 5. (1)...magnetic tape, alpha...sample hold section, alpha (a)...equalizer circuit, alpha9...comparator for digital conversion, alpha...synchronization detection section, 09... Synchronization pattern detection circuit, (1)...Synchronization signal detection counter, (A)...Comparator for synchronization signal detection, @P...Detection processing control circuit, ■...Period setting counter, (A)...・・・
Detection number counter, (E)...Detection reference value control circuit, (C)...Reference value generation circuit.

Claims (1)

[Claims] (1) A rotating magnetic tape is helically scanned by a rotating head, and during recording, tracks in which digital recording information signals, tracking pilot signals, and synchronization signals are recorded in a predetermined format are sequentially formed on the tape, and then played back. At times, by digitally detecting the reproduction of the synchronization signal by the head and sampling the reproduction signal of the head based on the detection, the pilot signals of two tracks adjacent to the trace track included in the reproduction signal are detected. A magnetic recording/reproducing apparatus is provided in a magnetic recording/reproducing apparatus that generates and holds a tracking error signal having a level difference, and controls the tracking of the head by controlling the rotational phase of a capstan motor for controlling the running of the tape based on the error signal. , synchronization pattern detection means that continuously outputs pattern detection pulses while a digital waveform pattern formed by binarizing the reproduced signal becomes a digital waveform pattern of the synchronization signal; and a count value of the pattern detection pulses. detecting reproduction of the synchronization signal by determining whether or not the reproduction signal is the synchronization signal based on a comparison with a detection reference value of the synchronization signal;
A tracking control device comprising: synchronization signal detection processing means for forming a sampling pulse; and sample hold means for generating and holding the error signal based on the sampling pulse; Detection number counting means for repeatedly counting the number of detected synchronization signals, and the counted value of the number of detections is a value within an optimal range set based on the detection probability of the synchronization signal and the detection delay of the synchronization signal. detection reference value varying means for varying the detection reference value so as to pull the counted value of the number of detections to a value within the optimum range based on the determination by the detection number discrimination means; A tracking control device comprising: