JPS63155985A - Signal processing circuit - Google Patents

Abstract

PURPOSE:To contrive the improvement of the pulling-in performance of a 2nd input signal with respect to the 1st input signal of a phase comparator by using a detection circuit to detect the presence or absence of a phase lock of the 2nd input signal to the 1st input signal to output a control signal and using the control signal so as to change over a time constant of a low pass filter. CONSTITUTION:The presence of the phase lock of the 2nd input signal is detected by a detection circuit 6 with respect to the 1st input signal of a phase comparator 2 so as to change over the time constant of a low pass filter 3, thereby improving the pulling-in performance of the 2nd input signal with respect to the 1st input signal of the phase comparator 2. That is, when the detection circuit 6 detects it that the phase of the 2nd input signal is not locked to the 1st input signal of the phase comparator 2, the time constant of the low pass filter 3 is set to a small value. Since the lock range and capture range of the low pass filter whose time constant is small is wide, the pulling-in performance of the 2nd input signal with respect to the 1st input signal of the phase compara tor 2 is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a signal processing circuit used in a PLL circuit of a video tape recorder (hereinafter abbreviated as VTR) or the like.

BACKGROUND OF THE INVENTION In a PLL circuit used in conventional VTRs, etc., the time constant of the low-pass filter is set very slowly in order to obtain a signal that should be the reference for the first input signal of the phase comparator at the second input. was.

Problems to be Solved by the Invention However, when using a PLL circuit having the above configuration,
Since the time constant of the low-pass filter is very slow, the lock range and capture range are narrow, and the phase comparator has the disadvantage that the second input signal is not well drawn into the first input signal.

Means for Solving the Problems The signal processing device of the present invention uses a detection circuit to detect whether the phase of a second input signal is locked to the first input signal of a phase comparator, and The phase comparator is configured to improve the performance of drawing in the second input signal with respect to the first input signal by switching the time constant of the phase comparator. In other words, when the detection circuit detects that the phase of the second input signal is not locked with respect to the first input signal of the phase comparator, the time constant of the low-pass filter becomes faster (the set zero time constant Since a fast low-pass filter has a wide lock range and capture range, the phase comparator's ability to pull in the phase of the second input signal with respect to the first input signal is improved.
Phase can be locked quickly. Further, when the detection circuit detects that the phase of the second input signal is locked with respect to the first input signal of the phase comparator,
The time constant of the low-pass filter is set slowly. In a low-pass filter with a slow time constant, the signal that should serve as a reference for the first input signal can be obtained as the second input signal, as in the past.

When a signal to be used as a reference for the first input signal of the working phase comparator is obtained as a second input signal, the present invention uses the above-described configuration to adjust the second input signal to the first input signal of the phase comparator. Improved pulling performance.

EXAMPLE An example of the present invention will be described below with reference to the drawings.

FIG. 1 shows a block diagram of the invention.

A signal obtained based on the horizontal synchronization signal of the video signal inputted from the terminal 1 is input to the first input of the phase comparator 2.

The output of the phase comparator 2 is input to a low pass filter 3. In the low-pass filter 3, the time constant can be switched based on the control signal obtained by the detection circuit 6.

The output signal of the low-pass filter 3 is input to a voltage controlled oscillator 4. The output of the voltage controlled oscillator 4 is output through a terminal 7 and simultaneously input to a 1/n frequency divider 5 (n is any natural number). The output of the 1/n frequency divider 5 (rl is an arbitrary natural number) is input as the second input of the phase comparator 2.

Further, the first input signal and the second input signal of the phase comparator 2 are also input to the detection circuit 6 . The detection circuit 6 detects whether the phase of the second input signal is locked to the first input signal of the phase comparator 2 and outputs a control a signal to the low-pass filter 3.

Here, in the PLL circuit shown in this embodiment,
With the above configuration, it is possible to detect whether the phase of the second input signal is locked to the first input signal of the phase comparator and to switch the time constant of the low-pass filter. Therefore, in the Yuki example, the performance of drawing in the second input signal to the first input signal of the phase comparator is improved compared to the conventional example.

FIG. 2 shows an example of an integrated circuit of the detection circuit 6, and FIG. 2 shows waveform diagrams of each part a to d in FIG. 2. (Figure 3 (
1) to (8)) In one specific example of the detection circuit 6 shown here, it is detected whether the phase of the 20th input signal is locked to the first input signal of the phase comparator 2, If it is in a locked state, the output is kept low, and if it is not in a locked state, the output is kept high.

Here, it is composed of an AND gate 8 and a monomulti 9. The first input signal (input to part a) and the second input signal (input to part b) of the phase comparator 2 are input to the input of the AND gate 8.

The output signal of the AND gate 8 is input to the monomulti 9. The output signal of the monomulti 9 is output to the low-pass filter 3 as a control signal.

In a state where the phase of the second input signal is not locked to the first input signal of the phase comparator 2, the second input signal is adjusted based on the first input signal ((1) in FIG. 3). When looking at the signal, the waveform flows ((2) in Figure 3). Therefore, when the first input signal and the second input signal are input to the AND gate 8, when the pulse generation timing of the first input signal and the second input signal fails, the AND gate 8
A pulse is generated at the output ((3) in Figure 3). When such a pulse is input to the monomulti 9 in retrigger mode with a time constant determined by T = C, ・R1, if the period of T is long enough, the monomulti 9 will input it multiple times within the period of T. A trigger is applied, and the output is kept at H4gh (+41 in FIG. 3).

In addition, when the phase of the second input signal is locked to the first input signal of the phase comparator 2, the second When looking at the input signal, there is no waveform flowing. ((6 in Figure 3)
)). Therefore, the first input signal and the second input signal are A
Even if it is input to the ND gate 8, no pulse is generated at the output (171 in Figure 3), therefore, the monomulti 9
In this case, no trigger is applied, and the output is kept low ((8) in FIG. 3).

FIG. 4 shows an example of a low-pass filter 3.

Here, it is composed of a switch SW1, a resistor R2R3, and a capacitor C2.

In the example of the low-pass filter 3 shown here,
The time constant can be switched by a control signal output from the detection circuit 6.

First, the switch SW1 is turned on and off using the Low and High control signals obtained by the detection circuit 6.

When switch SW1 is on, switch SW1 is on.
The time constant of the low-pass filter is determined by the resistor Rsv+, the resistor R2R3, and the capacitor C2, but when it is off, the time constant of the low-pass filter is determined only by the resistor R2R3 and the capacitor C2. 0Normally, Rsv+''
= -0, and Rsw and R2 are °, so when it is on, the time constant of the low-pass filter becomes faster, and when it is off, the time constant of the low-pass filter becomes slower.

In this embodiment, a case is described in which a signal obtained based on the horizontal synchronization signal of the video signal is input from terminal 1, but the signal obtained based on the burst present or added to the video signal is input. The present invention can also be applied to other signals such as signals obtained by Furthermore, in the detection circuit in this embodiment, a signal was output when the phase of the second input signal was not locked with respect to the first input signal of the phase comparator 2; The present invention can also be applied when outputting a signal when the phase of the second input signal is locked to the input signal. Further, although the detection circuit in this embodiment is configured with an AND gate or a monomulti, the present invention can be applied to other elements as well. Further, in this embodiment, an RC lag lead filter is used as the low-pass filter, but the present invention can be applied to other RC lag filters, active filters, and the like.

Furthermore, in this embodiment, the time constant of the low-pass filter is switched based on the control signal obtained by the detection circuit, but it is also possible to select one of a plurality of low-pass filters with different time constants based on the control signal. The present invention can also be applied.

Effects of the Invention As is clear from the above explanation, the present invention inputs the output of the phase comparator to the voltage controlled oscillator after passing through a low-pass filter, and simultaneously outputs the output of the voltage controlled oscillator by 1/n. Input the frequency generator (n is any natural number) and
A PL that generates a signal phase-locked with a first input signal input to a first input of the phase comparator by inputting the output of the /n frequency divider to a second input of the phase comparator.
L circuit, the detection circuit detects whether or not the phase of the second input signal is locked with respect to the first input signal and outputs a control signal, and the time constant of the low-pass filter is switched by the control signal. This is a signal processing circuit characterized by improving the performance of drawing in a second input signal with respect to a first input signal of a phase comparator. Therefore, when the present invention is used in a PLL circuit such as a VTR, great effects can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the present invention, FIG. 2 is a detection circuit diagram of the present invention, FIG. 3 is a waveform diagram of each part of the present invention, and FIG. 4 is a circuit diagram of a low-pass filter of the present invention. 1... terminal, 2... phase comparator, 3...
...Low pass filter, 4...Voltage controlled oscillator, 5...1/n frequency divider (n is any natural number), 6...Detection circuit, 7...terminal,
8...AND gate, 9...Mono multi, 10-13...Terminal. Name of agent: Patent attorney Toshio Nakao (1 person) ←

Claims (4)

[Claims] (1) The output of the phase comparator is input to a voltage controlled oscillator after passing through a low-pass filter, and at the same time as the output of the voltage controlled oscillator is output, input to a 1/n frequency divider (n is any natural number). , by inputting the output of the 1/n frequency divider to the second input of the phase comparator, a signal that is phase-locked with the first input signal input to the first input of the phase comparator is generated. A PLL circuit, in which a detection circuit detects whether or not the phase of a second input signal is locked with respect to a first input signal and outputs a control signal, and the time constant of the low-pass filter is switched by the control signal. A signal processing circuit characterized by: (2) The signal processing circuit according to claim (1), wherein the first input signal is a signal obtained based on a horizontal synchronization signal of a video signal. (3) The signal processing circuit according to claim (1), wherein the low-pass filter is capable of changing a time constant based on a control signal obtained by the detection circuit. (4) The detection circuit inputs the first input signal and the second input signal of the phase comparator, and detects the signal when the phase of the second input signal is not locked with respect to the first input signal. The signal processing circuit according to claim 1, wherein the signal processing circuit outputs the following.