JPS63155462A - Sound signal recorder - Google Patents

Abstract

PURPOSE:To record and reproduce a sound signal of a wide band and also to reduce a quantizing noise by executing the encoding by an ADPCM system, adding an error correcting code to a prediction coefficient and range information and also dispersing and arranging the continued prediction coefficient and range information in plural areas, and recording them. CONSTITUTION:The titled recorder executes encoding by an ADPCM (adaptive difference PCM) system, and provided with an error correcting encoder 14 for adding an error correcting code to a prediction information and range information after encoding, and an arrangement converting means 15 for dispersing and arranging the continued prediction coefficient and range information in plural areas. By executing the encoding by the ADPCM system, the number of quantizing bits can be decreased. Accordingly, a sampling frequency in an A/D converter and the number of quantizing bits can be increased, a recording and reproducing band of a sound signal is widened, and also, the quantization noise can be reduced.

Description

[Detailed description of the invention] The present invention will be explained in the following order.

A. Field of industrial application B. Overview of the invention C. Prior art D. Problem to be solved by the invention E. Means for solving the problem (Figs. 1 and 3) F
Effect G Embodiment G1 Description of configuration G2 Description of operation H Effect of invention A Field of industrial application The present invention relates to an audio signal recording device that encodes an audio signal and records it on a recording medium as a digital signal.

B. Summary of the Invention The present invention provides an audio signal recording device that encodes an audio signal and records it on a recording medium as a digital signal.
By using the DPCM method, adding an error correction code to the prediction coefficients and range information, and recording continuous prediction coefficients and range information in a distributed arrangement in multiple areas, it is possible to record wideband audio signals. The present invention is designed to enable recording and reproduction, reduce quantization noise, and sufficiently protect prediction coefficients and range information.

C. Conventional Technology As one of the rotary head type VTRs, as shown in Figure 5, a magnetic tape (2) is wound around a tape guide drum (1) over an angular range of over 216 degrees, and the magnetic tape (2) is wound around a tape guide drum (1) over an angular range of more than 216 degrees.
Two rotating magnetic heads H arranged with an angular spacing of °
A and HB are scanned, and as shown in FIG. 6, one part of the video signal is placed in the bone area AP in an angular range of about 36 degrees from the point where the rotary magnetic heads HA and HB start scanning in the recording track.
It is proposed to convert the audio signal related to one field into PCM and record it in a time-axis compressed state, and then record the video signal for one field in the 180' angular range bone area AV. has been done.

FIG. 7 shows an audio signal recording and reproducing system of such a VTR.

In the figure, the left signal SL and right signal SR of the audio signal are passed through the input terminals (31L) and (31R) and the pre-emphasis circuit (32) to the A/D converter (33).
) and converted into a digital signal. in this case,
For example, the sampling frequency is set to 31.5 KHz, and one sample is set to 10 points, and the left signal SL and right signal SR are sampled.

The 10-bit digital data from this A/D converter (33) is converted into 8-bit digital data by a 10-8 conversion circuit (34), and then sent to a signal processing circuit (35).
is supplied to

In the signal processing circuit (35), processing such as interleaving and addition of error correction/detection codes is performed.

In this case, a CRC code is used as an error detection code, and a simple parity (P, Q) code is used as an error correction method.
A cross-interleave method using

Furthermore, the data per field is composed of 132 blocks from #0 to #131 as shown in Figure 8, and these 132 blocks are interleaved by being distributed and arranged in three areas. There is. That is, FIG. 9 shows the data arrangement of one field's worth of data.

One word has 8 bits, and m x n = 1056 words (m = 8 words, n = 132 blocks).

NT when sampling frequency is 31.5KHz
The digital data for one field in the SC method is 105
Since it is 0 word, the discrimination data IDo is 6 words.

ID1. ...IDs will be added. In other words, (Lo, Ro, Ll, RL, L2.R2,...

Ls2i + R523+ L524 + R5
The above-mentioned 6-word discrimination words IDo to IDs are added to the beginning of 1 field of digital data that continues with 24). The 1056 words of data including the 6 words of discrimination data IDo"lDs are divided into 4 rows in the horizontal direction every 2 words.
They are arranged at intervals of 4 blocks. In hardware, data is written to addresses separated by 44 blocks by RAM address control. Apart from control data or parity data, (Li, Ri) (i
=o~524) are arranged in the horizontal direction.

The reason why the digital data is interleaved by dividing into three in the horizontal direction is to increase the burst error length that can be corrected, for example, by interpolating the average value. In particular, (Li, Ri
) by arranging them in the horizontal direction, the correction length can be made longer than by arranging them in the vertical direction.

Two parities, for example, even parity, are added to this one field of audio data and discrimination data. The digital data series of each line of the above configuration is WO+
When Wx + . Further, a second parity sequence Q is formed from nine words taken out at a distance of 12 blocks from each of a total of nine sequences, the digital data sequence W o '' W t and the parity sequence P. first parity series P
is placed at the center of one block, and the second parity series Q
is placed at the end of one block. In other words, since there is a high probability that data at the central position within one block will be uncorrectable, a parity sequence P that is less important than audio data is allocated, and this parity sequence P is generated by In order to maximize the distance between words, the parity series Q is arranged at the end of one block.

Each of the 132 blocks includes 8 words of digital data and 2 words of parity data, and a 16-bit CRC code for error detection, for example, is added to the data of each block, and a 3-bit CRC code is added to the data of each block. A block synchronization code of 8 bits and a block address code of 8 bits are added.

Further, from the signal processing circuit (35), a first block,
The digital data is outputted in the order of the second block, . . . , the 132nd block, and is supplied to the time axis compression circuit (36). is time-axis compressed to the area AP mentioned above. The time compression rate in this case is, for example, l/6
．． 84, and the digital data output from this time axis compression circuit (36) is 5.8 Mbps.

The digital data output from the time axis compression circuit (36) is subjected to, for example, bi-phase transformation in a modulator (37), and then supplied to the rotating magnetic disks HA and HB via a recording amplifier (38). and recorded on magnetic tape (2).

In addition, from the magnetic tape (2), the rotating magnetic disks HA and H
The digital data reproduced by B is sent to the reproduction amplifier (39).
The signal is supplied to the demodulator (40) via the . This demodulator (4
The digital data demodulated by 0) is sent to the time axis expansion circuit (4
In step 1), the time axis is expanded to one field time and then supplied to the signal processing circuit (42). This signal processing circuit (
42), processing such as dinterleaving, error detection, and error correction is performed.

The 8-bit digital data output from the signal processing circuit (42) is converted into 10-bit digital data by the 8-101 conversion circuit (43). The output of this 8-10 conversion circuit (43) is converted into an analog signal by a D/A converter (44) and then supplied to a de-emphasis circuit (45). The left signal SL and right signal SR of the audio signal are obtained at the output terminals (46L'') and (46R) derived from this de-emphasis circuit (45), respectively.

D. Problems to be Solved by the Invention As described above, in the example shown in FIG. 7, the audio signal can be converted into PCM and recorded and reproduced satisfactorily on the magnetic tape (2).

However, according to the example in FIG. 7, the sampling frequency in the A/D converter (33) is -31.5KH.
z and 1 sample IO bit, the recording/reproduction band of the audio signal was as narrow as 15.75KIIz, and the quantization noise was large.

In view of these points, the present invention aims to widen the recording/reproduction band of audio signals and reduce quantization noise.

E. Means for Solving Problems (FIGS. 1 and 3) The present invention performs encoding using the ADPCM (adaptive differential PCM) method. The present invention also includes an error correction encoder (14) that adds an error correction code to the encoded prediction coefficients and range information, and an array conversion means (15) that distributes and arranges the continuous prediction coefficients and range information in a plurality of areas. and

F By using the ADPCM method for effect encoding, the number of quantization bits can be reduced. Therefore, the sampling frequency and number of quantization bits in the A/D converter can be increased, making it possible to record audio signals. It is possible to widen the reproduction band and reduce quantization noise.In addition, error correction codes are added to the prediction coefficients and range information, and continuous prediction coefficients and range information are distributed and arranged in a plurality of areas. Since the information is recorded, important prediction coefficients and range information can be sufficiently protected in the ADPCM method.

G. Example Hereinafter, an example of the present invention will be described with reference to FIG. In this example, the present invention is applied to a rotary head type VTR that records audio signals as digital signals on a magnetic tape. In FIG. 1, parts corresponding to those in FIG. 7 are designated by the same reference numerals, and detailed explanation thereof will be omitted.

Explanation of G1 configuration In FIG. 1, the left signal SL and right signal SR of the audio signal
is the A/D through input terminals (IIL) and (IIR).
The signal is supplied to a converter (12) and converted into a digital signal. In this case, the sampling frequency is 48KH2, 1 sample is 16 bits, and the left signal SL
and the right signal SR are sampled. The 16-bit digital data from this A/D converter (12) is
The signal is supplied to the M encoder (13) and encoded using the ADPCM method.

This encoder (13) is configured as shown in FIG. 2, for example. Since this encoder (13) has a conventionally well-known configuration, a detailed explanation will be omitted, but the input terminal (131
) is processed block by block.

In this case, in a VTR like this example, it is desirable to complete the data processing for each track, and the blocks are divided so that there is no excess data for one track, that is, one field, and evenly across all blocks. It is said to be a number that can be divided into That is, as mentioned above, the sampling frequency in the A/D converter (12) is 48 K I
Since the data amount for one field is 800 samples each for the left signal SL and right signal SR, the total is 1600 samples. Therefore, in this example, 1
The data of the block is assumed to be 40 samples. As a result, there are 20 blocks related to the left signal SL and 20 blocks related to the right signal SR, for a total of 40 blocks, and data processing can be completed for each track.

16-bit digital data X to input terminal (131)
(n) is supplied, the prediction coefficient calculation circuit (132) uses the digital data X (
n), the correlation of the data is taken, and the prediction coefficient is calculated. Then, the digital data X (n) is converted into a prediction residual d (nl) by the prediction coefficient of each block in the prediction residual calculation circuit (133).Then, this prediction residual d (n) is converted into a prediction residual d (nl) by the prediction residual calculation circuit (133). 134), it is rounded to a certain number of bits, in this example 4 bits.

In this case, the error due to rounding is taken into account by the circuit (135), and rounding is performed in a manner appropriate to the range of data within the block using the range information from the intra-block maximum value detection circuit (136). As a result, 4×8 bit prediction coefficients (when a 4th order prediction filter is used, in this case there are 4 coefficients) are obtained, and furthermore, 8 bit range information is obtained at the output terminal (139).

Therefore, the residual data d(n) is 4 bits, the prediction coefficient is 4 x 8 bits, and the range information is 8 bits.
The average bit length is 4015 bits/word, and 16 bit data is compressed to 5 bits.

As described above, the digital data from the encoder (13) is residual data, prediction coefficients for each block, and range information (hereinafter referred to as "side chain"). Digital data from this encoder (13) is supplied to a side chain error correction encoder (14). This encoder (14) cannot add an error correction code to the side chain. As the error correction code, for example, a Reed-Solomon code on CF (28) is used. At this time, one word of data is 8 bits.

By the way, since the residual data has 4 pints, two pieces of residual data make up one word, and the data for one track, therefore one field, is the residual data...800
Word side chain... 200 words.

Now, the side chain for each block is 5 words each, and the side chain for each of the 20 blocks related to the left signal SL is li+I12+...12o1-each of the 20 blocks related to the Mangoku signal SR. Sidechain! + r2 +...r20, then 11 and r
(12
, 10) is added. In this case, as will be described later, an error correction coding system is configured for each distributed area (see FIG. 3).

Further, the digital data with the error correction code added to the side chain by the encoder (14) is processed by the array conversion circuit (15).
). In the array conversion circuit (15), the side chain to which the error correction code C1 has been added is divided into three areas (see areas A, B, and C in FIG. 9) during the interleaving process in the signal processing circuit (35). )
The array is converted so that it is a distributed array. That is, as shown in FIG. 3, areas of (10 + 2) x 7-84 words are taken corresponding to areas A, B, and C, respectively.
Sidechain E1 and rl+N4 and r41Jt and r7+
... is in area A, 12 and r2, j2s and rs,
aa and r@,...” are in area B, 13 and r3, f6
and rs.

j29 and r9+ . . . are array-converted so that they are distributed and arrayed in area C.

Here, the total number of words of digital data output from the array conversion circuit (15) is: Total number of words=Residual data+Side chain+Error correction code=800+252=1052 words.

Digital data output from the array conversion circuit (15) is supplied to the B-side terminal of the switch circuit (16).

Moreover, the A side terminal of this switch circuit (16) has a 10
Digital data output from the -8 conversion circuit (34) is supplied, and the output of this switch circuit (16) is supplied to the signal processing circuit (35).

Further, the digital data output from the reciprocating signal processing circuit (42) is supplied to the 8-10 conversion circuit (43) via the A side of the switch circuit (17), and is also supplied via the B side of the switch circuit (17). It is supplied to the array conversion circuit (18). This array conversion circuit (18) performs an array conversion that is inverse to the process of the above-described recording system array conversion circuit (15). The digital data output from the array conversion circuit (18) is supplied to a side chain error correction decoder (19), and in this decoder (19) side chain error detection and correction processing is performed using a Reed-Solomon code. Then, this decoder (19) outputs residual data and side chain as digital data, which is A
The signal is supplied to the DPCM decoder (20).

This ADPCM decoder (20) is configured as shown in FIG. 4, for example. This PCM decoder is supplied with a slave, 4×8 bit prediction coefficients are supplied to an input terminal (202), and 8-bit range information is supplied to an input terminal (203). Then, the rounded residual data is returned to range-independent data by the range information, and the original data is predicted by the prediction coefficient by the predictor (204), and 16-bit digital audio is output to the output terminal (205). Data is output.

The 16-bit digital audio data from this decoder (20) is sent to the D/A controller (21).
A left signal SL and a right signal SR of the audio signal are obtained at output terminals (22L) and (22R) derived from this D/A converter (21), respectively.

The rest of the structure is the same as the example shown in FIG.

Description of G2 operation This example is constructed as described above, and when the switch circuits (16) and (17) are connected to the A side, the configuration is similar to that of the example in FIG. 7, and recording and reproduction are performed in the same manner.

Also, when the switch circuits (16) and (17) are connected to the B side, the ADPCM encoder (13)
Digital data encoded using the PCM method is recorded and reproduced. That is, the error correction code C1 is added to the side chain from the array conversion circuit (15), and the digital data subjected to the array conversion is supplied to the signal processing circuit (35) via the switch circuit (16), and is interleaved and error-corrected. Processing such as addition of correction/detection codes is performed. As mentioned above, in this interleaving process, the side chain to which the error correction code C1 is added is divided into three areas (A, B in FIG. 9).
, area C)). The digital data output from this signal processing circuit (35) is time-base compressed in a time-base compression circuit (36), and then sent to a modulator (37).
It is supplied to the rotating magnetic heads HA and HB via the recording amplifier (38), and recorded on the magnetic tape (2).

Also, from the magnetic tape (2), the rotating magnetic heads HA and T
(The digital data played back by B is transferred to the playback amplifier (39
) to the demodulator (40). This demodulator (
The digital data demodulated by 40) is sent to the time axis expansion circuit (
41), the time axis is expanded to one field time and then supplied to the signal processing circuit (42), where it is dinterleaved and
Processing such as error detection and error correction is performed. The digital data output from the signal processing circuit (42) is supplied to the array conversion circuit (18) via the switch path (17).
After the array transformation circuit (15) of the recording system performs the reverse array transformation, the signal is supplied to the side chain error correction decoder (19), where the side chain error detection and correction processing is performed. And this decoder (1
9) outputs the residual data and side chain as digital data and supplies it to the ADPCM decoder (20), which outputs 16-bit digital audio data. This 16-bit digital audio data is converted into a D/A converter (21
), and the left signal SL and right signal SR of the audio signal are obtained at the output terminals (22L) and (22R), respectively.

In this case, the total number of words of digital data from the array conversion circuit (15) is 1052 words as described above,
Since the total number of words of digital data processed in the signal processing circuit (35) is smaller than 1056, recording and reproduction can be performed satisfactorily without missing digital data.

In this way, according to this example, since the ADPCM method is used for encoding, the sampling frequency and number of bits in the A/D converter can be increased, and the recording and playback band of audio signals can be widened (as well as quantization It is possible to reduce noise.

Furthermore, according to this example, an error correction code (Reed-Solomon code) is added to the side chain, that is, the prediction coefficient and range information, and continuous side chains are distributed and recorded in three areas, so the ADPCM method can fully protect important sidechain data. In particular, it is resistant to burst errors, and the side chain does not make continuous errors, making error correction easier.

Further, according to this example, even in the recording and reproducing system of digital data encoded by the ADPCM method, the recording system and the signal processing circuit (42) below the conventional signal processing circuit (35)
) can be used in common, so it can be constructed at low cost.

In the above-mentioned embodiment, the side chains are distributed and recorded in three areas, but the invention is not limited to this. Similar effects can be obtained by performing array conversion in (15).

H Effects of the invention According to the invention described above, encoding is performed using the ADPCM method, an error correction code is added to the prediction coefficients and range information, and continuous prediction coefficients and range information are distributed to multiple areas. Since recording is arranged in an array, the sampling frequency and number of bits can be increased, the recording and playback band of audio signals can be widened, quantization noise can be reduced, and prediction Coefficient and range information can be well protected.

[Brief explanation of the drawing]

Figure 1 is a configuration diagram showing one embodiment of the present invention, Figures 2 to 4
5 is a diagram for explaining the rotary head device, FIG. 6 is a diagram showing a recording track pattern, FIG. 7 is a diagram of a conventional example, and FIGS. 8 and 9 are diagrams thereof. It is a figure for explanation. (13) is ADPCM F: I-ta, (14) 4!
-'J-()' chain error correction encoder, (15)
and (18) are array conversion circuits, (19) are side chain error correction decoders, and (20) are ADPCM decoders.

Claims (1)

[Claims] An audio signal recording device that encodes an audio signal and records it on a recording medium as a digital signal includes an ADPCM encoder that performs the encoding, and an error correction encoder that adds an error correction code to the encoded prediction coefficients and range information. . Arrangement conversion means for distributing and arranging the continuous prediction coefficients and range information in a plurality of areas.