JPS63153860A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To stabilize the region to be metallic silicified by a method wherein, in the formation of polycide layer making a high melting point metallic layer solid-react with a polycrystalline layer, a high concentration phosphorus implanted layer is provided in the intermediate part of polycrystalline silicon layers. CONSTITUTION:The first non-doped polycrystalline silicon layers 2a, 2c are formed on a substrate 1 and then high concentration phosphorus is implanted in the surface of the first polycrystalline layers. Then, the second non-doped polycrystalline silicon layer 2 in contact with the surface layer is formed. Next, a high melting point metallic layer 3 in contact with the surface of the second polycrystalline silicon layer 2 is formed to form a polycide layer 5 by making the high melting point metallic layer 3 solid-react with the second polycrystalline silicon layer 2. As mentioned so far, the solid reaction of high melting point metal to polycrystalline layer 2 is obstructed in the region implanted with phosphorus proportionally to the phosphorus concentration. Resultantly, the solid reaction in case of forming the polycide layer 5 is obstructed in the surface layer so that the first polycrystalline silicon layer may be left evenly stabilizing the region to be metallic silicified.

Description

[Detailed Description of the Invention] [Summary] In forming a polycide layer in which a high melting point metal layer is subjected to a solid phase reaction with a polycrystalline silicon layer, metal silicide is formed by providing a high concentration phosphorus implantation layer in the middle of the polycrystalline silicon layer. This is aimed at stabilizing the area that is subject to change.

[Industrial application field]

The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming a polycide layer in which a high melting point metal layer is subjected to a solid phase reaction with a polycrystalline silicon layer.

The polycide layer is a two-layer conductive layer consisting of a polycrystalline silicon layer and a metal silicide layer thereon.
It is used for the gate electrode of a Mis-type semiconductor device in which source and drain regions are formed by self-alignment, and has a feature of lower resistance than the conventionally used case of using only a polycrystalline silicon layer.

When used as the gate electrode, it is important to reliably maintain the underlying polycrystalline silicon layer.

[Conventional technology]

FIG. 2 is a step-by-step side view (a) to (d+) of an example of a conventional method for forming a polycide layer to serve as a gate electrode by solid phase reaction.

In the figure, first of all, [see figure (al)] polycrystalline silicon with a thickness of about 0.4 μm doped with phosphorus (P) by CVD (chemical vapor deposition) is placed on a substrate l having a gate insulating film 1a on its surface. Form layer 2.

Next, as shown in the figure (bl), a refractory metal layer 3 made of titanium (Ti) having a thickness of approximately 0.1 μm is formed on the polycrystalline silicon layer 2 by sputtering.

Next [see Figure (C)], the high melting point metal layer 3 is subjected to a solid phase reaction with the polycrystalline silicon layer 2 by heat treatment at about 700° C. to form a metal silicide layer 4. The heat treatment at this time is stopped before the solid phase reaction reaches the gate insulation 1*la so that the polycrystalline silicon layer 2 remains.

In this way, a polycide layer 5 having a two-layer structure made up of the polycrystalline silicon layer 2 and the metal silicide layer 4 is completed.

After this, see Figure C (d)], polycide layer 5 and gate insulating film 1a are patterned to form polycide gate electrode 6, and using this as a mask, source/drain regions 7 are formed.

[Problem that the invention seeks to solve]

In the conventional method, the solid phase reaction for forming the polycide layer 5 does not progress uniformly in the direction of the gate insulating film 1a, and as shown in FIG. It may reach the gate insulating film 1a and lower the gate breakdown voltage. Moreover, if the degree of heat treatment is suppressed for fear of this, sufficient metal silicide layer 4 will not be formed. Therefore, in this solid-phase reaction, the control of heat treatment is extremely delicate, and there is a problem that stability is lacking during mass production.

[Means for solving problems]

The above problem lies in the process of forming a non-doped first polycrystalline silicon layer on a substrate and implanting phosphorus at a high concentration into the surface layer of the first polycrystalline silicon layer, and forming a second polycrystalline silicon layer;
The present invention forms a polycide layer including the step of forming a high melting point metal layer in contact with the surface of the second polycrystalline silicon layer and causing a solid phase reaction between the high melting point metal layer and the second polycrystalline silicon layer. The problem is solved by the manufacturing method.

[Effect]

The solid-state reaction of the refractory metal to the polycrystalline silicon layer is inhibited when it encounters a phosphorus-implanted region, and is more strongly inhibited as the phosphorus concentration increases.

Therefore, when the solid phase reaction to form the polycide layer reaches the surface layer, its progress is stopped, leaving the first polycrystalline silicon layer uniformly, and the region to be converted into metal silicide becomes stable. become

For this reason, the formed polycide layer reliably retains the underlying polycrystalline silicon layer while ensuring a sufficient metal silicide layer without requiring delicate control of the solid-phase reaction heat treatment.

〔Example〕

Examples of the method of the present invention will be described below with reference to step-by-step side views (a) to (d) of FIG. The same reference numerals indicate the same objects throughout the figures.

The embodiment shown in FIG. 1 corresponds to the conventional method example shown in FIG.

That is, in FIG. 1, first of all, a non-doped polycrystalline silicon layer 2a having a thickness of about 0.2 μm is formed by CVD on a substrate l having a gate insulating film 1a on its surface.
(the above-mentioned first polycrystalline silicon layer) is formed, and phosphorus is ion-implanted into the surface portion at a dose of 1015/cnl to form the phosphorus-implanted layer 2b (the above-mentioned surface layer).

Next (see Figure (b)), a non-doped polycrystalline silicon layer 2c (the above-mentioned second polycrystalline silicon layer) with a thickness of about 0.2 μm is formed by CVDC, and then a polycrystalline silicon layer 2c with a thickness of about 0.1 μm is formed by sputtering. High melting point metal layer 3 made of titanium
form.

Next, as shown in FIG. However, phosphorus is not sufficiently diffused in the polycrystalline silicon layer 2a with the phosphorus injection layer 2b.

At this time, the solid phase reaction progresses toward the phosphorus injection layer 2b, but when it encounters the phosphorus injection layer 2b with a high phosphorus concentration, the progress is blocked, so the progress within the polycrystalline silicon layer 2C is uneven. Also, the polycrystalline silicon layer 2a is left uniformly. However, this heat treatment does not require delicate control as in conventional methods.

Next [see figure (d)], the polycide layer 5 and the gate insulating film 1a are patterned to form a polycrystalline silicon layer 2a.
forming a polycide gate electrode 6 in an incomplete state;
Using this as a mask, source/drain regions 7 are formed. Since activation heat treatment is performed when forming source/drain regions 7, polycrystalline silicon N
2a shows that the phosphorus in the phosphorus injection layer 2b is sufficiently diffused as shown in FIG.
C) A polycrystalline silicon layer 2 corresponding to that shown in the figure is formed, and a polycide gate electrode 6 made of a completed polycide layer 5 is formed.

Note that, prior to the formation of the source/drain regions 7, the above-described phosphorus diffusion into the polycrystalline silicon layer 2a may be performed independently by a separate heat treatment.

(Since the formed polycide gate electrode 6 has a sufficient amount of metal silicide layer 4 and does not reach the gate insulating film 1a, it exhibits the characteristic of low resistance without reducing the gate withstand voltage. .

The solid phase reaction of its formation does not require delicate control of heat treatment as in conventional methods, and is therefore stable even during mass production.

In the above embodiment, titanium was used as the material for the high melting point metal layer 3, but other high melting point metals, such as zirconium (Zr), which form the metal silicide layer 4 through a solid phase reaction with the polycrystalline silicon layer 2c, may be used. etc. may be used.

〔Effect of the invention〕

As explained above, according to the configuration of the present invention, in forming a polycide layer in which a high melting point metal layer is subjected to a solid phase reaction with a polycrystalline silicon layer, it is possible to stabilize the region to be metal silicided, and for example, This has the effect of enabling stable mass production of MIS type semiconductor devices using polycide gate electrodes.

[Brief explanation of the drawing]

FIG. 1 is a step-by-step side view of an embodiment of the method of the present invention, FIG. 2 is a step-by-step side view of a conventional method, and FIG. 3 is a diagram illustrating problems in the conventional method. In the figure, ① is a substrate, 1a is a gate insulating film, 2 is a phosphorous-doped polycrystalline silicon layer, 2a and 2c are non-doped polycrystalline silicon layers, 2b is a phosphorous injection layer, 3 is a high melting point metal layer, 4 is a metal silicide layer , 5 is a polycide layer, 6 is a polycide gate electrode, and 7 is a source/drain region. Honko Akiho crush fruit is an example of the process p1 printing/1 page drawing # 1 Cause! # On the other hand, the process of 6 cases, 1 thickness, 1 m, [Shiflo 2 Figure # 3 Figure

Claims (1)

[Claims] a step of forming a first non-doped polycrystalline silicon layer on a substrate and implanting phosphorus at a high concentration into the surface layer of the first polycrystalline silicon layer; and a second non-doped polycrystalline silicon layer in contact with the surface layer. a step of forming a crystalline silicon layer; and a step of forming a high melting point metal layer in contact with the surface of the second polycrystalline silicon layer and causing a solid phase reaction between the high melting point metal layer and the second polycrystalline silicon layer. 1. A method of manufacturing a semiconductor device, comprising: forming a polycide layer.