JPS63153840A - Selective oxidation isolating method - Google Patents

Selective oxidation isolating method

Info

Publication number
JPS63153840A
JPS63153840A JP30252186A JP30252186A JPS63153840A JP S63153840 A JPS63153840 A JP S63153840A JP 30252186 A JP30252186 A JP 30252186A JP 30252186 A JP30252186 A JP 30252186A JP S63153840 A JPS63153840 A JP S63153840A
Authority
JP
Japan
Prior art keywords
substrate
film
silicon nitride
nitride film
groove
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP30252186A
Other languages
Japanese (ja)
Inventor
Takaaki Kuwata
孝明 桑田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP30252186A priority Critical patent/JPS63153840A/en
Publication of JPS63153840A publication Critical patent/JPS63153840A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent the narrowing of the effective channel width of an MOS transistor even when the width of an active region is 1mum or less by a method wherein, after the side face of a groove and an active region have been coated with a silicon nitride film, a polycrystalline silicon layer is buried contacting to the exposed surface of a substrate on the bottom part of the groove, and said layer is oxidized. CONSTITUTION:A thermally oxided film 12 and the first silicon nitride film 13 are grown on a substrate 11, the region which becomes a field region is etched, a groove is formed in the substrate 11, and the impurities having the conductive type same as the substrate 11 are ion-implanted. Then, after the second silicon nitride film has been grown on the substrate 11, the second silicon nitride film 15 is left on the side face only of the groove by performing anisotropic etching, a polycrystalline film 16 is grown on the substrate 11, and photoresist 17 is thickly coated thereon. Then, the photoresist 17 and the polycrystalline silicon film 16 are anisotropically etched, and a flat polycrystalline silicon film 16' is left in the groove only of the substrate 11. Then, the whole surface of the substrate 11 is thermally oxided, and the polycrystalline silicon film 16' in the groove is oxided.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、シリコン集積回路の製造方法、特に素子間分
離方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a silicon integrated circuit, and particularly to a method for isolating elements.

〔従来の技術〕[Conventional technology]

LSI製造技術における素子間分離方法としては、シリ
コン窒化膜をマスクとして選択酸化によ多形成した厚い
酸化膜を用いるLOCO8法が一般的である。しかしL
OCO8法でフィールド領域を形成すると、バーズビー
クが活性領域内に張り出してくるため、活性領域の面積
が小嘔くなるという不利な点があり、そこで以下に示す
ような改良LOCO8法によるフィールド領域形成が行
なわれている。この改良LOCO8法は、シリコン基板
上に薄い酸化膜および第1シリコン窒化膜を形成した後
、前記膜を予定された活性領域を残してエツチングし、
さらにこの残された膜の側面に第2シリコン窒化膜を形
成して熱酸化用マスクを形成し、フィールド予定領域を
選択酸化する方法である。
As a device isolation method in LSI manufacturing technology, the LOCO8 method is generally used, which uses a thick oxide film formed by selective oxidation using a silicon nitride film as a mask. But L
When a field region is formed using the OCO8 method, the bird's beak protrudes into the active region, which has the disadvantage that the area of the active region becomes small. It is being done. This improved LOCO8 method involves forming a thin oxide film and a first silicon nitride film on a silicon substrate, and then etching the film leaving a predetermined active region.
Furthermore, a second silicon nitride film is formed on the side surface of this remaining film to form a mask for thermal oxidation, and the intended field area is selectively oxidized.

この方法を以下、落3図で説明する。第3図(a)に示
すように、シリコン基板(以下、単に基板という) 3
1上に約50OAの酸化膜32および約2000^の第
1シリコン窒化膜あを成長させる。
This method will be explained below using three figures. As shown in FIG. 3(a), a silicon substrate (hereinafter simply referred to as a substrate) 3
An oxide film 32 of about 50 OA and a first silicon nitride film 32 of about 2000 OA are grown on the first silicon nitride film.

次に第3図(b)に示すように、フィールド予定領域上
の前記酸化膜32.第1シリコン窒化膜33をエツチン
グして基板310表面を露出させた後、基板31と同一
伝導型の不純物あをイオン注入する。その後、基板31
上に第2シリコン窒化膜を約50OA成長させた後、異
方性エツチングによシ、活性予定領域にある酸化膜32
!、第1シリコン窒化膜ゴの側面に第2シリコン窒化膜
あを残しておく。
Next, as shown in FIG. 3(b), the oxide film 32. After the first silicon nitride film 33 is etched to expose the surface of the substrate 310, impurity ions having the same conductivity type as the substrate 31 are implanted. After that, the board 31
After growing a second silicon nitride film of about 50 OA on top, anisotropic etching is performed to remove the oxide film 32 in the area to be activated.
! , a second silicon nitride film is left on the side surface of the first silicon nitride film.

以上によシ熱酸化用マスクが、活性予定領域に形成され
るので、基板31全面を熱酸化し第3図(e)に示すよ
うに厚いフィールド酸化膜(約800OA)36および
チャネルストッパ層37を形成する。この方法の利点は
上記の熱酸化用マスクが上面・側面がともにシリコン窒
化膜におおわれているので、熱酸化のとき、酸化性ふん
い気が活性領域内に侵入するのを防ぎ、バーズビークの
伸びを抑えることにある。
Since the thermal oxidation mask is formed in the area to be activated as described above, the entire surface of the substrate 31 is thermally oxidized to form a thick field oxide film (approximately 800 OA) 36 and a channel stopper layer 37 as shown in FIG. 3(e). form. The advantage of this method is that both the top and side surfaces of the thermal oxidation mask are covered with a silicon nitride film, which prevents oxidizing air from entering the active region during thermal oxidation, and prevents the bird's beak from elongating. The goal is to suppress the

次に、第3図(d) K示すように、第1・第2シリコ
ン窒化膜3γ・あを除去した後、薄い酸化膜32′を除
去して活性領域の基板表面を露出してから、MOSトラ
ンジスタの場合にはゲート酸化膜あを形成する。
Next, as shown in FIG. 3(d) K, after removing the first and second silicon nitride films 3γ and A, the thin oxide film 32' is removed to expose the substrate surface in the active region. In the case of a MOS transistor, a gate oxide film is formed.

ところで、上記の改良LOCO8法は、バーズビークの
伸びを抑えるが、第3図(clに示すようにフィールド
酸化膜あは、その一部が活性領域の下方に伸びている。
By the way, although the above-mentioned improved LOCO8 method suppresses the extension of the bird's beak, as shown in FIG. 3 (cl), the field oxide film partially extends below the active region.

またイオン注入された不純物が拡散して形成したチャネ
ルストッパ層37も同じように活性領域に侵入する。
Similarly, the channel stopper layer 37 formed by the diffusion of ion-implanted impurities also invades the active region.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した改良LOCO8法では、バーズビークの活性層
領域内への伸びは、約α3〜α4μmと少ないものの、
全く無視できるものでは々く、半導体装置が微細化する
にともない、問題となってきておシ、活性領域の幅が1
μm以下の幅を有する半導体装置には適用不可能である
In the improved LOCO8 method described above, the extension of the bird's beak into the active layer region is small at approximately α3 to α4 μm;
This is often completely negligible, but as semiconductor devices become smaller, it has become a problem.
It is not applicable to semiconductor devices having a width of less than μm.

また、チャネルスト、ツバ層も活性領域内に侵入してお
り、MOS)ランジスタの場合、活性領域に半導体基板
と逆伝導型の不純物の拡散層を形成するので、その拡散
層とチャネルストッパ層との間に大きな容量が形成され
、半導体装置の高速動作の防げとなる。
In addition, the channel stopper layer and brim layer also invade the active region, and in the case of a MOS transistor, a diffusion layer of impurities of the opposite conductivity type to the semiconductor substrate is formed in the active region, so the diffusion layer and the channel stopper layer are A large capacitance is formed between them, which prevents high-speed operation of the semiconductor device.

また、熱駿化用マスクの第2シリコン窒化膜は、半導体
基板に直接接触嘔せることに依シ、バースビークが大き
く成長するのを防いでいるため、フィールド酸化膜が形
成される過程で、第2シリコン窒化膜の近傍では大きな
ストレスが生じ、結晶欠陥、拡散層の耐圧不良が発生し
易いという不都合がある。
In addition, the second silicon nitride film of the thermal oxidation mask relies on direct contact with the semiconductor substrate to prevent the birth beak from growing large. A large stress is generated in the vicinity of the 2-silicon nitride film, which is disadvantageous in that crystal defects and breakdown voltage defects in the diffusion layer are likely to occur.

本発明の目的は、上記の欠点を除去した、新規な選択酸
化分離方法を提供することにある。
An object of the present invention is to provide a new selective oxidation separation method that eliminates the above-mentioned drawbacks.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の選択酸化分離方法は、シリコン基板上に、酸化
膜・第1シリコン窒化膜を順に形成する工程と、フィー
ルド予定領域の前記酸化膜・第1シリコン窒化膜および
基板を所定の深さまでエツチングし溝を形成する工程と
、前記溝の底面の基板に、基板と同−伝導盤の不純物を
イオン注入する工程と、前記溝側面に第2シリコン窒化
膜からなるサイドウオールを形成する工程と、前記溝内
に所定の深さに多結晶シリコン膜を形成する工程と、基
板全面を熱酸化し、前記多結晶シリコン膜をフィールド
酸化膜に変化させる工程と、前記第1−第2シリコン窒
化at除去する工程と、前記第2シリコン窒化膜除去に
より生じた活性領域周辺の欠所を絶縁物で埋める工程と
を含むものである。この方法は、概略すると、フィール
ド予定領域の基板に溝を形成し、その溝の側面および活
性領域をシリコン窒化膜でおおった後、前記溝の底部の
基板の露出面に接して多結晶シリコン層を埋込み、この
多結晶シリコン層を酸化することで、フィールド酸化膜
とするものである。
The selective oxidation separation method of the present invention includes the steps of sequentially forming an oxide film and a first silicon nitride film on a silicon substrate, and etching the oxide film, the first silicon nitride film, and the substrate in a region where a field is to be formed to a predetermined depth. a step of forming a groove, a step of ion-implanting the same conductive impurity as the substrate into the substrate at the bottom of the trench, and a step of forming a sidewall made of a second silicon nitride film on the side surface of the trench; forming a polycrystalline silicon film to a predetermined depth within the groove; thermally oxidizing the entire surface of the substrate to change the polycrystalline silicon film into a field oxide film; The method includes a step of removing the second silicon nitride film, and a step of filling the void around the active region caused by the removal of the second silicon nitride film with an insulator. In general, this method involves forming a trench in a substrate in a region where a field is planned, covering the sides of the trench and the active region with a silicon nitride film, and then layering a polycrystalline silicon layer in contact with the exposed surface of the substrate at the bottom of the trench. A field oxide film is formed by burying the polycrystalline silicon layer and oxidizing the polycrystalline silicon layer.

〔実施例〕〔Example〕

以下、本発明の実施例につき、図面を参照して説明する
。第1図(a)に示すように、基板11上に薄い熱酸化
膜(約5.0OA ) 12および比較的薄い第1シリ
コン窒化膜(約150OA) 13を成長させる。第1
図(blに示すように、フィールド領域となるべき領域
の前記熱酸化膜12・第1シリコン窒化膜13および基
板11をエツチングし、基板11中に深さ0.8〜1.
0μmの溝を形成する。その後、前記基板11と伝導型
が同一の不純物をイオン注入する。この時活性領域上の
シリコン窒化膜11および酸化膜12!がマスクとな9
、前記不純物はイオン注入されない。
Embodiments of the present invention will be described below with reference to the drawings. As shown in FIG. 1(a), a thin thermal oxide film (approximately 5.0 OA) 12 and a relatively thin first silicon nitride film (approximately 150 OA) 13 are grown on a substrate 11. As shown in FIG. 1st
As shown in FIG.
Form a groove of 0 μm. Thereafter, impurity ions having the same conductivity type as the substrate 11 are implanted. At this time, silicon nitride film 11 and oxide film 12 on the active region! is a mask9
, the impurity is not ion-implanted.

次に第1図(e)に示すように、基板11上に約200
〜400Aの薄い第2シリコン窒化膜を成長させた後、
異方性エツチングによシ溝側面にのみ第2シリコン窒化
膜15を残す。この時、活性領域上の第2シリコン窒化
膜巧および第1シリコン窒化膜13′によって、活性領
域を形成する凸部が完全にシリコン窒化膜で覆われた状
態と々シ、溝底面部は露出した状態となる。その後、基
板11上に多結晶シリコン膜16を4000〜5000
^成長させ、その上にホトレジスト17を厚く塗布する
Next, as shown in FIG. 1(e), about 200
After growing a thin second silicon nitride film of ~400A,
The second silicon nitride film 15 is left only on the side surfaces of the groove by anisotropic etching. At this time, the convex portion forming the active region is completely covered with the silicon nitride film by the second silicon nitride film 13' and the first silicon nitride film 13' on the active region, and the bottom surface of the trench is exposed. The state will be as follows. After that, a polycrystalline silicon film 16 with a thickness of 4000 to 5000
^ grown, and a thick layer of photoresist 17 is applied thereon.

次に第1図(d)に示すようにホトレジスト17および
多結晶シリコン膜16を異方性エツチングする。この時
ホトレジスト17と多結晶シリコン膜16とのエツチン
グレートが同等となるエツチングを行々い、基板11の
溝内にのみ、平坦に多結晶シリコンj#16’t−残す
様にする。
Next, as shown in FIG. 1(d), the photoresist 17 and the polycrystalline silicon film 16 are anisotropically etched. At this time, etching is performed so that the etching rates of the photoresist 17 and the polycrystalline silicon film 16 are the same, so that a flat polycrystalline silicon j#16't- is left only in the groove of the substrate 11.

次に第1図(e)に示すように、基板11を全面熱酸化
することにより、溝中の多結晶シリコン膜1σを酸化膜
化すると同時に溝中の底面部の一部も酸化する。この時
4000〜5000 Aの膜厚の多結晶シリコン膜16
′が酸化膜化することによシ、溝中が酸化膜に依シ埋込
まれる。溝の側面に於いては第2シリコン窒化膜15が
存在するため活性領域内に、熱酸化膜が大きく侵入する
ことは表い。また、この熱処理によシ、基板11と同一
伝導型を有するチャネルストッパ層19が形成される。
Next, as shown in FIG. 1(e), by thermally oxidizing the entire surface of the substrate 11, the polycrystalline silicon film 1σ in the trench is turned into an oxide film, and at the same time, a part of the bottom surface of the trench is also oxidized. At this time, a polycrystalline silicon film 16 with a thickness of 4000 to 5000 A is formed.
′ becomes an oxide film, the groove is filled with the oxide film. Since the second silicon nitride film 15 exists on the side surfaces of the trench, it is obvious that the thermal oxide film will largely invade into the active region. Further, through this heat treatment, a channel stopper layer 19 having the same conductivity type as the substrate 11 is formed.

次に第1図(f)に示すように、ホットリン酸によシ、
第1・第2シリコン窒化膜13’、15をエツチング除
去してから、第2シリコン窒化膜15を除去したために
生じた狭いat−埋めるために、第1図瞳)に示すよう
に、再び熱酸化工程に依シ、溝側面の基板表面を熱酸化
膜化し、その体積膨張により溝を埋める。以上で酸化分
離されるので、MOSトランジスタの場合は、次に第1
図(h)に示すように、緩衝弗酸に依シ、活性領域上の
薄い熱酸化膜2oを除去し、新にゲート酸化膜21を形
成する。
Next, as shown in Fig. 1(f), hot phosphoric acid was added.
After the first and second silicon nitride films 13' and 15 are removed by etching, heat is applied again to fill the narrow at area created by removing the second silicon nitride film 15, as shown in Figure 1 (pupil). Depending on the oxidation process, the surface of the substrate on the side surfaces of the groove is formed into a thermal oxide film, and the groove is filled by the volume expansion. Since oxidation separation is performed above, in the case of a MOS transistor, the first
As shown in Figure (h), the thin thermal oxide film 2o on the active region is removed using buffered hydrofluoric acid, and a new gate oxide film 21 is formed.

上記実施例では、第1図(g)に示すように活性領域の
側面の第2シリコン窒化1115を除去して生じた欠所
を、熱酸化によシ埋めている。しかし別の方法で埋める
ようにしてもよい。次に別方法について第2図を参照し
て説明する。
In the above embodiment, as shown in FIG. 1(g), the defects created by removing the second silicon nitride 1115 on the side surfaces of the active region are filled by thermal oxidation. However, it may be filled in another way. Next, another method will be explained with reference to FIG.

第1図(flの工程が完了した後、第2図(alに示す
様に、前記基板11表面に7リカフイルム膜nを塗布に
よシ形成し、第2シリコン窒化膜15が除去されること
に依り生じた狭い溝を埋め、熱処理を施し、固化させる
。次に第2図(blに示す様に、緩衝弗酸に依り、活性
領域上の前記シリカフィルムa22及び薄い酸化膜銀を
除去し、新に、ゲート酸化膜21を形成する。
After the process of FIG. 1 (fl) is completed, as shown in FIG. 2 (al), a 7Lica film n is applied and formed on the surface of the substrate 11, and the second silicon nitride film 15 is removed. The resulting narrow grooves are filled and heat treated to solidify.Next, as shown in Figure 2 (bl), the silica film A22 and thin silver oxide film on the active area are removed using buffered hydrofluoric acid. Then, a new gate oxide film 21 is formed.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明の方法に依り、半導体基板
上のフィールド領域とまるべき領域、を形成した場合、
活性領域内にフィールド酸化膜が侵入しないので活性領
域の幅が1μm以下の場合においても例えばMOS型ト
ランジスタの実効チャネル幅が狭まることはない。
As explained above, when a field region on a semiconductor substrate is formed by the method of the present invention,
Since the field oxide film does not invade into the active region, the effective channel width of a MOS transistor, for example, will not be narrowed even when the width of the active region is 1 μm or less.

チャネルストッパ層はMOS)ランジスタの場合、拡散
層が形成される半導体基板表面よシも1μm程度深い領
域に存在するため、拡散層と直接接することはない。従
って、拡散層の容量が低減され、半導体装置の高速動作
に有利である。
In the case of a MOS transistor, the channel stopper layer exists in a region approximately 1 μm deeper than the surface of the semiconductor substrate where the diffusion layer is formed, so it does not come into direct contact with the diffusion layer. Therefore, the capacitance of the diffusion layer is reduced, which is advantageous for high-speed operation of the semiconductor device.

また、フィールド領域が大面積であっても小面積であっ
ても、同一の方法でフィールド領域の溝中に酸化膜を埋
込むことが可能である。さらに、溝中の多結晶シリコン
膜を酸化して、フィールド酸化膜としている丸め、酸化
防止用の第1・第2シリコン窒化膜にかかるストレスが
少なく、結晶欠陥、拡散層の耐圧不良が発生し難いとい
う効果がある。
Further, whether the field region has a large area or a small area, it is possible to bury the oxide film into the groove of the field region using the same method. Furthermore, by oxidizing the polycrystalline silicon film in the trench, there is less stress on the field oxide film, the first and second silicon nitride films for oxidation prevention, and crystal defects and breakdown voltage failures of the diffusion layer can occur. It has the effect of being difficult.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図、第2図は本発明の実施例を工程順に示した図、
第3図は従来例を工程順に示した図である。 11・・・シリコン基板、12.12!・・・酸化膜、
13 、13’・・・第1シリコン窒化膜、14・・・
イオン注入不純物、 15・・・第2シリコン窒化膜、 16 、16’・・・多結晶シリコン膜、17・・・ホ
トレジスト、18・・・フィールド酸化層、19・・・
チャネルストッパ層、 加・・・酸化膜、21・・・ゲート酸化膜、n・・・シ
リカフィルム膜。
Figures 1 and 2 are diagrams showing embodiments of the present invention in the order of steps;
FIG. 3 is a diagram showing a conventional example in the order of steps. 11...Silicon substrate, 12.12! ···Oxide film,
13, 13'...first silicon nitride film, 14...
Ion implantation impurity, 15... Second silicon nitride film, 16, 16'... Polycrystalline silicon film, 17... Photoresist, 18... Field oxide layer, 19...
Channel stopper layer, additive... oxide film, 21... gate oxide film, n... silica film film.

Claims (1)

【特許請求の範囲】[Claims] シリコン基板上に、酸化膜・第1シリコン窒化膜を順に
形成する工程と、フィールド予定領域の前記酸化膜・第
1シリコン窒化膜および基板を所定の深さまでエッチン
グし溝を形成する工程と、前記溝の底面の基板に、基板
と同一伝導型の不純物をイオン注入する工程と、前記溝
側面に第2シリコン窒化膜からなるサイドウォールを形
成する工程と、前記溝内に所定の深さに多結晶シリコン
膜を形成する工程と、基板全面を熱酸化し、前記多結晶
シリコン膜をフィールド酸化膜に変化させる工程と、前
記第1・第2シリコン窒化膜を除去する工程と、前記第
2シリコン窒化膜除去により生じた活性領域周辺の欠所
を絶縁物で埋める工程とを含むことを特徴とする半導体
装置の選択酸化分離方法。
a step of sequentially forming an oxide film and a first silicon nitride film on a silicon substrate; a step of etching the oxide film, the first silicon nitride film and the substrate in the intended field area to a predetermined depth to form a groove; A step of ion-implanting an impurity of the same conductivity type as that of the substrate into the substrate at the bottom of the trench, a step of forming a sidewall made of a second silicon nitride film on the side surface of the trench, and a step of ion-implanting an impurity of the same conductivity type as the substrate into the substrate at a predetermined depth within the trench. a step of forming a crystalline silicon film; a step of thermally oxidizing the entire surface of the substrate to change the polycrystalline silicon film into a field oxide film; a step of removing the first and second silicon nitride films; 1. A selective oxidation isolation method for a semiconductor device, comprising the step of filling in defects around an active region caused by removing a nitride film with an insulator.
JP30252186A 1986-12-17 1986-12-17 Selective oxidation isolating method Pending JPS63153840A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP30252186A JPS63153840A (en) 1986-12-17 1986-12-17 Selective oxidation isolating method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP30252186A JPS63153840A (en) 1986-12-17 1986-12-17 Selective oxidation isolating method

Publications (1)

Publication Number Publication Date
JPS63153840A true JPS63153840A (en) 1988-06-27

Family

ID=17909961

Family Applications (1)

Application Number Title Priority Date Filing Date
JP30252186A Pending JPS63153840A (en) 1986-12-17 1986-12-17 Selective oxidation isolating method

Country Status (1)

Country Link
JP (1) JPS63153840A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0964165A (en) * 1995-08-30 1997-03-07 Nec Corp Fabrication method of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0964165A (en) * 1995-08-30 1997-03-07 Nec Corp Fabrication method of semiconductor device

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