JPS63153797A - Writable read only memory - Google Patents

Abstract

PURPOSE:To reduce write time by turning on all transistors (TRs) provided to each bit line through the control of each signal line so as to attain simultaneous write to plural memory cells connected to one word line. CONSTITUTION:All transistors (TRs) QX0, QX1,... are turned on by controlling a signal line X of an EPROM and a prescribed voltage is applied, e.g., to a word line W0. Thus, simultaneous write is applied to plural memory cells Q00, Q01,... connected to the word line W0. In this case, since the load of the TRs QX0, QX1,... are each of memory cells Q00, Q01,... a power voltage with less voltage drop is applied to all bit lines B0, B1,... to attain stable write.

Description

[Detailed Description of the Invention] [Summary] In a writable read-only memory, a transistor that directly turns on and off power to the bit line of a memory cell array and whose control electrode is connected to a common signal line is connected to each bit line. By providing a word line, it is possible to simultaneously write to multiple memory cells connected to one word line.

[Industrial application field]

The present invention relates to a writable read-only memory configuration.

The above-mentioned memories include rewritable EPROM and FROM that can be written by the user, but it is desirable that the time required for writing be short.

[Conventional technology]

The case of EPROM will be explained below as an example.

FIG. 2 is a circuit diagram of a main part of a conventional example of an MO3 structure EPROM.

In the figure, A is a memory cell array, QOO.

qot, HHH+ QnO, Qnl+ ... are memory cells with MO3 type transistor structure, wo, wt,
....

Wn is a word line, BO, Bl, . . . are bit lines, QYO, QYL . . . are transistors that select bit lines, QO is a transistor that is turned on during writing, vpp is a power supply for writing, and QS is turned on during reading. This is a transistor that allows

For example, writing to the memory cell QOO is executed by turning on the transistor QD and the transistor QYO that selects the bit line BO, and applying a predetermined voltage to the word line WO. The same applies to writing to other memory cells.

At this time, the word line current is a charge-up amount to the gate capacitance of the memory cell and is very small, and the bit line current is the drain current of the memory cell and is small.
This is an IA order. Also, the time required for writing is ms
It is an order.

[Problem that the invention seeks to solve]

In EFROM, as one of the functional tests, writing is sometimes executed to all memory cells regardless of addresses.

In the EFROM having the above configuration, the memory cell array A
For example, if a memory cell containing 32 kilobits, or 32 kilograms, is stored in the memory cell, and it takes about 1 ms to write to a memory cell once, the time required to write to all memory cells is The test time is about 32 seconds, which is a long test time.

As a measure to reduce the time required to cause this problem, it is conceivable to write to a plurality of memory cells simultaneously by multiple selection of either word lines or bit lines.

However, when multiple word lines are selected,
Since the drains of the memory cells are commonly connected, the drain voltage is determined by the memory cell with the lowest breakdown voltage, making writing to other memory cells unstable, and when multiple bit lines are selected, the voltage of the transistor QD Increasing the drop limits the number of multiple selections, making it impractical in either case.

[Means for solving problems]

The above problem is solved by a writable read-only memory cell array having multiple word lines and multiple bit lines, and a control electrode that is provided for each bit line to directly turn on and off power to the bit line. The problem is solved by the writable one-domain memory of the present invention, which is capable of simultaneously writing to a plurality of memory cells connected to one word line, with transistors connected to a common signal line.

[Effect]

The above-mentioned simultaneous writing in this memory corresponds to the case of multiple selection of bit lines described above.

That is, by controlling the signal line to turn on all of the transistors provided for each bit line, a power supply voltage with a small voltage drop can be supplied to all of the bit lines.

From this, it is possible to stably perform simultaneous writing to the same number of memory cells as the number of transistors, and it becomes possible, for example, to shorten the test time, which was a problem earlier, in accordance with the number.

Note that since the above-mentioned transistor is provided for each bit line, turning off the transistor does not interfere with other functions of the memory.

〔Example〕

Embodiments of the present invention will be described below with reference to the main circuit diagram of FIG. The same reference numerals indicate the same objects throughout the figures.

The embodiment shown in FIG. 1 is similar to the conventional EPR shown in FIG.
: EPROM equivalent to IM.

That is, in the embodiment, the transistor Q×0°QXl is added to the conventional example.
, . . . and a signal line X are added,
The transistors QXO, QXI, . . . directly turn on and off the power supply Vpl) for each of the bit lines BO, BL, . has been done.

For example, it is possible to simultaneously write to a plurality of memory cells QOO, QOI, . . . connected to the word line WO. This is performed by controlling the signal line X to turn on all of the transistors QXO, QXI, . . . and applying a predetermined voltage to the word line WO. At this time, transistors QXO, QX
The load of I, ... is the memory cell QOO, QOI,
..., so the bit lines BO, Bl
, . . . all of the memory cells QOO, QOI are supplied with a power supply voltage with a small voltage drop.

Writing is performed stably for all of... This also applies to the memory cells connected to the other word lines WL...Wn.

Therefore, in this embodiment, the memory cell array A accommodates, for example, 32 kilobits, or 32 kilograms, of memory cells in a configuration of 64 per bit line, and it takes, for example, about 1 ms to write to a memory cell once. In this case, the time required to write to all memory cells is approximately 0.5 seconds, which is significantly shorter than approximately 32 seconds in the conventional example.

This greatly reduces the time required for a functional test in which writing is performed on all memory cells in an EPROM.

Note that since the transistors QXO, QXI, . . . are provided separately for each bit line BO, Bl, .

On the other hand, in this embodiment, transistors QO and Qvo,
Since QYI, . . . are provided, it is possible to write to any one of the memory cells in the same way as in the conventional example.

Therefore, by using the system of transistors QYO, QYI, . . . together with the system of transistors QXO, QXI, .

Although the above description has been made using an EPROM as an example, the present invention can also be applied to a PROM and provide convenience for user writing in the same manner as in the case of an EFROM.

〔Effect of the invention〕

As explained above, according to the configuration of the present invention, in a writable one-domain memory, it is possible to simultaneously write to a plurality of memory cells connected to one word line, thereby reducing the time required to write to the memory, For example, it has the effect of shortening the time required for EPROM functional testing and providing convenience for user writing.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a main part of an embodiment of the present invention, and FIG. 2 is a circuit diagram of a main part of a conventional example. In the figure, A is a memory cell array, QOO, QOI, ... are memory cells, WO, W!
, . . . are word lines, BO, BL, . . . are bit lines, QXO, QXI, . . . are transistors, X is a signal line, and vpp is a power supply for writing.

Claims (1)

[Claims] A writable read-only memory cell array having a plurality of word lines and a plurality of bit lines, and a control electrode provided for each bit line to directly turn on/off power to the bit line, and a control electrode connected to a common signal line. What is claimed is: 1. A writable read-only memory characterized in that it is equipped with connected transistors and can simultaneously write to a plurality of memory cells connected to one word line.