JPS6315334A - Parallel processor - Google Patents

Abstract

PURPOSE:To attain the reallocation of a processing to another processor possible to operate when a processor is placed under a state impossible to operate, by inputting information from a first and a second holding means, detecting the number of the processor to which the processing can be allocated, and performing the allocation of the processing to each processor. CONSTITUTION:The processing read out from a memory device by a reading means is allocated to and executed at each processor, and at this time, a detecting means sends the number of the processor in which no fault is found, and which is not operated at present, to an allocating means, based on the state of the processor held in the first and the second holding means. The allocating means allocates the processing sequentially based on the number of the processor. Also, when the second holding means in execution on the processor, is set at a state impossible to start up, the detecting means detects the number of the processor, and sends it to the allocating means. The allocating means performs the reallocation of the processing based on the number of the processor. In this way, it is possible to allocate the processing dynamically in the execution time of a program, and furthermore, to reallocate the processing when the fault, etc., is found in the processor.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a parallel processing device, and particularly to a parallel processing device suitable for a data processing device.

[Conventional technology]

There are many parts of a program that can execute multiple processes in parallel. In this case, if the processing of the parallel execution part is regular, such as the operation of array elements, Croy-1
By using the pipeline processing method adopted in vector processors such as , etc., it is possible to achieve efficient high-speed processing by sequentially processing a large number of regular operations at once.

However, there are many cases where the processing of the parallel execution part is not regular.1 For example, in device model calculations of circuit analysis programs, it is possible to execute ffX calculations for many transistors in parallel, but depending on the type of transistor etc. It becomes a rule.

In processing in such a case, the effect of the pipeline processing method cannot be obtained sufficiently, and it is difficult to increase the speed.

For this reason, parallel processing methods are being actively developed to obtain high arithmetic performance by breaking down parallel execution parts into a large number of processing units and having them simultaneously executed by a large number of processing devices.

At this time, a large number of processing units that can be executed in parallel are assigned to each processing device for processing, but in conventional devices, this assignment is specified in advance in the program. However, sufficient consideration was not given to dynamic allocation during execution.

[Problem that the invention seeks to solve]

The above-mentioned conventional technology does not take into account dynamic assignment of processing to each processing device at the time of execution, and has the following problems.

In general, parallel processing devices can have a wide range of configurations, ranging from tens to hundreds, or thousands to tens of thousands of processing devices. At this time, if the allocation of processing to each processing device is fixedly specified in the program, if the number of devices assumed at the time of program creation and the number of devices at the time of actual execution of the program do not match, the processing The program could not be executed due to an insufficient number of devices, or the program could not be executed because there were too many devices, so it was necessary to modify the program at the program level to match the number of devices at the time of actual execution.

Furthermore, when the number of processing devices becomes extremely large, the probability of a failure occurring increases, but it is possible to continue processing by reassigning the processing assigned to the failed processing device to another processing device. There was a problem that reliability was low because it could not be done.

An object of the present invention is to dynamically allocate processing to each processing device at the time of execution, and furthermore, it is an object of the present invention to dynamically allocate processing to each processing device at the time of execution. I? An object of the present invention is to provide a parallel processing device that can reallocate processing to a device capable of performing IJ operations.

[Means for solving problems]

The above purpose is to provide a reading means for reading information necessary for processing from a storage device based on instructions of a program; a second holding means that holds the state of whether or not the processing cannot be started due to a failure or the like; a third holding means that holds information necessary to execute the processing assigned to each processing device; a detection means for detecting the state of each processing device by inputting information from the second holding means, and each processing based on the state detection information from the detection means and the information necessary for the processing that is returned from the reading means. Allocates processing to the device, and also uses the state detection information from the detection means and the third
This is achieved by comprising an allocation means for reallocating processing to a processing device based on the information necessary for the processing from the holding means.

[Effect]

The processing read out from the storage device by the reading means is assigned to each processing device and executed. At this time, based on the state of the processing device held in the first and second holding means, the detection means is determined to be free of failure and operational. A processing device number that is not in the middle is sent to the allocating means. The allocation means sequentially allocates processing based on this processing device number, but at this time, the information necessary for processing is retrieved from the reading means and transferred to the processing device, and at the same time, the same information is transferred to the third holding device corresponding to the processing device number. and the corresponding first holding means is set to the operating state. Note that when the execution in the processing device is completed, the first holding means is set to a non-operating state, and if there is a failure or the like during execution, the corresponding second holding means is set to a non-startable state.

Furthermore, when the second holding means is set to a non-startable state during execution in the processing device, the detection means detects the processing device number and sends it to the allocation means.

The allocation means reallocates the processing based on this processing device number, and the information necessary for the processing at this time is taken out from the third holding device corresponding to the detected processing device number.

By controlling in this way, it is possible to dynamically allocate processing during program execution, and furthermore.

Processing can be reassigned due to a failure in a processing device or the like.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a schematic configuration diagram of an embodiment of the present invention. In the figure, 1 is the main memory, 2 is the storage side #2-1 to 7 is the port 3 for accessing the main memory 1, and 4 is the input/output processor. 5 is a host processor, 5 is a processor element (PE) control circuit, 5-1 is a brief fetch buffer, 5-2 is a microcomputer, 5-3 is a latch group that maintains the operating state of each PE, and 5-4 is a A group of latches for each PE that maintains the state of whether processing cannot be started due to a failure or the like, 5-5
is a group of registers that holds information about a certain processing unit (this is called a block and each block can be executed in parallel) allocated to each PE, and 5-6 are registers for each PE. Circuit for searching operating status, 5-
7 is a circuit that searches for an unstartable state, and 6 to 9 are numbers O to
3 PE, 6-1 to 9-1 are local storage, 6-2 to 9
-2 is a processing unit (PU), Q1 to Ω9. f
llo-1-D~3.1210-2. Q10-3-0
~3.1210-4-0~3 are signal lines. Although FIG. 1 shows a configuration in which the number of processor elements is four, in general, there is no limit to four processor elements, and any number of processor elements may be used as long as it is within the practical range.

Next, the general operation will be explained based on the schematic configuration diagram of FIG. 1, but the explanation will be made assuming a simple processing example as shown in FIG. Main memory 1
100-1 to n are the n blocks consisting of input/output data, address list, and program, and 100-1-1 to 100-n-1 are the inputs corresponding to each block. Output data, 100-1-2 to 100
- n -2 is an address list and program corresponding to each block, 101-1 to n are MS (main memory 1) read start address, LS (local memory 6-1 to 9-1)
Block information corresponding to each block consists of a size indicating the amount of data to be transferred from the write start address MS to LS, 102 is the start address where block information 101-1 to n is stored, 103 is the block to be processed number (in this case n).

Here, the address list I~ is a list that specifies the addresses of input/output data to be referenced in the program of the corresponding block. For example, if a FORTRAN subroutine corresponds to a block, the data specified by the subroutine argument corresponds to the above input/output data, and the address information when accessing this input/output data is in the above address list. Equivalent to.

In addition, the address list and program corresponding to each block are transferred from the main memory to the local memory of one assigned PE, but at this time, the MS read start address is the address list of the corresponding block stored in the main memory. and specifies the start address of the program, and the LS write address specifies the start address stored in local storage. In this case, it is assumed that the address list and the program are stored consecutively in the main memory.

The host processor 4 transfers the number of blocks to be processed 103 and the start address 102 to the PE control circuit 5 and instructs it to start processing.Then, the PE control circuit 5 transfers the block information 101-1 to n from the main memory 1 based on the start address 102. are sequentially read out and sequentially transferred from the block information 101-1 to fixed addresses in the local storage of each PE, and an activation start signal is sent. Each PE that receives the start ljJ start signal performs the following processing based on the block information set in the fixed address of the local storage. That is, the corresponding address list and program are read from the address in the main memory specified by the MS read start address in the block information, and written to the address in the local memory specified by the LS write start address in the block information. It's crowded. It is assumed that the amount of address list and program to be read from the main memory is specified by the size in the plot information.

Processing is then started according to the program read out to the local memory, but at that time, when accessing the corresponding input/output data in the main memory, it is done using the information in the address list read out from the main memory earlier. . Note that intermediate result data obtained during program execution may be stored in local storage, but in such a case, it is necessary to support instructions that access main storage and local storage separately. When the processing is completed, the PE sends an end signal to the PE control circuit 5. And P.E.
If there is an unprocessed block, the control circuit 5 transfers the block information of the new block to the PE and sends out a start signal.

When processing of all blocks specified by the number of blocks to be processed 103 is completed in this manner, the PE control circuit 5 sends an end signal to the host processor and ends the operation.

Here, the processing of each block is assigned to each PE, and control regarding this assignment is a feature of the present invention.
Operating state holding latch group 5-3, activation disabled state holding latch group 5-4, block information holding register group 5-5. This is performed using the operating state search circuit 5-6 and the inactivation state search circuit 5-7. In the above, the embodiment will be described in detail with reference to FIGS. 2 to 5, focusing on control of allocation of each block process to PE.

Figure 2 shows the processor element (P E
) This is an example of the configuration of the control circuit 5. In the figure, 5-1 is a brief fetch buffer, 5-2 is a microprocessor, and 5-3-
0 to 5-3-3 are operating state holding latches corresponding to processor element (PE) numbers O to 3, respectively, and 5-4-0 to
3 is a bootable state holding latch corresponding to PE numbers 0 to 3, respectively; 5-5-0 to 3 are block information holding registers corresponding to PE numbers O to 3, respectively; 5-6 is an operation state search circuit; 5- 7 is a startup failure state search circuit, 5-10.5-
14.5-20.5-23 to 26,5-27.5-29
~32 is selector, 5-11°5-13.5-15-1
~2.5-18.5-33 is a register, and 5-12 is a count up circuit.

5-17 is a countdown circuit, 5-16 is a zero detection circuit, 5-19. 5-21 to 22. 5-27 to 28 are decoders, A4-1 to 4. f15-1~2゜Q10-1
-0~3. Q10-2. fllO-3-0~3. A1
0-4-0~3. A50-1~4゜A50-5-1~2
．． A50-6 to A50-19 are signal lines. FIG. 3 is a control flow diagram showing the main operations of the PE control circuit 5 shown in FIG. Further, FIGS. 4 and 5 respectively show the operating state search circuit 5-6 shown in FIG. This is an example of the configuration of a startup failure state search circuit 5-7. In addition, in Figure 4, 5-3
-〇~3 are operating state holding latches corresponding to PE numbers 0~3 (shown in Figure 2), 5-4-0~3 are P
The unstartable state holding latch (second
(Illustrated in the figure) 5-34 to 35° 5-45 is an OR circuit, 5-
36-39.5-44°5-46-47. is an AND circuit, 5-40~43°5-48~53 is an NO7 circuit,
A50-5-1 to 2.150-12 are signal lines.

Also, in Figure 5, 5-3-0~3 and 5-4-0~3
is the same as in Figure 4, and 5-50.5-52 to 56.5
-60 to 61 are AND circuits, 5-51.5-59 are OR circuits
Circuit, 5-57 to 58, 5-62 are NOT circuits, A5
0-7~8. A50-13 is a signal line.

When a command specifying the processing shown in FIG. 6 is input from the host processor 4 to the PE control circuit 5 via the signal line 24-4, it is decoded by the decoder 5-19 and sent to the signal line Q50- 15 to the microcomputer 5-2.

Then, the microcomputer 5-2 reads PEliJ No. 0.
.about.3 are all unstartable, based on the signal line Q50-7 output from the unstartable state search circuit 5-7. As shown in FIG. 5, the signal aQ50-7 indicates that all start-up disabled state holding latches 5-4-0 to 3 are ON.
It turns ON when , that is, when all PEs are in a non-startable state.

Therefore, when the signal line fi50-7 is ON, all PEs are in a non-startable state and cannot execute instructions from the host processor 4. For this reason, the microcomputer 5-2
reports the inability to process to the host processor 4 via the signal line Q4-3 and ends.

On the other hand, when signal line Q50-7 is OFF, signal line Q4
-3, the host processor 4 reports that processing is possible through the signal lines Q4-1. selector 5
-14, the number of processing blocks is 103 (see Figure 6)
to the register 5-15-2, and the signal mΩ4-1. The start address 102 (see FIG. 6) is set in the register 5-11 via the selector 5-10. After that, based on the start address set in the register 5-11, the read address to the main memory 1 is sent to the port 2-3 via the signal line Q5-1 while updating the address sequentially in the count-up circuit 5-12. , reads the block information (101-1 to 101-n shown in FIG. 6) from the main memory 1, and connects the signal line Q5-
2 and sequentially stored in the brief fetch buffer 5-1. In parallel with the reading of the block information, the microcomputer 5-2 performs control according to the control flow shown in FIG. 3.The operation will be described in detail below according to FIG.

First, at 5100, a check is made to see if each PE has been activated for all blocks. This is register 5-15-
The countdown circuit 5-17 counts down the number of processing blocks initially set to 2 every time one block is activated, and when the value reaches 0, the zero detection circuit 5-1
When the signal line Q50-1 output from 6 is turned ON, it is recognized that the activation of all blocks has been completed.

(1) When activation of all blocks has not been completed In the case of Koni, first check whether there is an inactive PE in 5 lots. If there is no non-operating PE, activation of a new block is waited until a non-operating PE appears, but during this time, it is checked in 5104 whether all PEs are in the activation-incapable state (recognized by signal line Q 50-7). )do. If all PEs are unable to start, the microcomputer 5-2 reports abnormal termination to the host processor 4 via the signal line Q4-2, and interrupts the process being executed.

Note that when each PE detects an inoperable factor such as a machine check while processing a block, it connects signal lines QIO-4-0 to QIO-3.
(Corresponding to PE numbers O to 3).

It is assumed that the corresponding activation disabled state holding latches 5-4-0 to 3 are turned on via the selectors 5-29 to 31.

Next, we will describe the processing procedure when there is an inactive PE.
Here, whether or not there is an inactive PE is recognized as follows.

That is, if both the operating state holding latch and the activation disabled state holding latch corresponding to the operating state holding latch are OFF, it is assumed that there is an inactive PE. Note that the operating state holding latch is activated to the corresponding PE (the activation signal is sent and turned ON via signal lines 210-1-0 to 210-3, and the processing in the PE is completed (signal line Q1-3). −〇〜
3), it will turn OFF. Specifically, information as to whether there is an inactive PE is transferred to the microcomputer 5-2 via the signal line Q50-5-1 based on the operating state search circuit 5-6 shown in FIG. be recognized.

If there is an inactive PE, first 510 shown in FIG.
If the block information required for the brief fetch buffer 5-1 has been read out from the main memory 1 in advance in step 2, then the process in step 5103 is performed. If it has not been read in advance, wait until it is read and perform the process of 8103.

Next, the processing procedure at 5103 will be described. First, the encoded information of the non-operating PE number (if there are multiple non-operating PEs, one is selected from them) output from the operating state search circuit 5-6 via the signal mΩ50-12 is decoded. Enter in 5-21. Here, the encoded information is created with 2 bits as shown in bit 0 and bit 1 of the signal line Q50-12 in FIG. 4, and bit 0=0. When bit 1 = O, PE number O' =
O,' = 1' PE number 1' = 1. '
=O' PE number 2' =1. '＝
1' PE number 3 shall be specified. Then, when the microcomputer 5-2 sends an enable signal to the selector 5-21 via the signal l1IQ50-3.

The aforementioned encoded information is decoded and the signal line Q10-1-
Any one of 0 to 3 turns ON and a start signal is sent to the corresponding PE. At the same time, the operating state holding latch 5-3
The corresponding latch among -0 to 3 is turned on to be in an operating state.

In parallel, block information is read from the brief fetch buffer 5-1, and the signal line Q50-10° selector 5-20.
Block information is sent to each PE via the signal line Q10-2. At this time, at the same time, the block information is set in the corresponding register among the block information holding registers 5-5-0 to 5-3. Thereafter, the process returns to 5100 and the processing procedure when all blocks have not been activated ends.

(2) When activation of all blocks is completed: In this case, first, it is checked in 8106 whether there is any PE in operation. This is recognized by the microprocessor 5-2 based on information transferred from the operating state search circuit 5-6 via the signal line 1250-5-2.

At this time, the signal line Q50-5-2 is turned ON if any one of the operating state holding latches 5-3-0 to 3 is ON as shown in FIG. P of
Shows that E exists.

If there is no PE in operation, the microprocessor 5-2 recognizes that the processing of all blocks has been completed normally, and connects the signal line Q.
A normal completion report is sent to the host processor 4 via 4-2.

If there are any PEs in operation, it is checked in step 5107 whether all PEs are in an unstartable state. If all PEs are in an unstartable state, the above-mentioned slog process is performed, and if all PEs are not in an unstartable state, the process of 8108 is performed.
8, an inoperable factor such as a machine check occurs in the PE after the PE starts, and the corresponding inoperable state holding latch is turned ON.
Check whether it is.

Specifically, as shown in FIG. 5, the unstartable state holding latches (5-4-0 to 3) are ON, and the corresponding operating state holding latches (5-3-0 to 3) are ON. If any PE is ON, the signal mu50-8 is turned ON, and the microprocessor 5-2 is notified that an unstartable PE has occurred during execution.

If an unstartable PE has not occurred during execution, the process returns to 5106, and if it has occurred, performs the process of 5109, 510
At step 9, in the same manner as the process at step 8101 described above, it is checked whether there is an inactive PE.

If there is no non-operating PE, the system waits until a non-operating PE appears, but during this time it is checked whether all PEs are in a non-startable state, and if all PEs are in a non-startable state, the above-mentioned process is performed. Processing in step 3105 is performed and the process ends abnormally.

On the other hand, if there is a non-operating PE, 5 LIO.

After processing 5112, the process returns to 3106. first.

In 5Lio, the operating state holding latch corresponding to the unstartable PE that occurs during execution is turned OFF.

Specifically, the encoded information of the unstartable PE number (select one from among them if there is more than one) that occurred during execution is output from the unstartable state search circuit 5-7 via the signal line A30-13. , set in register 5-33.

The encoding method is the same as that for the inactive PE number described above, and please refer to FIG. 5 for the specific logical configuration.

Then, the encoded information of the PE number set in the register 5-33 is sent to the decoder 5-3 via the signal line Q50-14.
22. And microcomputer 5-2
sends an enable signal to the decoder 5-22 via the signal line fi50-4, the encoded information is decoded6, and the decoded information is transmitted via the selectors 5-23 to 5-26 to reset the operating state holding latch of the corresponding PE. It is input to the terminal and turned OFF.

Subsequently, the process of 5112 is performed.

The basic operation is the same as that of 5103 described above, but the following points are different. That is, in 5103, block information was extracted from the brief fetch buffer 5-1, but in 511
2, based on the encoded information of the PE number set in the register 5-33, the block information holding register 5-5-
Selector 5-2 selects the corresponding block information from 〇 to 3.
The difference is that it is taken out via 7.

This concludes the explanation of the operation based on one embodiment of the present invention.
Although the above description is an operation description based on the processing example shown in FIG. 6, it is generally not necessary to be limited to the processing example shown in FIG.

For example, in Figure 6, the processing program for each block is read from the main memory to the local memory separately by the PE for each block, but if it is common to each block, it may be a good idea to broadcast it in advance. It will be done. Moreover, the same thing can be considered for input data if there is common data.

Furthermore, instead of reading the necessary data from the main memory as needed during the program execution in each PE, the necessary data is read in advance from the main memory to the local memory in advance before the program starts. Another possible method is to avoid accessing the main memory as much as possible while the program is running. Further, in FIG. 6, the host processor 4 instructs the processor element IIJ control circuit 5 to process a plurality of blocks at once, but a method of instructing each block separately is also conceivable.

For example, the process for broadcasting common data is performed as follows.

When a command specifying broadcast is input from the host processor 4 to the PE control circuit 5 via the signal line Q4-4, it is decoded by the decoder 5-19, and the signal mD,
The information is transmitted to the microcomputer via 50-16. At the same time, the host processor 4 connects the signal line Q
4-1, the start address of the main memory to be read is sent to register 5-11, and the data size to be transferred is sent to register 5-11.
-15-2, and sets the start address to be written to the local memory in register 5-15-1.

Here, it is assumed that the addressing of the data to be transferred is continuous in both the main memory and the local memory.

Thereafter, the start address set in the register 5-15-1 is transferred to the signal line 150-9° selector 5-20. Transfer to all PEs via signal line QIO-2. Subsequently, while counting up the start address set in the register 5-11 by the count-up circuit 5-12, data is sequentially read from the main memory to the prefetch buffer 5-1.
Extract data by the data size set in register 5-15-2 and send signal 171tQ50-10° selector 5
-20, transfer to all PEs via signal line filo-2 and write in local storage.

In addition, in FIG. 2, decoder 5-27 and decoder 5-
28 sets the unstartable state holding latches 5-4-0 to 3 to 0N10 based on the command transferred from the host processor 4.
This is used when performing FF. Incidentally, if the host processor 4 needs to know the status of the non-startable state latches 5-4-0 to 3, a function for that purpose can be easily added. The same thing can be said.

FIG. 7 is a block diagram of another embodiment of the present invention.

FIG. 7 shows a configuration in which a vector processing device is incorporated in the configuration shown in FIG. 6, where 10 is a vector processing device, 2-8 is a boat for the vector processing device to access the main memory 1, and 111 is a vector processing bag! ! Q12 is a signal line for transferring addresses, read data/write data, etc. between the vector processing device 10 and the host processor 4, and a signal line Q12 is used to transfer control information (for example, the host processor 4
This is a signal line for transmitting a start signal for instructing the vector processing device 10 to start processing, a vector processing signal (a processing end signal from 10 to the host processor 4, etc.), and the rest is the same as in FIG. . Note that the vector processing device 1
0, a vector processing device such as Cray 1+HITAC3-810 can be considered.

When executing a program, processing suitable for parallel processing is performed in parallel by processor element numbers O to 3 under the control of the processor element control circuit 5, while processing suitable for vector processing (pipeline processing) is performed in parallel using processor element numbers O to 3. By processing with the processing device 10, high speed and high efficiency can be realized.

Note that in FIG. 7, the vector processing device 10 is a relatively large-scale processing device that employs an advanced pipeline system, while processor element numbers O to 3 are relatively small-scale processing devices. be. Further, the number of processor elements does not need to be limited to four; in fact, it may consist of several tens to hundreds of processor elements, and it is also conceivable that the vector processing device may also be composed of a plurality of units.

〔Effect of the invention〕

According to the present invention, since processing can be dynamically assigned to each processing device at the time of execution, the user does not need to be aware of the number of processing devices and the number of the processing device, and
If a processing device becomes inoperable due to a failure or the like during operation, processing can be reassigned to another operational processing device, which has the effect of providing a parallel processing device that can improve reliability. , incorporates a vector processing unit.

By executing processes suitable for vector processing on a vector processing device, and executing processes suitable for parallel processing on a parallel processing device, it is possible to distribute the load according to the content of the processing, achieving higher speed and efficiency. There is an effect that it can be done.

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram of an embodiment of the present invention, and FIG.
An example of the configuration of the processor element control circuit shown in the figure,
FIG. 3 is a control flow for explaining the operation of an embodiment of the present invention, and FIGS. 4 and 5 are configuration examples of the operating state search circuit and the inactivation state search circuit shown in FIG. 2, respectively. ,
FIG. 6 is a processing example for explaining the operation of one embodiment of the present invention, and FIG. 7 is a diagram showing a configuration diagram of another embodiment of the present invention.

Claims (1)

[Claims] 1. Consisting of a plurality of processing devices, a control device that controls the processing devices, and a storage device shared by the processing devices and the control device, each processing device has a different in a parallel processing device capable of executing a plurality of processes in parallel;
a second holding means for holding a state as to whether or not each processing device is unable to start processing due to a failure or the like, and inputting information from the first holding means and the second holding means to allocate processing. The parallel processing apparatus is characterized by having a detecting means for detecting possible processing apparatus numbers, and an assigning means for allocating processing to each of the processing apparatuses in response to information output from the detecting means. 2. In the parallel processing device of item 1, there is also a third parallel processing device that holds information necessary to execute the processing assigned to each processing device.
, the detecting means is capable of detecting a processing device number that becomes inoperable during execution of processing, and the assigning means is capable of detecting a processing device number that becomes inoperable during execution of processing. , a parallel processing device capable of reassigning processes by extracting information necessary to execute a process from a corresponding third holding means.