JP4743414B2 - Information processing system, information processing method, and program - Google Patents

Description

  The present invention relates to an information processing system including a plurality of input / output processing devices serving as communication units with external devices, an information processing method for input / output setting, and a program to be executed by a computer.

  An information processing system such as a mainframe that requires higher performance than a normal computer is an input / output processing device (hereinafter referred to as IOP) serving as a communication unit with a peripheral processing device such as a disk array. A plurality of logical cards for controlling the IOP are provided. Each IOP includes a plurality of slots for connecting peripheral processing devices. Before the information processing system is turned on or reset, peripheral processing devices connected to the slots are set in units of IOPs. Then, the logical card and the IOP are paired to perform information processing related to input / output with the peripheral processing device connected to the IOP.

A technique is disclosed in which some slots can be shared by a plurality of logical partitions (see Patent Document 1).
JP 2005-122640 A

  In the information processing system described above, if a connection with a peripheral processing device is set in units of IOPs, the magnitude of the load may be extremely different between IOPs due to differences in the peripheral processing devices. In this case, there is a problem that even if the load of input / output processing is increased for some IOPs, the load cannot be averaged over the entire information processing system. In the method disclosed in Patent Document 1, the load applied to some slots is merely distributed in a time division manner to a plurality of logical partitions.

  The present invention has been made to solve the above-described problems of the prior art, and is implemented in an information processing system, an information processing method, and a computer that can be divided into logically different partitions in units of slots. The purpose of this is to provide a program.

In order to achieve the above object, an information processing system of the present invention comprises:
An IOP management table in which information of the slot is described for each logical IOP that is a unit of a group divided for a plurality of slots for connection to a peripheral processing device, and the logical IOP for each partition that is a unit of input / output processing. A memory that stores a logical IOP configuration table indicating whether or not it is included as a configuration, and a diagnostic processing device that includes a processing unit that externally instructs the incorporation of the logical IOP when an initialization instruction is input ,
When receiving the incorporation instruction from the plurality of slots, the memory for storing the information of the logical IOP, and the diagnostic processing device, the IOP management table and the logical IOP configuration table are referred to, A plurality of input / output processing devices including a processing unit for storing information on a partition of a logical IOP belonging to a slot in the memory;
It is the structure which has.

  In the present invention, in each input / output processing device, the logical IOP of each slot handled by the own device is specified by the IOP management table, and the partition to which the logical IOP belongs is registered. For this reason, the entire slots provided in the plurality of input / output processing devices can be configured to belong to different sections in slot units.

On the other hand, an information processing method of the present invention for achieving the above object includes a plurality of input / output processing devices having a plurality of slots for connecting to an external peripheral processing device, and the input / output processing devices. An information processing method for input / output setting of an information processing system having a diagnostic processing device for instructing setting,
The diagnostic processing device includes an IOP management table in which information of the slot is described for each logical IOP that is a unit of a group divided for the plurality of slots, and the logical IOP for each partition that is a unit of input / output processing. Storing in a memory a logical IOP configuration table indicating whether it is included as a configuration;
The diagnostic processing device, when an initialization instruction is input, instructing the plurality of input / output processing devices to incorporate the logical IOP;
When each of the plurality of input / output processing devices receives the instruction for incorporation from the diagnostic processing device, the I / O processing device refers to the IOP management table and the logical IOP configuration table, and partitions the logical IOP belonging to each slot of the own device. Storing information of
It is what has.

In addition, a program of the present invention for achieving the above object is a program for causing a computer having a plurality of input / output processing devices provided with a plurality of slots to be connected to an external peripheral processing device. ,
An IOP management table in which information of the slot is described for each logical IOP that is a unit of a group divided for the plurality of slots, and whether or not the logical IOP is included in each partition that is a unit of input / output processing. Storing a logical IOP configuration table indicating whether or not in a memory;
When an initialization instruction is input, each of the plurality of input / output processing devices is referred to the IOP management table and the logical IOP configuration table, and the logical IOP belonging to each slot is determined for each input / output processing device. Storing parcel information; and
The computer is caused to execute a process having

  According to the present invention, an input / output processing device that is physically regarded as a single unit can be divided into a plurality of logical input / output processing devices, and an input / output operation can be performed corresponding to each information processing device.

  The information processing system of the present invention is configured to be able to belong to a partition for each logical IOP that is a unit obtained by dividing a plurality of slots, and is provided with a table for managing information on the partition corresponding to each logical IOP. It is characterized by that.

  The configuration of the information processing system of this embodiment will be described. FIG. 1 is a block diagram illustrating a configuration example of an information processing system according to the present embodiment.

  As shown in FIG. 1, the information processing system of this embodiment includes one diagnostic processing device (hereinafter abbreviated as DGP) 1000, a plurality of logical cards 2000 to 2007, and a plurality of input / output processing devices ( In the following, it is 3000-3007 (abbreviated as IOP). The DGP 1000, the logical cards 2000 to 2007, and the IOP 3000 to 3007 are connected to each other via a bus 4000 so that they can communicate with each other. In this embodiment, eight logical cards and IOPs are used, but the number is not limited to this.

  The eight IOPs IOP0 to IOP7 are individually expressed as IOPm. Here, m is a different number for each logical card, and is an integer from 0 to 7. Here, m is the identifier of the IOP. As shown in FIG. 1, reference numerals 3000 to 3007 are associated with IOPs 0 to 7. Hereinafter, IOP0 to 7 are referred to as IOP3000 to 3007. And IOP 3000 to 3007 is expressed as IOP 300m. Further, the logical card is represented as CELL in FIG.

  FIG. 2 is a block diagram showing a configuration example of a logical card. On the logical cards 2000 to 2007, four arithmetic processing units (hereinafter abbreviated as EPU) 1x0 to 1x3 and a memory 20x are mounted for each logical card. The symbol x is a number different for each logical card, and is an integer from 0 to 7. FIG. 2 shows the case where x is 0 and 1. Below, EPU1x0-1x3 is described as EPU1xy. However, y is a different number for each EPU mounted on one logical card, and is an integer from 0 to 3.

  The EPU 1xy and the memory 20x mounted on each of the logical cards 2000 to 2007 are also connected to the bus 4000, and can be mutually accessed among the EPU 1xy, the memory 20x, and the IOP 300m. In addition, a plurality of peripheral processing devices such as a magnetic disk device are connected to a plurality of IOPs 3000 to 3007. In FIG. 1, a plurality of peripheral processing devices are denoted by reference numerals 5000 to 500w. w is a different number for each peripheral processing apparatus, and is an integer of 0 or more.

  One IOP 300m can connect a plurality of peripheral processing devices 500w. Each IOP 300m is provided with a plurality of slots (SLOT) for connecting the peripheral processing device 500w. In this embodiment, eight SLOTs are connected to each IOP 300m. Further, as shown in FIG. 1, one peripheral processing device 500w may be connected to a plurality of IOPs 300m. Data can be transferred between the memory 20x and the peripheral processing device 500w via the IOP 300m.

  It is necessary to perform information processing with a plurality of peripheral processing devices connected to the slot more efficiently. Therefore, in this embodiment, it is possible to divide a plurality of slots of a plurality of EPU1xy and IOP300m included in a plurality of logical cards into groups by a method described later. This division is not limited to an IOP unit, and may be performed over a plurality of IOPs. This divided group is referred to as a “section”. By executing software for each partition, each functions as an information processing apparatus.

  Hereinafter, a virtual storage area provided in each partition is referred to as a “logical memory space”. Further, a plurality of slots of the IOP 300m are grouped, and one unit is referred to as a “logical IOP”. In this embodiment, it is possible to move between partitions in units of logical IOPs by a method described later. The initial settings of these partitions and logical IOPs are input from outside and registered.

  Next, the configuration of DGP will be described. FIG. 3 is a block diagram showing a configuration example of DGP. The DGP 1000 is a device that controls the EPU 1xy, the memory 20x, and the IOP 300m. As illustrated in FIG. 3, the DGP 1000 includes a processing unit 1100 that performs various types of information processing, firmware 1200 for controlling the processing unit 1100, and a local memory 1300. The processing unit 1100 includes a CPU (Central Processing Unit) that executes processing according to a program, and a memory for temporarily storing the program. Firmware 1200 and local memory 1300 are connected to processing unit 1100. The local memory 1300 is controlled by the processing unit 1100 executing the firmware 1200.

  Next, information stored in the local memory 1300 will be described. The local memory 1300 stores an IOP management table 1310, an address management table array 1320, and a logical IOP configuration table array 1330. Each table will be described below.

  FIG. 4 is a diagram for explaining the IOP management table. In the IOP management table 1310, two entries are stored for each SLOP of each IOP. One is a logical IOP number indicating to which logical IOP each slot of the IOP 300m is defined. The logical IOP number is an identifier of the logical IOP. In FIG. 4, SLOTz (where z is an integer from 0 to 7) of IOP300m is represented as IOPm / SLOTz. The logical IOP number is represented as logical IOP (LIOP) #. # Is different for each logical IOP. The other is the CH number of the logical IOP corresponding to the SLOT. The CH number is represented as CH #. This CH number is an identifier of the peripheral processing device. The IOP management table 1310 indicates the relationship of components involved in information processing, and is information registered by the DGP 1000 and stored without being erased even when the power is turned off.

  FIG. 5 is a diagram for explaining an address management table array. The address management table array 1320 is for managing a logical memory space for each partition. As shown in FIG. 5, the address management table array 1320 is an array having an address management table 132p for each partition. p is a partition number. The address management table 132p is shown in FIG. The address management table 132p is a table indicating the MU number corresponding to each address number of the logical memory space of each partition. The address number is a number obtained by dividing an address in the logical memory space (hereinafter referred to as “logical address”) by a fixed length (here, 256 MB), and the logical address is divided by a fixed length. Value. The address management table array 1320 and the address management table 132p indicate the relationship of components involved in information processing, and are information registered by the DGP 1000 and stored without being erased even when the power is turned off.

  FIG. 7 is a table showing a logical IOP configuration table array. The logical IOP configuration table array 1330 is for managing the logical IOP for each partition. The logical IOP configuration table array 1330 is an array having the logical IOP configuration table 133p of each partition as shown in FIG. 7, and the logical IOP configuration table 133p is as shown in FIG. The logical IOP configuration table 133p is a table indicating which logical IOP is configured in the logical partition, and has an entry for each logical IOP. Each entry stores an identifier indicating in which partition the logical IOP is configured. In this embodiment, the identifier is “configuration” and “unconfigured” information. To the entry. If “configuration” is stored, it indicates that the logical IOP is configured in the partition, and if “not configured” is stored, it indicates that the logical IOP is not configured in the partition. The logical IOP configuration table array 1330 and the logical IOP configuration table 133p indicate the relationship of configurations involved in information processing, and are information registered by the DGP 1000 and stored without being erased even when the power is turned off.

  Next, the firmware 1200 will be described in detail. The firmware 1200 includes an initialization unit that initializes the information processing system when the information processing system starts up, a partition initialization unit that initializes each partition, a built-in unit that incorporates the specified logical IOP, and a designation A program for executing a detaching unit that detaches the specified logical IOP and a partition moving unit that moves the specified logical IOP to the specified partition is stored. The processing unit 1100 executes a program corresponding to each means. Details of each means will be described later.

  Next, the configuration of the EPU will be described. FIG. 9 is a block diagram illustrating a configuration example of the EPU.

  The EPU1xy performs a predetermined process according to an instruction from the software. As illustrated in FIG. 9, the EPU 1xy includes a processing unit 1xy-1 that performs various types of information processing, firmware 1xy-2 for controlling the processing unit 1xy-1, and a local memory 1xy-3. The processing unit 1xy-1 includes a CPU (not shown) that executes predetermined processing according to a program, and a memory (not shown) for temporarily storing the program. Firmware 1xy-2 and local memory 1xy-3 are connected to processing unit 1xy-1. The local memory 1xy-3 is controlled by the processing unit 1xy-1 executing the firmware 1xy-2.

  The firmware 1xy-2 stores programs for executing the following various means according to instructions from the software. The means includes a built-in means for incorporating the designated logical IOP, a detaching means for separating the designated logical IOP, and data transfer between the memory 20x and the peripheral processing device 500w to the designated logical IOP. Input / output instructing means, partition moving means for moving a specified logical IOP to a specified partition, and configuration information acquisition means for returning a logical IOP configuration table to software.

  Next, the configuration of the IOP will be described. FIG. 10 is a block diagram illustrating a configuration example of the IOP.

  The IOP 300m performs data transfer between the memory 20x and the peripheral processing device 500w according to an instruction from the EPU 1xy. As shown in FIG. 10, the IOP 300m includes a processing unit 3m0 that performs various types of information processing, firmware 3m1 for controlling the processing unit 3m0, a local memory 3m2, and a SLOT 3m4-0-7 for connecting a peripheral device 500w. And have. The firmware 3m1, the local memory 3m2, and the SLOT 3m4-0 to 7 are connected to the processing unit 3m0, and each unit is controlled by the processing unit 3m0 executing the firmware 3m1.

  In the firmware 3m1, data is transferred between the memory 20x and the peripheral processing device 5000w according to an instruction from the EPU1xy, an embedding unit that incorporates a logical IOP according to an instruction from the DGP 1000, a disconnecting unit that disconnects a logical IOP according to an instruction from the DGP 1000 And input / output instruction means for enabling the storage. The processing unit 3m0 executes a program corresponding to each means. Details of each means will be described later.

  The processing unit 3m0 includes a CPU (not shown) that executes a program of the firmware 3m1 and a memory (not shown) for temporarily storing the program. The memory of the processing unit 3m0 is provided with four interrupt units 3m0-0 to 3, which are areas for storing interrupt information corresponding to the logical IOP. When a logical IOP is specified by DGP1000 or EPU1xy, information on the specified logical IOP is input to the processing unit 3m0. Then, when interrupt information enters any one of the interrupt units 3m0-0 to 3 corresponding to the specified logical IOP, the processing unit 3m0 selects which interrupt unit among the interrupt units 3m0-0 to 3. It is possible to recognize whether there is an interrupt notification and specify the specified logical IOP. Thus, when the processing unit 3m0 executes the firmware 3m1, processing for the corresponding logical IOP is performed. Since each of the interrupt units 3m0-0 to 3 corresponds to each of the logical IOPm0 to logical IOPm3, the interrupt unit 3m0-n corresponds to the logical IOPmn. However, n is an integer of 0-3.

  The local memory 3m2 has four areas 3m2-0 to 3 corresponding to the logical IOP. Since each of the areas 3m2-0 to 3m corresponds to each of the logical IOPm0 to logical IOPm3, the area 3m2-n corresponds to the logical IOPmn. The area 3m2-n includes a CH slot management table 3m2-n0, an address management table 3m2-n1, and a flag 3m2-n2. The CH slot management table 3m2-n0, the address management table 3m2-n1, and the flag 3m2-n2 will be described below.

  FIG. 11 is a diagram for explaining the CH slot management table. The CH slot management table 3m2-n0 indicates the SLOT number of the IOP corresponding to the CH number of the logical IOP, and has an entry for each CH number of the logical IOP. In this entry, when the SLOT corresponding to the CH number exists, the SLOT number is stored, and when the corresponding SLOT does not exist, an identifier indicating that it does not exist is stored.

  FIG. 12 shows an address management table. The address management table 3m2-n1 shows the configuration of the logical memory space of the partition corresponding to the logical IOP, and is the same as the address management table 132p of the DGP 1000.

  FIG. 13 is a diagram for explaining the flag. Area 3m2-n is used to store flag 3m2-n2. This flag 3m2-n2 is an entry indicating whether or not the corresponding logical IOP is incorporated. If the corresponding logical IOP is incorporated, an identifier indicating the incorporation is stored in the area 3m2-n. On the other hand, if the corresponding logical IOP is not incorporated, an identifier indicating separation is stored in the area 3m2-n. The identifier indicating separation is the same as that cleared.

  As described above, the IOP 300m of this embodiment can divide the subordinate SLOTs 3m4-0 to 7 into a plurality of logical IOPs, and each logical IOP can be configured in different partitions. How to divide the IOP 300m into logical IOPs is determined by the IOP management table 1310 shown in FIG. The IOP management table 1310 can store logical IOP numbers corresponding to SLOTs 3m4-0 to 7 of IOP300m. The IOP 300m has the ability to divide into up to four logical IOPs according to the number of EPUs on the logical card. The IOP number that is the identifier of the IOP and the logical IOP number that is the identifier of the logical IOP have the following rules. When the IOP number is IOPm, the corresponding logical IOP number is the logical IOPmn. This is recognized by all of DGP1000, EPU1xy, and IOP300m.

  In addition, the information processing system according to the present embodiment divides the EPU 1xy, the memory 20x, and the slots 3m4-0 to 7 of the input / output processing device 300m into logically different partitions, and performs information processing for each partition. It can be operated as a device. A specific example will be described below.

  FIG. 14 is a block diagram illustrating an example of partition division. Here, only two logical cards 2000 and 2001 are shown. As shown in FIG. 14, the information processing configuration is logically divided into two partitions, a partition 1 and a partition 2. The partition 1 includes EPUs 100, 102, and 103, a memory 200, and SLOTs 304-0 to 3 of the IOP 3000. Partition 2 includes EPUs 101, 104, 105, 106, 107, a memory 201, IOP 3000 SLOTs 304-4 to 7, and IOP 3001 slots 314-0 to 7. Different software can operate in each partition.

  At this time, the IOP 3000 is divided into two or more logical IOPs in order to access two different logical memory spaces of the partition 1 and the partition 2. In FIG. 14, SLOTs 304-0 to 1 are assigned to the logical IOP00, SLOTs 304-2 to 3 are assigned to the logical IOP01, SLOTs 304-4 to 5 are assigned to the logical IOP02, and SLOTs 304-6 to 7 are assigned to the logical IOP03. Therefore, it is possible to assign SLOTs 304-0 to 3 to partition 1 and to assign SLOTs 304-4 to 7 to partition 2.

  The software that operates in each partition operates in the logical memory space 5p0 for each partition. The logical memory space 5p0 is a memory space whose address starts at address 0 in each partition. An address in this memory space is called a logical address. Since the software operates in the logical memory space 5p0, the software need not be aware of partitions.

  Here, a physical memory space serving as a real storage area with respect to a virtual memory space of the information processing system will be described. This memory space is called a physical memory space. FIG. 15 is a schematic diagram for explaining the physical memory space. As shown in FIG. 15, the physical memory space 400 is divided into a HW control area 410 and a main memory area 420. The physical memory space 400 is also a memory space whose address starts from address 0. The logical memory space 5p0 of each partition is developed in the main memory space 420.

  The HW control area 410 is an area used by the EPU1xy, DGP1000, and IOP300m. The main memory area 420 is an area for the logical memory space 5p0 used in each partition. The HW control area 410 and the main memory area 420 are divided at a fixed HW boundary address 430. EPU1xy, DGP1000, and IOP300m recognize the HW boundary address 430. The main memory area 420 is divided into 128 256 MB (megabyte) fixed parts called MU6jk. Each part is given a MU number for identifying MU6jk. The MU number is continuously assigned to the physical address, and the address is uniquely determined from the MU number. For example, when the MU number is 3, the physical address is “HW boundary address 430 + 256 MB × 3”. In the physical memory space 400, a MU6jk space is allocated to the logical memory space of each partition.

  For example, in FIG. 15, MU00 to MU07 are assigned to the logical memory space 510 of partition 1, and MU08 to MU4F are assigned to the logical memory space 520 of partition 2. The software of each partition operates in this allocated logical memory space 5p0, but the address recognized by the software is the logical address for each partition. That is, the software in the partition 1 uses logical addresses from 0h to 7FFFFFFFh.

  An IOP management table 411 shown in FIG. 16 is stored in the HW control area 410 of the physical memory space 400 in FIG. This is the same as the IOP management table 1310 of FIG. The physical address in which the IOP management table 411 is stored is fixed, and the DGP 1000, the EPU 1xy, and the IOP 300m recognize the physical address.

  Further, the address management table 5p1 shown in FIG. 17 and the logical IOP configuration table 5p2 shown in FIG. 18 are stored in each of the logical memory spaces 5p0 of each partition shown in FIG. The logical addresses in which the address management table 5p1 and the logical IOP configuration table 5p2 are stored are fixed, and these are stored in the first MU 6jk in the logical memory space 5p0. The DGP 1000, the EPU 1xy, and the IOP 300m recognize the logical address in which the address management table 5p1 and the logical IOP configuration table 5p2 are stored.

  The address management table 5p1 is the same as the address management table 132p of FIG. 6 of the DGP 1000 (p is 1 in FIG. 6). The logical IOP configuration table 5p2 is basically the same as the logical IOP configuration table 133p (p is 1 in FIG. 8) of FIG. 8 of the DGP 1000, but there are more types of identifiers stored in the entries than those of the DGP 1000. . The logical IOP configuration table 5p2 includes a logical IOP in addition to an identifier “configuration” indicating that the logical IOP is configured in the partition and an identifier “unconfigured” indicating that the partition is not configured. An identifier “built-in” indicating that is stored.

  The logical address of the logical memory space 5p0 is an address that can be recognized only by software. When the EPU1xy, the DGP 1000, and the IOP 300m access a logical address instructed by software, it is necessary to convert the logical address into a physical address in the physical memory space 400. The address management table 132p (3m2-n1 or 5p1) and the HW boundary address 430 are used for the conversion from the logical address to the physical address. The logical address is converted into a logical address by the following equation. The MU number input in the following equation is obtained as an entry corresponding to the address number of the logical address in the address management table 132p (3m2-n1 or 5p1). The offset is the remainder of dividing the logical address by 256 MB.

HW boundary address 430 + (MU number × 256 MB) + offset (1)
For example, when the logical address is 30000100h in the logical memory space 510 of the partition 1 in FIG. 15, the address number is 3, and the corresponding MU number is “3” from MU03. The offset is 100h. Therefore, the corresponding physical address is from equation (1):
HW boundary address 430 + (3 x 256MB) + 100h
It is obtained.

  Next, operations from initialization to input / output setting in the information processing system of this embodiment will be described.

  Here, it is assumed that the information processing system is divided into section 1 and section 2 as shown in FIG. In addition, SLOTs 304-0 to 1 of IOP3000 are assigned to logical IOP00, SLOTs 304-2 to 3 are assigned to logical IOP01, SLOTs 304-4 to 5 are assigned to logical IOP02, and SLOTs 304-6 to 7 are assigned to logical IOP03. It has been. Further, as shown in FIG. 14, other configurations such as the EPU 1xy and the memory 20x are also set corresponding to each of the partition 1 and the partition 2.

  When the CH numbers corresponding to each logical IOP are CH00 and CH01, the IOP management table 1310 of the DGP 1000 is as shown in the table of FIG. When the logical memory space of the partition 1 is as indicated by reference numeral 510 shown in FIG. 15, the address management table 1321 of the partition 1 of the DGP 1000 is as shown in the table of FIG. Similarly, for the partition 2, when the logical memory space is as indicated by reference numeral 520 shown in FIG. 15, the address management table 1322 of the partition 2 of the DGP 1000 is as shown in the table of FIG.

  When the information processing system is initialized by power-on or the like, the DGP 1000 executes initialization means. FIG. 22 is a flowchart showing the procedure of DGP initialization means. The DGP 1000 clears all the physical memory space 400 (step 1211). Subsequently, the IOP management table 1310 in the local memory 1300 is stored as the IOP management table 411 in the HW control area 410 (step 1212). At this time, the IOP management table 411 is as shown in FIG.

  Next, in order to initialize the partition 1 and the partition 2, the DGP 1000 executes the partition initialization unit 1202 for each partition. FIG. 23 is a flowchart showing the procedure of the DGP section initialization means.

  The DGP 1000 reads the address management table 132p of the partition p designated from the address management table array 1320 of the local memory 1300 (step 1221). Subsequently, MU6jk defined in the address management table 132p is converted into a physical address from the address number, and MU6jk is cleared (step 1222). Then, the specific address b in the logical memory space 5p0 of the designated partition p is converted into a physical address b 'by the address management table 132p, and the address management table 132p is set in the address management table 5p1 (step 1223).

  Subsequently, the DGP 1000 reads the logical IOP configuration table 133p of the partition p specified from the logical IOP configuration table array 1330 of the local memory 1300 (step 1224). Then, the specific address c in the logical memory space 5p0 of the designated partition p is converted into a physical address c 'by the address management table 132p, and the logical IOP configuration table 133p is set in the logical IOP configuration table 5p2 (step 1225). Further, an instruction to incorporate a logical IOP defined in the logical IOP management table 133p is executed (step 1226).

  By the partition initialization means described above, the address management table 511 shown in FIG. 20 and the logical IOP configuration table 512 shown in FIG. 24 are stored at specific addresses in the logical memory space 510 of the partition 1. Further, the address management table 521 shown in FIG. 21 and the logical IOP configuration table 522 shown in FIG. 25 are stored at specific addresses in the logical memory space 520 of the partition 2. Then, in accordance with the logical IOP configuration tables 512 and 522 of the partition 1 and the partition 2, the DGP 1000 executes an incorporation instruction.

  Subsequently, the procedure of the incorporating means by the DGP 1000 will be described. FIG. 26 is a flowchart showing the procedure of the DGP incorporation means.

  The DGP 1000 reads the logical IOP configuration table array 1330 from the local memory 1300 (step 1231). Subsequently, the logical IOP configuration table 133p in which the logical IOPmn specified from the logical IOP configuration table array 1330 is configured is searched for and the corresponding partition p is obtained (step 1232). The address management table 132p for the partition p is read from the local memory 1300 (step 1233). Then, the specific address c in the logical memory space 5p0 of the partition p is converted into a physical address c 'from the address management table 132p, and the logical IOP configuration table 5p2 of the partition p is read (step 1234). The state of the designated logical IOPmn is confirmed from the entry of the logical IOPmn in the logical IOP management table 5p2 (step 1235), and it is determined whether or not the logical IOPmn is set as a configuration (step 1236).

  When the logical IOPmn is set as the configuration in step 1236, the DGP 1000 sets the head physical address d ′ of the logical memory space 5p0 of the partition p and the logical IOP number mn for the IOPm corresponding to the logical IOPmn. (Step 1237). It waits for a report from IOPm (step 1238), and determines whether the integration is successful (step 1239).

  If the integration is successful in step 1239, the DGP 1000 sets the integration in the logical IOPmn entry of the logical IOP configuration table 5p2 of the logical memory space 5p0 of the partition p (step 1240). Subsequently, it is determined where the instruction source is (step 1241). If it is determined in step 1241 that the instruction source is an arithmetic processing unit, the integration success is reported to EPU1xy (step 1242). On the other hand, if it is determined in step 1241 that the instruction source is the partition incorporation means, no report is made anywhere.

  If No in step 1236 or No in step 1239, it is determined where the instruction source is (step 1243). When the instruction source is determined to be an arithmetic processing unit, the integration failure is reported to EPU1xy (step 1244). If it is determined in step 1243 that the instruction source is the partition incorporation means, no information is reported anywhere.

  When the above-described incorporating means is executed for the logical IOP00, the result is as follows. Partition 1 is obtained from the logical IOP configuration table 1331 of partition 1 in FIG. 24 defined in the logical IOP configuration table array 1330 (step 1231). Then, the logical address corresponding to the partition 1 is converted into a physical address by the address management table 1321 in FIG. Further, the logical IOP configuration table 512 of the partition 1 in FIG. 24 is read to check the state of the logical IOP (steps 1232 to 1236). At this time, since the logical IOP00 is set as the configuration in the logical IOP configuration table 512, the logical IOP00 is designated as the IOP0 corresponding to the logical IOP00 and the incorporation instruction is performed. When the incorporation is completed, the entry of the logical IOP00 in the logical IOP configuration table 512 of FIG. 24 is set to the incorporation, and the logical IOP00 enters the incorporation state (steps 1232 to 1242).

  If the logical IOP state is not configuration, it is not incorporated (steps 1243 to 1244). Further, when the above-described incorporation means is executed for the logical IOP02, the entry of the logical IOP02 in the logical IOP configuration table 522 shown in FIG. 25 is set to incorporation.

  The IOP 300m receives an incorporation instruction from the DGP 1000, receives an interrupt corresponding to the designated logical IOPmn, and executes an incorporation means for the designated logical IOPmn. The procedure of the incorporation means will be described below. FIG. 27 is a flowchart showing the procedure of the IOP incorporating means.

  The IOP 300m checks the state of the logical IOPmn from the flag 3m2-n2 in the area 3m2-n of the local memory 3m2 corresponding to the designated logical IOPmn (step 1561). Then, it is determined whether or not the logical IOPmn is incorporated (step 1562). If the logical IOPmn is not incorporated, the area 3m2-n is cleared (step 1563). The IOP management table 411 is read from the specific address a in the HW control area 410 (step 1564). Based on the IOP management table 411, the CH slot management table 3m2-n0 of the area 3m2-n is set (step 1565).

  Subsequently, the IOP 300m reads the address management table 5p1 of the partition p from the head physical address d 'and the specific address b of the logical memory space 5p0 of the designated partition p (step 1566). The address management table 5p1 is set in the address management table 3m2-n1 of the area 3m2-n (step 1567), and the flag 3m2-n2 of the area 3m2-n is set to be incorporated (step 1568). Thereafter, the integration success is reported to the DGP 1000 (step 1569). In the case of Yes in step 1562, the integration failure is reported to the DGP 1000 (step 1570).

  When executing the above-described incorporating means for the logical IOP00, the IOP 300m checks the flag 302-02 of the corresponding area 302-0 and checks the state of the logical IOP00 (steps 1561 and 1562). At this time, since the flag 302-02 is not in the built-in state, the area 302-0 is cleared (step 1563). Then, the IOP management table 411 shown in FIG. 19 is read from the HW control area 410, and the CH slot management table 302-00 shown in FIG. 28 is created in the area 302-0 (steps 1564 and 1565).

  Subsequently, the physical address is obtained from the head physical address and the specific address in the logical memory space 510 of the designated partition 1, and the address management table 511 in FIG. 20 is read and stored in the address management table 302-01 in the area 302-0. (Steps 1566, 1567). Finally, the flag 302-02 of the area 302-0 is set to incorporation, and the incorporation success is reported to the DGP 1000 (steps 1568 and 1569).

  If it has already been incorporated, the failure of incorporation is reported to the instruction source (step 1570). Further, when the incorporating means 30 is executed for the logical IOP02, since it is a partition 2, the address management table 302-21 of FIG. 21 and the CH slot management table 302-20 shown in FIG. 29 are stored in the area 302-2. The flag 302-22 is set to be incorporated.

  In this way, the logical IOPmn corresponding to the partition 1 and the partition 2 includes the CH slot management table 3m2-n0 indicating the SLOT information allocated to the corresponding partition, and the address management table 3m2-n1 indicating the address information for each partition. In the area 3m2-n for each logical IOPmn of its own local memory 3m2. Therefore, the logical address of the logical memory space 5p0 of each partition can be accessed after being converted into the physical address of the physical memory space 400.

  When the partition initialization means by the DGP 1000 is completed, the software starts operating on the EPU1xy. In the software, it is described in advance which CH number is set to which logical IOP and which peripheral processing device 500w is connected to that CH number in the initial stage. However, the software is not aware of which logical IOP is currently embedded. Therefore, the software requests configuration information from EPU1xy.

  When the EPU 1xy receives a request for configuration information from software, the EPU 1xy executes configuration information acquisition means. FIG. 30 is a flowchart showing the procedure of EPU configuration information acquisition means. As shown in FIG. 30, the EPU 1xy reads the logical IOP configuration table 5p2 of the specific address c in the logical memory space 5p0 and returns it to the software (step 1551).

  In the configuration information acquisition means described above, in the case of partition 1, the logical IOP configuration table 512 of FIG. 24 is read from a specific address in the logical memory space 510 and returned to the software. In the case of partition 2, the logical IOP configuration table 522 of FIG. 25 is returned to the software. At this time, each logical IOP entry in the logical IOP configuration tables 512 and 522 is set to be embedded. When returning the table to software, EPU1xy converts the logical address to a physical address.

  As a result, the software can determine which logical IOP is incorporated, and data can be transferred between the memory 20x and the peripheral processing device 500w. However, the memory 20x that can be used by the software is the logical memory space 5p0 of the corresponding partition p, which is designated by a logical address.

  In order for the software to enable data transfer between the memory 20x and the peripheral processing device 500w, an input / output setting instruction is given to the EPU1xy. When the EPU 1xy receives an input / output setting instruction from the software, the EPU 1xy executes input / output instruction means. The procedure of the input / output instruction means by EPU1xy will be described below. FIG. 31 is a flowchart showing the procedure of the EPU input / output instruction means. Hereinafter, IOP300m is abbreviated as IOPm.

  The EPU1xy reads the logical IOP configuration table 5p2 at the specific address c in the logical memory space 5p0 and checks the state of the designated logical IOPmn (Step 1531). Then, it is determined whether or not the logical IOPmn is incorporated (step 1532). As a result of the determination, if it is incorporated, the logical IOPmn, the CH number h, the logical address e of the transfer destination, and the count f designated in the IOPm corresponding to the designated logical IOPmn are designated to instruct the input / output setting ( Step 1533).

  Subsequently, the EPU1xy waits for a response from the IOPm (step 1534) and determines whether the input / output setting is successful (step 1535). When the input / output setting is successful, the success of the input / output setting is reported to the software (step 1536). In the case of No in step 1535, the failure of the input / output setting is reported to the software (step 1537).

  In the case of an input / output setting instruction to the logical IOP00 in the partition 1, the logical IOP configuration table 512 of FIG. 24 is read from the logical memory space 510 by the above-described input / output instruction means, and the state of the logical IOP00 is confirmed (step 1531, 1532). At this time, the logical IOP00 is incorporated and set as incorporation in the logical IOP configuration table 512. Therefore, the IOP0 corresponding to the logical IOP00 is designated by specifying the logical IOP00, the designated CH number, the transfer destination logical address, and the count (step 1533). Thereafter, the end of transfer setting from IOP0 is waited for, and if there is no problem, the success of input / output setting is reported to the software (steps 1534 to 1536).

  If the state of the logical IOP00 is not built-in, or if an I / O setting failure is reported from the IOP0, an I / O setting failure is reported to the software (step 1537). When the software receives information on the success or failure of the input / output setting from the EPU1xy, the software completes the input / output instruction.

  When the software in the partition 2 instructs the EPU 1xy to perform input / output setting for the logical IOP02, the logical IOP configuration table 522 in FIG. 25 in the logical memory space 520 in the partition 2 is used and processed.

  On the other hand, when the IOPm receives an input / output setting instruction from the EPU1xy, the designated logical IOPmn is determined by the interrupt unit 3m0-n of the processing unit 3m0, and the input / output is performed using the area 3m2-n corresponding to the logical IOPmn. The instruction means is executed. The procedure of the input / output instruction means by IOPm will be described below. FIG. 32 is a flowchart showing the procedure of the IOP input / output instruction means.

  The IOPm checks the state of the logical IOPmn from the flag 3m2-n2 in the area 3m2-n of the local memory 3m2 corresponding to the designated logical IOPmn (step 1591). It is determined whether or not the logical IOPmn is incorporated (step 1592). As a result of the determination, if it is incorporated, the address management table 3m2-n1 is read from the area 3m2-n, and the designated logical address e is converted to the physical address e '(step 1593).

  Subsequently, the IOPm reads the CH slot management table 3m2-n0 from the area 3m2-n, and converts the designated CH number h into a SLOT number h '(step 1594). SLOT3m4-h ′ of SLOT number h ′ is controlled, and data is transferred between the peripheral processing device 500w connected to SLOT3m4-h ′ and the memories 200 to 207 from the physical address e ′ by the designated count f. Perform (step 1595). After waiting for the completion of the transfer (step 1596), it is determined whether or not the transfer is successful (step 1597).

  When the transfer is successful in step 1597, the IOPm reports the success of the input / output setting to the EPU1xy (step 1598). On the other hand, if No at step 1597, the failure of the input / output setting is reported to EPU1xy (step 1599).

  When the above input / output instruction means is executed for the logical IOP00, the operation is as follows. The flag 302-02 is read from the area 302-0 of the local memory 302, and the state of the logical IOP00 is confirmed (steps 1591 and 1592). At this time, since the flag 302-2 is set to built-in, the address management table 302-01 of FIG. 20 is read from the area 302-0, and the logical address of the designated logical memory space 510 is set as the physical address. Conversion is performed (step 1593). Subsequently, the CH slot management table 302-00 of FIG. 28 is read, the designated CH number is converted into a SLOT number (step 1594), and the SLOT 304-h ′ is controlled to designate the designated count from the physical address. The data is transferred by the amount (step 1595).

  Then, the completion of the transfer is awaited and confirmed, and the success of the input / output setting is reported to EPU1xy (steps 1596 to 1598). If the state of the logical IOP is not embedded or the transfer fails, an I / O failure is reported to the EPU1xy (step 1599). When the input / output instruction unit 32 is executed for the logical IOP02, the address management table 302-21 in FIG. 21 and the CH slot management table 302-20 in FIG. Data is transferred to the memory space 520 using the SLOT assigned to the logical IOP02.

  Thus, the IOP0 can perform data transfer using the SLOT for each logical IOP in the logical IOP00 and the logical IOP02 obtained by dividing a plurality of SLOTs into the logical memory spaces 520 and 520 of the corresponding partition 1 and partition 2, respectively. It becomes possible.

  As described above, the information processing system according to the present embodiment can divide the entire plurality of slots included in the plurality of input / output processing devices into a plurality of sections. As a result, an input / output processing device that is physically regarded as a single unit can be divided into a plurality of logical input / output processing devices, and an input / output operation can be performed corresponding to each information processing device.

  Further, by this method, a plurality of information processing systems in the company can be integrated, and the resources resulting from the integration can be further subdivided according to the load status to function as a plurality of information processing apparatuses.

  Next, another function of the information processing system of this embodiment will be briefly described. Here, similarly to the description from the initialization to the input / output setting described above, it is assumed that the information processing system is divided into a partition 1 and a partition 2 as shown in FIG. When the software is operating in each partition, if the load applied to any partition becomes extremely large due to the difference in the load of each partition, it is necessary to reduce the load. Another function of the information processing system according to the present embodiment is that the logical IOP can be moved while the information processing system is operating in order to average the load applied to each partition in such a case. It is to be. The operation will be described below.

  It is assumed that the logical IOP02 in the partition 2 is moved to the partition 1 because the input / output to the peripheral processing device 500w in the partition 1 is heavy. Further, it is assumed that the peripheral processing device 5002 required by the partition 1 is connected to the logical IOP02, and the software of the partition 1 and the partition 2 can communicate with each other.

  When the partition 1 and partition 2 software communicate with each other and decide to move the logical IOP02 from the partition 2 to the partition 1, the partition 2 software disconnects the logical IOP02 by specifying EPU1xy as the logical IOP02. Give instructions. When the EPU 1xy receives the disconnection instruction, the EPU 1xy executes the disconnecting means.

  The procedure of the disconnecting means by EPU1xy will be described. FIG. 33 is a flowchart showing the procedure of the EPU disconnecting means. In FIG. 33, the case of logical IOPmn is assumed.

  As shown in FIG. 33, the EPU 1xy reads the logical IOP configuration table 5p2 of the specific address c in the logical memory space 5p0 and confirms the state of the designated logical IOPmn (step 1521). It is determined whether or not the logical IOPmn is incorporated (step 1522). As a result of determination, if it is incorporated, the logical IOPmn is designated to the DGP 1000 to instruct detachment (step 1523). It waits for a response from the DGP 1000 (step 1524). Then, it is determined whether or not the separation is successful (step 1525). If the disconnection is successful, EPU1xy reports the disconnection success to the software (step 1526).

  If the answer is No in Step 1522 or Step 1525, the disconnection failure is reported to the software (Step 1527).

  When the above disconnecting means is executed for the logical IOP02, the EPU1xy reads the logical IOP configuration table 522 of FIG. 25 from the logical memory space 520 and confirms the state of the designated logical IOP02 (steps 1521 and 1522). At this time, since the logical IOP02 is set to be incorporated in the logical IOP configuration table 522, the logical IOP02 is designated and instructed to be disconnected from the DGP 1000 (step 1523). Thereafter, it waits for a response from the DGP 1000, and if the disconnection is successful, reports the disconnection success to the software (steps 1524 to 1526). If the logical IOP state is not built-in or disconnection fails, the disconnection failure is reported to the software (step 1527).

  Subsequently, when the DGP 1000 receives an instruction to disconnect the logical IOP02 from the EPU1xy, the DGP 1000 executes the disconnecting unit. Below, the procedure of the separation means by DGP1000 is demonstrated. FIG. 34 is a flowchart showing the procedure of the DGP disconnecting means. In FIG. 34, the case of logical IOPmn is assumed.

  The DGP 1000 performs the same processing as the steps from steps 1231 to 1233 of the incorporating means described with reference to FIG. 26, and performs processing until the address management table 132p is read (steps 1251 to 1253). Subsequently, the specific address b in the logical memory space 5p0 of the partition p is converted into the physical address b 'from the address management table 132p, and the logical IOP configuration table 5p2 of the partition p is read (step 1254). Then, the state of the designated logical IOPmn is confirmed from the entry of the logical IOPmn in the logical IOP management table 5p2 (step 1255). It is determined whether or not the logical IOPmn is incorporated as a configuration (step 1256).

  When the logical IOPmn is incorporated as a configuration, the DGP 1000 instructs the IOPm corresponding to the logical IOPmn to disconnect (step 1257). Thereafter, a report from IOPm is waited for (step 1258). Then, it is determined whether or not the separation is successful (step 1259). If the separation is successful, the configuration is set in the logical IOPmn entry of the logical IOP configuration table 5p2 of the logical memory space 5p0 of the partition p (step 1260). Subsequently, it is determined where the instruction source is (step 1261). If it is determined that the instruction source is an arithmetic processing unit, the disconnection is reported to EPU1xy (step 1262). If it is determined in step 1261 that the instruction source is the partition incorporation means, no report is made anywhere.

  In the case of No in step 1256 or in the case of No in step 1259, the DGP 1000 determines where the instruction source is (step 1263). If the instruction source is determined to be an arithmetic processing unit, the failure is reported to EPU1xy and a failure is reported (step 1264). On the other hand, if it is determined in step 1243 that the instruction source is the partition incorporation means, no information is reported anywhere.

  The case where the logical IOP02 of the partition 2 is separated will be described as follows. The DGP 1000 reads the logical IOP configuration table array 1330 from the local memory 1300 and obtains the partition 2 from the logical IOP configuration table 1332 of FIG. 25 (steps 1251 and 1252). Then, the address management table 1322 of FIG. 21 is read from the local memory 1300 (step 1253). Subsequently, the specific address in the logical memory space 520 of the partition 2 is converted into a physical address, the logical IOP configuration table 522 of the partition 2 in FIG. 25 is read, and the state of the logical IOP02 is confirmed (steps 1254 to 1256). At this time, since the logical IOP02 is set to be included in the logical IOP configuration table 522, the corresponding IOP0 is instructed to disconnect the logical IOP02 (step 1257).

  Thereafter, a response from IOP0 is waited for. When the detachment is successful, the logical IOP02 in the logical IOP configuration table 522 in the logical memory space 520 is set to the configuration, and the detachment success is reported to EPU1xy (steps 1258 to 1262). If the state of the logical IOP02 is not embedded or the disconnection fails, the disconnection failure is reported to the EPU1xy (steps 1263 and 1264).

  Subsequently, when the IOP0 receives a disconnection instruction from the DGP 1000, the interrupting unit 300-2 of the processing unit 300 determines the specified logical IOP02, and the disconnecting unit 31 uses the area 302-2 corresponding to the logical IOP02. Execute. The procedure of the IOPm disconnecting means will be described below. FIG. 35 is a flowchart showing the procedure of the IOP separating means. In FIG. 35, the case of logical IOPmn is assumed.

  The IOPm checks the state of the logical IOPmn from the flag 3m2-n2 in the area 3m2-n of the local memory 3m2 corresponding to the designated logical IOPmn (step 1581). Then, it is determined whether or not the logical IOPmn is incorporated (step 1582). When the logical IOPmn is incorporated, the flag 3m2-n2 of the area 3m2-n is set to be disconnected (step 1583), and the disconnection success is reported to the DGP 1000 (step 1584). On the other hand, if No at step 1582, the disconnection failure is reported to the DGP 1000 (step 1585).

  When detaching the logical IOP02 of the partition 2, when the detaching means is executed, the IOP0 confirms the state of the logical IOP02 from the flag 302-22 of the area 302-2 corresponding to the designated logical IOP02 (steps 1581 and 1582). . At this time, since the flag 320-22 is set to incorporation, the flag 302-22 is set to separation, and the separation success is reported to the DGP 1000 (steps 1583 and 1584). If the state of the logical IOP02 is not built-in, disconnection is reported to the DGP 1000 and a failure is reported (step 1585).

  As a result, the logical IOP02 is separated from the partition 2, and the availability capability instruction cannot be performed. Then, in order to move the logical IOP02 to the partition 1, the software of the partition 2 designates the partition 1 and the logical IOP02 to the EPU1xy and instructs the partition movement.

  When the EPU 1xy receives the designation of the partition 1 and the logical IOP02 and the partition movement instruction from the software, the EPU 1xy executes the partition movement means 13. Below, the procedure of the partition movement means by EPU1xy is demonstrated. FIG. 36 is a flowchart showing the procedure of EPU partition movement means. In FIG. 36, the case of logical IOPmn is assumed.

  The EPU1xy reads the logical IOP configuration table 5p2 at the specific address c in the logical memory space 5p0 and checks the state of the designated logical IOPmn (step 1541). Then, it is determined whether or not the logical IOPmn is set in the configuration (step 1542). If the logical IOPmn is set in the configuration, the DGP 1000 is instructed to move the designated logical IOPmn to the designated partition q (step 1543), and a response from the DGP 1000 is waited (step 1544). Subsequently, it is determined whether or not the partition movement is successful (step 1545). If the partition movement is successful, the partition movement success is reported to the software (step 1546). On the other hand, in the case of No in step 1545, the partition movement failure is reported to the software (step 1547).

  When the logical IOP02 of the partition 2 is moved to the partition 1, the operation is as follows. The EPU1xy reads the logical IOP configuration table 522 from the specific address in the logical memory space 520 of the partition 2 and checks the state of the logical IOP02 (Steps 1541 and 1542). At this time, since the logical IOP02 is set as the configuration in the logical IOP configuration table 522, the DGP 1000 is instructed to move the logical IOP02 to the partition 1 (step 1543). Thereafter, it waits for a response from the DGP 1000, and if the movement is successful, reports the movement success to the software (steps 1544 to 1546). If the status of the logical IOP02 is not configuration or the migration fails, the migration failure is reported to the software (step 1547).

  When the DGP 1000 receives an instruction to move the logical IOP02 from the EPU1xy to the partition 1, the DGP 1000 executes the partition moving unit 1205. Below, the procedure of the partition moving means by DGP1000 is demonstrated. FIG. 37 is a flowchart showing the procedure of the DGP section moving means. In FIG. 37, the case of logical IOPmn is assumed.

  The DGP 1000 performs the same processing as the procedure from steps 1231 to 1235 of the incorporating means described with reference to FIG. 26, and performs processing until the status of the designated logical IOPmn is confirmed by the logical IOP management table 5p2 (steps 1271 to 1275). ). Subsequently, it is determined whether or not the logical IOPmn is set as a configuration (step 1276). If the logical IOPmn is set as a configuration, the logical IOPmn entry in the logical IOP configuration table 133p of the partition p of the local memory 1300 is set to be unconfigured (step 1277).

  Subsequently, the DGP 1000 sets the logical IOPmn entry in the logical IOP configuration table 5p2 of the logical memory space 5p0 of the partition p to be unconfigured (step 1278). The logical IOPmn entry in the logical IOP configuration table 133q of the partition q of the local memory 1300 is set in the configuration (step 1279). The address management table 132q for the partition q is read from the local memory 1300 (step 1280). Then, the specific address c in the logical memory space 5q0 of the partition q is converted into a physical address c 'from the address management table 132q, and the entry of the logical IOPmn in the logical IOP configuration table 5q2 of the partition q is set to the configuration (step 1281). Thereafter, the movement success is reported to EPU1xy (step 1282). On the other hand, in the case of No in step 1276, the DGP 1000 reports the movement failure to the EPU1xy (step 1283).

  The case where the logical IOP02 of the partition 2 is moved to the partition 1 will be described as follows. The DGP 1000 obtains the corresponding partition 2 from the logical IOP configuration table 1332 in which the logical IOP02 of the logical IOP configuration table array 1330 of the local memory 1300 is configured (steps 1271 and 1272). The address management table 1322 of the partition 2 is read from the local memory 1300, the specific address of the logical memory space 520 of the partition 2 is converted into a physical address, the logical IOP configuration table 522 of the partition 2 is read, and the state of the logical IOP02 is confirmed ( Steps 1273-1276). At this time, since the logical IOP02 is set as configured in the logical IOP configuration table 522, the entries of the logical IOP02 in the logical IOP configuration table 1332 of the local memory 1300 and the logical IOP configuration table 522 of the partition 2 are set to unconfigured ( Steps 1277 and 1278), the entry of the logical IOP02 in the logical IOP configuration table 1331 of the partition 1 is set to the configuration (step 1279).

  Then, the address management table 1321 of the partition 1 is read from the local memory 1300, the specific address in the logical memory space 510 of the partition 1 is converted into a physical address, and the entry of the logical IOP02 in the logical IOP configuration table 512 of the partition 1 is set to the configuration. Then, the movement success is reported to EPU1xy (steps 1280 to 1282). When the state of the logical IOP02 is not “configuration”, the migration failure is reported to the EPU1xy (step 1283).

  Thereby, the entry of the logical IOP02 in the logical IOP configuration table 522 of the partition 2 becomes unconfigured, and the entry of the logical IOP02 of the logical IOP configuration table 511 of the partition 1 becomes a configuration. When the software of the partition 2 is notified of the transfer success from the EPU1xy, the software of the partition 1 notifies the software of the partition 1 that the transfer of the logical IOP02 is successful, and the software of the partition 1 instructs the EPU1xy to incorporate the logical IOP02.

  When EPU1xy is instructed by software to incorporate logical IOP02, it executes the embedding means 10. Below, the procedure of the incorporating means by EPU1xy is demonstrated. FIG. 38 is a flowchart showing the procedure of EPU incorporation means. In FIG. 38, the case of logical IOPmn is assumed.

  The EPU1xy reads the logical IOP configuration table 5p2 at the specific address c in the logical memory space 5p0 and confirms the state of the designated logical IOPmn (step 1511). Then, it is determined whether or not the logical IOPmn is set in the configuration (step 1512). The logical IOPmn is set in the configuration, the logical IOPmn is designated to the DGP 1000 to instruct incorporation (step 1513), and a response from the DGP 1000 is waited (step 1514). Thereafter, it is determined whether or not the integration is successful (step 1515). If the integration is successful, the integration success is reported to the software (step 1516). On the other hand, when the integration fails, the integration failure is reported to the software (step 1517).

  The case where the logical IOP02 of the partition 2 is moved to the partition 1 will be described as follows. The EPU1xy reads the logical IOP configuration table 512 from the specific address in the logical memory space 510 of the partition 1 and checks the state of the logical IOP02 (Steps 1511 and 1512). At this time, since the logical IOP02 is set as the configuration in the logical IOP configuration table 512, the DGP 1000 is instructed to incorporate the logical IOP02 (step 1513). Thereafter, a response from the DGP 1000 is waited, and if the integration is successful, the integration success is reported to the software (steps 1514 to 1516). If the state of the logical IOP02 is not configuration or if the integration fails, the failure of the integration is reported to the software (step 1517). Thereafter, the incorporation process of the DGP 1000 is performed. Since the incorporation process by the DGP 1000 is the same as the incorporation means described with reference to FIG. 26, the detailed description thereof is omitted here.

  As a result, the logical IOP02 is incorporated in the partition 1, and the software in the partition 1 can use the logical IOP02. The partition movement can be normally performed so that the logical IOP02 operating in the partition 2 can operate in the partition 1.

  In a conventional information processing system, if a connection with a peripheral processing device is set in units of IOPs, the slot cannot be dynamically moved to a partition corresponding to another IOP after the information processing system is activated. It was. On the other hand, the information processing system according to the present embodiment can move slots to other sections even when the system is operating by grouping each slot corresponding to a logical IOP.

  In the information processing system according to the present embodiment, it is possible to allocate subdivided resources to places with high loads even during system operation. Therefore, even if the load level changes between peripheral processing devices during system operation in multiple connected peripheral processing devices, I / O processing is averaged and the processing power of the entire information processing system is utilized more efficiently. It becomes possible to do.

  Further, when a trouble occurs in the peripheral processing device, the peripheral processing device can be connected to the logical IOP corresponding to the slot to which the peripheral processing device is connected without turning off the system power. Can also be exchanged.

  Note that the initialization unit, the input / output setting unit, the separation unit, and the partition movement unit by the information processing system of the present embodiment may be applied to a program that is executed by a computer having a plurality of input / output processing devices.

It is a block diagram showing an example of 1 composition of an information processing system of this embodiment. It is a block diagram which shows one structural example of a logic card | curd. It is a block diagram which shows the example of 1 structure of DGP. It is a figure for demonstrating an IOP management table. It is a figure for demonstrating the address management table arrangement | sequence 1320. FIG. It is a figure for demonstrating an address management table. It is a table | surface which shows a logic IOP structure table arrangement | sequence. It is a figure for demonstrating a logic IOP structure table. It is a block diagram which shows the example of 1 structure of EPU. It is a block diagram which shows the example of 1 structure of IOP. It is a figure for demonstrating CH slot management table. It is a figure which shows an address management table. It is a figure for demonstrating a flag. It is a block diagram which shows an example of partition division. It is a schematic diagram for demonstrating a physical memory space. It is a figure which shows the IOP management table stored in the HW control area | region shown in FIG. It is a figure which shows the address management table stored in the logical memory space shown in FIG. FIG. 16 is a diagram showing a logical IOP configuration table stored in the logical memory space shown in FIG. 15. It is a figure which shows the IOP management table of DGP. It is a figure which shows the address management table of the division 1 of DGP. It is a figure which shows the address management table of the division 2 of DGP. It is a flowchart which shows the procedure of the initialization means of DGP. It is a flowchart which shows the procedure of the division | segmentation initialization means of DGP. It is a figure which shows an example of a logical IOP structure table. It is a figure which shows an example of a logical IOP structure table. It is a flowchart which shows the procedure of the incorporating means of DGP. It is a flowchart which shows the procedure of the incorporating means of IOP. It is a figure which shows an example of CH slot management table. It is a figure which shows an example of CH slot management table. It is a flowchart which shows the procedure of the structure information acquisition means by EPU. It is a flowchart which shows the procedure of the input / output instruction | indication means of EPU. It is a flowchart which shows the procedure of the input / output instruction means of IOP. It is a flowchart which shows the procedure of the isolation | separation means of EPU. It is a flowchart which shows the procedure of the isolation | separation means of DGP. It is a flowchart which shows the procedure of the isolation | separation means of IOP. It is a flowchart which shows the procedure of the partition moving means of EPU. It is a flowchart which shows the procedure of the division moving means of DGP. It is a flowchart which shows the procedure of the incorporating means of EPU.

Explanation of symbols

3000 to 3007 Input / output processing unit (IOP)
1000 Diagnostic processing equipment (DGP)

Claims (9)

An IOP management table in which information of the slot is described for each logical IOP that is a unit of a group divided for a plurality of slots for connection to a peripheral processing device, and the logical IOP for each partition that is a unit of input / output processing. A memory that stores a logical IOP configuration table indicating whether or not it is included as a configuration, and a diagnostic processing device that includes a processing unit that externally instructs the incorporation of the logical IOP when an initialization instruction is input ,
When receiving the incorporation instruction from the plurality of slots, the memory for storing the information of the logical IOP, and the diagnostic processing device, the IOP management table and the logical IOP configuration table are referred to, A plurality of input / output processing devices including a processing unit for storing information on a partition of a logical IOP belonging to a slot in the memory;
An information processing system. When the processing unit of the diagnostic processing device receives a disconnection instruction including information on the logical IOP to be disconnected from the outside, the processing unit identifies the target input / output processing device with reference to the IOP management table, and specifies the specified input / output Instruct the processing device to disconnect,
The information processing system according to claim 1, wherein the processing unit of the input / output processing device registers the logical IOP to be disconnected in a disconnected state when receiving the disconnection instruction from the diagnostic processing device.   When the processing unit of the diagnostic processing apparatus receives from the outside a partition movement instruction including information on the logical IOP to be disconnected and a partition to be moved, a logical IOP configuration table of the original partition to which the logical IOP to be disconnected belongs The information processing system according to claim 2, wherein the logical IOP configuration table of the destination partition is updated in accordance with the partition movement instruction. Input / output setting of an information processing system having a plurality of input / output processing devices having a plurality of slots for connection to an external peripheral processing device and a diagnostic processing device for instructing the input / output processing device to perform setting An information processing method for
The diagnostic processing device includes an IOP management table in which information of the slot is described for each logical IOP that is a unit of a group divided for the plurality of slots, and the logical IOP for each partition that is a unit of input / output processing. Storing in a memory a logical IOP configuration table indicating whether it is included as a configuration;
The diagnostic processing device, when an initialization instruction is input, instructing the plurality of input / output processing devices to incorporate the logical IOP;
When each of the plurality of input / output processing devices receives the instruction for incorporation from the diagnostic processing device, the I / O processing device refers to the IOP management table and the logical IOP configuration table, and partitions the logical IOP belonging to each slot of the own device. Storing information of
An information processing method comprising: When the diagnosis processing device receives a disconnection instruction including information on the logical IOP to be disconnected from the outside, the target input / output processing device is identified with reference to the IOP management table, and the identified input / output processing device is identified. Instructing the separation;
When the input / output processing device receives the disconnection instruction from the diagnostic processing device, registering the logical IOP to be disconnected in a disconnected state;
The information processing method according to claim 4. When the diagnostic processing apparatus receives from the outside a partition movement instruction including information on the logical IOP to be detached and the destination partition, the logical IOP configuration table of the original partition to which the logical IOP to be separated belongs and the movement Updating the logical IOP configuration table of the previous partition in accordance with the partition movement instruction;
The information processing method according to claim 5. A program for causing a computer having a plurality of input / output processing devices to have a plurality of slots for connecting to an external peripheral processing device,
An IOP management table in which information of the slot is described for each logical IOP that is a unit of a group divided for the plurality of slots, and whether or not the logical IOP is included in each partition that is a unit of input / output processing. Storing a logical IOP configuration table indicating whether or not in a memory;
When an initialization instruction is input, each of the plurality of input / output processing devices is referred to the IOP management table and the logical IOP configuration table, and the logical IOP belonging to each slot is determined for each input / output processing device. Storing parcel information; and
A program for causing the computer to execute a process including: A step of identifying a target input / output processing device by referring to the IOP management table when receiving a disconnection instruction including information on a logical IOP to be disconnected from the outside;
Registering the logical IOP to be disconnected in a disconnected state with respect to the identified input / output processing device;
The program according to claim 7, for causing the computer to execute a process including: When an instruction to move a partition including information on the logical IOP to be detached and the destination partition is received from the outside, the logical IOP configuration table of the original partition to which the logical IOP to be detached belongs and the logical IOP of the destination partition 9. The program according to claim 8, which causes the computer to execute a process including a step of updating a configuration table in accordance with the partition movement instruction.

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