JPS63152239A - Frame protecting circuit - Google Patents

Abstract

PURPOSE:To detect frame mis-synchronism and to reduce a forward protection time and a backward protection time by using a discrimination means so as to supervise whether or not specific detection pattern information in a storage means is consecutive. CONSTITUTION:Frame pulse detection means 2, 3 detecting a frame pulse at a frame pulse inserting position to output coincidence/dissidence information of pattern and information representing the type of pattern, and storage means (shift registers) 4, 5 storing sequentially by a prescribed number of output value of the means 2, 3 and discriminating means 6, 7 discriminating the end of forward protection and the end of backward protection from the information by the prescribed number of output values are provided. The dissident information in the shift registers 4, 5 is supervised by a discriminating means to discriminate the end to the forward protection and the end of backward protection due to out-of-synchronism. Moreover, the time required for the detection of out-of-synchronism and the confirmation of the synchronization recovery is reduced.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a frame protection circuit, and particularly to a frame protection circuit in which n (≧2) types of frame patterns are alternately included in a signal. The present invention relates to a preferred frame protection circuit.

[Conventional technology]

In the conventional method of detecting frame pulses in which two or more types of frame patterns alternate to protect frame synchronization, for example, the research practical application report of the Telecommunications Research Institute of Nippon Telegraph and Telephone Public Corporation, Vol. 25, No. 1 (1976), 114 As described on page 11B, the first pattern F and the second pattern F2 of frame pulses are checked, and if both patterns match, the frame pulses are counted as matching once. However, if there is a small number of mismatches (even if one of the patterns does not match), the mismatch of frame pulses is counted as one occurrence. Then, the results of the match or mismatch of these frame pulses are accumulated in a shift register or a counter, When one loss or mismatch continues for a predetermined number of times or more, it is determined that the backward protection or forward protection has ended, respectively.In this way, when the pattern matching results of multiple types of frame pulses are all -4, The reason why a frame pulse coincidence is counted as one time is to prevent a fixed pattern of a data signal included in a signal from being mistakenly recognized as a frame pulse, thereby preventing erroneous synchronization.

In addition, as other documents related to the prior art, JP-A-60-2
There is No. 14136.

[Problem that the invention seeks to solve]

In the above conventional technology, when frame protection is performed by detecting frame pulses in which n (≧2) patterns alternate, the number of frame protection stages is Nf, and the frame pulse insertion interval is T.
When (sec,), forward protection.

Regardless of rear protection, the time required for protection is n.
-Nf-T(sec,), and there is a problem that as n becomes larger, the time required for protection increases significantly, and the time required to detect loss of synchronization and confirm return of synchronization increases.

SUMMARY OF THE INVENTION An object of the present invention is to provide a frame protection circuit that reduces the number of times frame pulses are detected and compared, reduces the time required for forward protection and backward protection, and reduces the time required to detect synchronization loss and confirm synchronization recovery. .

[Means for solving problems]

The above object is to detect the frame pulse at the frame pulse insertion position to detect pattern match/mismatch information in a frame protection circuit that detects frame pulses in which n (≧2) types of frame patterns alternate and protects frame synchronization. frame pulse detection means for outputting information indicating the type of pattern; storage means for sequentially storing a specified number of output values of the frame pulse detection means; and termination of forward protection and termination of backward protection based on the specified number of information. This can be achieved by providing a determination means for making a determination.

[Effect]

In an out-of-frame synchronization state (excluding the case of frame erroneous synchronization to be described later), the coincidence/mismatch information outputted from the frame pulse detection means is information indicating that none of the n consecutive patterns match. Therefore, by monitoring the discrepancy information in the storage means with the determination means, it is possible to determine whether forward protection or backward protection has ended due to out-of-synchronization.

In an out-of-frame synchronization state due to frame synchronization error, the information indicating the type of pattern outputted from the frame pulse detection means becomes continuous pattern detection information of the same type. Therefore, an erroneous synchronization state can be detected by monitoring by the determining means whether specific detection pattern information in the storage means is consecutive.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a frame protection circuit according to an embodiment of the present invention, and in this embodiment, a case where n=2 will be explained.

The frame protection circuit includes a frame counter 1, a frame pulse detection circuit 2.3, shift registers 4, 5, a forward protection end determination circuit 6, a backward protection end determination circuit 7,
It is composed of 8 RS flip-flops.

The frame pulse detection circuit 2.3 detects the first pattern F, , and the second pattern of frame pulses of the manual data, and outputs them to the shift register 4.5. The shift registers 4.5 each receive the first patterns F2. Second
Detection/non-detection information of pattern F2 is sequentially accumulated for a specified number of pieces. These shift registers 4.5 are enabled by a frame pulse insertion timing identification signal outputted from the frame counter 1, and output a specific number of signals QA, Qs, and Qc, three in this embodiment.

The forward protection end determination circuit 6 includes a six-power NOR gate 6a that receives the outputs of the shift registers 4 and 5, a three-power AND gate 6b that receives the output of the shift register 4, and a human-power input that receives the output of the shift register 5. It consists of a three-man powered AND gate 6C, and a three-man powered OR gate 6d, which inputs the outputs of gates 6a+6, b, and 6c.

The backward protection end determination circuit 7 receives the Qa ratio output of the shift register 5, the Qs ratio output inverted signal, the inverted signal of the QA output of the shift register 4, the Q output, and a four-man power AND gate 7a, which receives the input signal of the gate 7a. A four-man power AND gate 7b which receives the inverted signal of the shift register 4, a two-man power AND gate 7c which receives the inverted signal of the output of the shift register 4, and an inversion of the QA ratio output QB of the shift register 5. It consists of a two-man AND gate 7d which receives a signal as input, an OR gate 7e which takes the logical sum of the outputs of the gates 7a and 7b, and an OR gate 7f which takes the logical sum of the outputs of the gates 7c and 7d and the flip-flop 8.

The RS flip-flop 8 is used to flag out-of-synchronization, and uses the output of gate 6d as a cent input and the output of gate 7e as a reset input.The Q output is out of synchronization, and the -G- output is synchronization establishment. There is.

The AND signal of the OR signal of the output of the frame pulse detection circuit 2.3 and the inverted signal of the output of the gate 7f is input to the CLR terminal of the frame counter l, and the AND signal and the output of the frame counter 1 are inputted. A logical OR signal with the CRY terminal output is applied to the enable terminal of the shift register 4.5. Also, frame counter 1. shift register 4
．． A clock signal 5 is provided with a clock signal that is bit synchronized with the input data.

The operation of the frame protection circuit having such a configuration will be explained next.

Frame pulse patterns F+ and Fz are detected by frame pulse detection circuits 2 and 3, respectively, and pattern match/mismatch information at the frame pulse insertion timing is shifted into shift registers 4 and 5, respectively.

When frame synchronization is achieved, frame pulse patterns F1 and F2 are detected alternately at the phase of the frame pulse insertion timing. Therefore, data "101" or "010" is stored in the shift registers 4 and 5. Therefore, the gates 6a and 6b of the forward protection end determination circuit 6.

Since the output of each gate 6c becomes "0°" and the output of the gate 6d remains "O", the RS flip-flop 8
There is no set input for .

On the other hand, in the out-of-frame synchronization state (excluding the case of false synchronization), since neither pattern F nor F2 match at the frame pulse insertion timing, neither of the shift registers 4.5 has "'000"'. is accumulated,
A signal to set the RS flip-flop 8 is issued from the forward protection end determination circuit 6, and an out-of-synchronization flag is set.

In the embodiment, the case where there is no match with either frame pulse patterns F+ or F2 in one pattern matching is referred to as 1.
The forward protection function of this embodiment is equivalent to a three-stage forward protection function of the reset counting type, since the forward protection is terminated when the number of mismatches occurs three times in a row.

In an erroneous synchronization state caused by fixed data having the same value as one pattern of frame pulses, only one of patterns F+ and F2 matches continuously at the frame pulse insertion timing. Therefore, since "111" is accumulated in either one of the shift registers 4.5, the forward protection end determination circuit 6 determines that there is an erroneous synchronization, and a signal is issued to set the RS flip-flop 8. Similarly, an out-of-sync flag is raised.

Next, the operation of backward protection when recovering synchronization from an out-of-synchronization state will be explained. First, a pattern match signal output from the frame pulse detection circuit 2.3 performs a hunting operation to reset the frame counter 1, and at the same time, the frame pulse detection circuit 2.3 is sent to the shift register 4.5.
takes in the output of and enters backward protection operation. In this example,
If patterns F and F2 are detected alternately from the results of the first two information captures, including the capture of output information from the frame pulse detection circuits 2 and 3 during hunting (that is, the shift register 4 .5 “QA, Q
," when the output is "10" or "01"),
An RS flip-flop 8 heliset signal is output from the gate 7e of the rear protection completion determination circuit 7, and a flag indicating the establishment of synchronization is set. In this embodiment, backward protection is performed when one pattern matching of frame pulses matches either F or F2 two times in a row, and the matches alternate between F, F2. finish. In other words, the rear protection function of this embodiment is equivalent to a two-stage rear protection function of reset counting type. If fixed data equal to either frame pulse pattern F+ or Fz is mistakenly hunted during the first hunting stage, the same pattern as during hunting will be continuously detected during pattern matching in the next frame pulse insertion phase. Therefore, the outputs “QA, Q,” of shift registers 4 and 5 are “1.0”
It is not. Therefore, since the output of the gate 7f remains at "0", the backward protection does not end and the hunting operation returns again, and false synchronization does not occur.

Although the embodiment has been described for the case where n=2, the present invention is not limited to this, and it goes without saying that it can also be applied to the case where n>2. In this case, the number of frame pulse detection circuits and shift registers may be increased by the number n, and the internal logic configurations of the forward and backward protection end determination circuits may be changed accordingly. Furthermore, the number of protection stages can be changed by changing the number of bacterial species stages of the shift register and the internal logic configuration of the backward protection end determination circuit.

〔Effect of the invention〕

According to the present invention, in a frame protection circuit that detects frame pulses in which n types of patterns alternate and protects the frame, it is possible to detect frame pulses by detecting and matching patterns n times as in the conventional method. , compared to the method that counts mismatches as one time, since one frame pulse pattern detection and matching result counts a match or mismatch of frame pulses as one time, the forward protection time and backward protection time can be reduced to 1/n. It is also possible to detect frame synchronization errors caused by fixed data.

[Brief explanation of the drawing]

The figure is a configuration diagram of a frame protection circuit according to an embodiment of the present invention. 1... Frame counter, 2, 3... Frame pulse detection circuit, 4.5... Shift register, 6... Forward protection end determination circuit, 7... Backward protection end determination circuit,
8...RS flip-flop.

Claims (1)

[Claims] In a frame protection circuit that protects frame synchronization by detecting frame pulses in which 1, n (≧2) types of frame patterns alternate, the frame protection circuit detects the frame pulses at the frame pulse insertion position and collects pattern match/mismatch information and pattern match/mismatch information. frame pulse detection means for outputting information indicating the type; storage means for sequentially storing a specified number of output values of the frame pulse detection means; and determination of termination of forward protection and termination of backward protection from the specified number of information. A frame protection circuit comprising: determination means for performing the following.