JPS63151211A - Pulse width modulator - Google Patents

Abstract

PURPOSE:To adjust the intermediate tone density in a uniform stage by adding a programmable clock generator newly so as to adjust the adjusting ratio of a modulation pulse width in response to each laser beam printer. CONSTITUTION:A programmable clock generator 700 and a code converter 400 to adjust the pulse width to be modulated around the predetermined timewise center position are provided in addition. A count clock (f) generated from a generator 700 is subjected to change freely for its period depending on the setting of set information FDATA to a dip switch 720. As a result, in using a frequency f2 as the frequency (f) shown in figure, the output C of the converter 400 is not divided equally timewise and the timewise ratio of pulse width adjustment of pulse width modulation in an output (i) of a glitch elimination circuit 500 varies with the period of (f). Thus, the frequency f2 is inputted as the count clock (f) of the pulse width modulator to adjust the modulation pulse width in the programmed width.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a pulse width modulator used for forming a laser modulation signal for a laser beam printer.

[Prior Art] In a conventional laser beam printer, in order to record a halftone image, a laser beam modulation signal is pulse width modulated to control the recording time of one pixel.

A block diagram of this conventional pulse width modulator is shown in FIG. In FIG. 2, 100 is a timing matching circuit, 200 is a comparator, 300 is a counter, and 500 is a glitch removal circuit.

The operation of the conventional system having the above configuration will be explained below with reference to the timing chart of FIG.

The external input code signal A is a code signal input indicating the pulse width to be modulated. Here, for ease of understanding, it is constructed from three parallel bits. In the case of 3 bits, eight types of pulse widths can be specified. However, in order to obtain halftones, for example, 64 different pulse widths are required, and in such a case, by expanding the number of parallel bits to 6 bits, s4f! +
A pulse width of 1 can be easily obtained.

Now, the input code signal A is input to the timing matching circuit 100 together with the input clock e having the period T, and the input code signal A is latched in the timing matching circuit 100 at the fall timing of the input clock e.

On the other hand, due to the counting clock f input to the counter 300, a synchronous clear signal g is sent to the counter 3 from the timing matching circuit 100 at the falling timing of the human clock e.
Output as 00. Therefore, each time the counter 300 is cleared by the synchronous clear signal g, the counter 300 starts counting up the counting clock f anew, and continues counting up until the next synchronous clear signal g is obtained. The comparator 200 constantly compares the latch output B of the input code signal A with the output of the counter 300, and outputs °゛1°' as the output while the relationship B>D is established. .

For example, in FIG. 3, when the value of B is A2, I=4, and T=6, the output changes as shown in FIG. The glitch removal circuit 500 is configured to latch the output at the falling timing of the counting clock f, so that a pulse from which the glitch has been removed can be obtained from the output signal 1.

[Problem to be Solved by the Invention 1] As explained above, conventionally, for example, eight types of pulse widths are available using a counting clock f obtained by dividing the period T of the input clock e by eight, and a manually coded signal A having a 3-bit configuration. is created, but when the output from this pulse width modulator is used as a laser drive signal to output a halftone image with a laser beam printer, a halftone image density corresponding to the laser lighting time can be obtained. There is a problem that there is no.

Furthermore, even if you use 64 types of pulse widths, you may only be able to obtain halftone image densities in more than a dozen levels, and depending on the material of the photoreceptor drum used in the laser beam printer, the same pulse width may not be obtained. Even when an image is output, there is a problem that the output halftone density varies.

[Means for Solving the Problems] The present invention solves the above-mentioned problems. For example, the increase/decrease ratio of the modulation pulse width can be adjusted according to each laser beam printer, and the halftone density in the image output is uniform. The purpose of this invention is to provide a pulse width modulator that can be increased or decreased in different stages, and the following configuration is provided as a means for achieving this purpose.

That is, the comparison means compares the output of the counting means, which is reset every fixed period and constantly counts the clock signal, with the code signal, which is updated every fixed period and instructs the pulse width to be modulated. A pulse width modulator that generates a pulse having a pulse width corresponding to a code signal as a result, a clock generating means for generating a clock signal to a counting means whose pulse train interval can be arbitrarily set, a counting means, and a comparing means. and converting means for converting the output of the counting means into another predetermined value to define the temporal center position of the pulse to be modulated between.

[Operations] In the above configuration, the temporal center position of the generated pulse is defined by the means for converting the output of the counter into a predetermined value, and the increase/decrease ratio of the modulated pulse width is determined by changing the cycle of the counting clock. It becomes possible to adjust the halftone density in the image output in equal steps.

[Example] Hereinafter, an example according to the present invention will be described with reference to the drawings. FIGS. 1 and 4 to 7 show this embodiment.

FIG. 1 is a diagram showing a schematic configuration of an embodiment according to the present invention, and the same components as in FIG. 2 are given the same numbers. As shown, the difference from that shown in FIG. 2 is that the counting clock f
is generated by the programmable clock generator 700, and its period is not constant, and by converting the output of the counter 300 into a predetermined value, the pulse width to be modulated can be centered around a predetermined temporal center position. The difference is that a code converter 400 for adjusting and subtracting the data is newly provided.

Here, the circuit operation will be explained with reference to FIG.
Assuming that the period of the counting clock f from the programmable clock generator 700 is constant, as in the previous case, the output of the counter 300 is updated at a constant period. The output is 6, 4, 2, 0, 1, 3 for each human power of 0', 1, 2, 3, 4, 5, 6.7, respectively, as shown in FIG. 4, by the coat converter 400. , 5.7 and output as a conversion output C. FIG. 5 shows a specific example of the code converter 400. In FIG. 5, D2. D
i, DO is the output of the counter 300 as input,
C2, C1, and Co are outputs of the coat converter 400 itself.

Do, Co as LSB, D2. C2 is output as MSB, and D2 is converted and output as is as CO. Also,
Dl and D are respectively c2. , cl or inverted as c2. c, and is converted and output. On the other hand, when D2 is 1°°, that is, the count value is 4 or more, Dl and Do are
C2. c, can be obtained as is by closing, and if the count value is less than 4, Dl and D2 are the inverter 410
．． 420 respectively, and the inverter 43
Nant Gate 460, 47 activated by 0
c2.
c. It can be obtained by binding.

The output C of this code converter 400 is 1 of the comparator 200.
The other human power of the comparator 200 becomes the output B of the timing matching circuit 100. Then, the comparator 200 compares the two forces, and the output h1 of the comparator 200 is the output i of the glitch removal circuit 500 as shown in FIG.

However, in this case as well, as described in the conventional example, the value of B is a;
, A = 4, and T = 6, and while the relationship B>C holds true, the output is 1''.In other words, the code converter 400 converts M (modulated pulse It has the function of adjusting the pulse width around the center (which indicates the temporal center of the pulse width).

In the case where the code converter 400 is not provided, the pulse width is adjusted by fixing one end without centering on M, as shown as output i in FIG.

The above is the operation when the period of the counting clock f, which is the output of the programmable clock generator, is constant.
FIG. 6(a) shows the configuration of an example of a programmable clock generator. According to this, the programmable clock generator 700 is an oscillation circuit 710 that generates a frequency signal F four times the frequency of the conventional counting clock f.
．． Consisting of 32 bits, “0°” when ON, “0°” when OFF.
It is composed of a dip switch 720 that outputs 1°, a shift register 730 consisting of 32 bits, and a 32-ary up counter 740 that outputs a ripple carryout signal RCO at time-up. shift register 7
30 constantly executes shift processing using the clock F from the oscillation circuit 710, and outputs a counting clock f as a shift output. At the same time, the clock F is counted by a counter 740, and when an overflow occurs, a ripple carry-out signal RCO is outputted, and is automatically cleared to start counting again. Since the RCO interacts with the load signal, the shift register 730 loads the setting information FDATA from the dip switch 720, and after loading, continues shifting from the MSB (most significant bit) side. In the end, shift register 73
Setting information FDA is set to 0 at a cycle equivalent to 32 clocks F.
TA is preset, and after presetting, the setting information FDA
TA is sequentially shifted out at the cycle of clock F.

Therefore, in order to obtain a lock like the counting clock f in FIG. 4, [11001100
. . 1100, and as shown in FIG. 6(b), the clock indicated by fl will be output from the shift register 730. Also, if [1111000010101100...] is set as FDATA, the shift register 730 will output a clock indicated by f2. In other words, the period of the counting clock f shown in FIG. 1 can be freely changed depending on the setting of the setting information FDATA for the ditub switch 720.

As a result, as shown in FIG. 7, if <f2 is used as f,
Since the output C of the code converter 400 is no longer equally divided in time, the temporal ratio of increase/decrease in pulse width of the pulse width modulation of the output i of the glitch removal circuit 500 also changes according to the period of f. In this way, by manually using f2 as the counting clock f of the pulse width modulator, the modulation pulse width can be increased or decreased by a programmed width, compared to the conventional example in which the modulation pulse width is increased or decreased by a constant width.

In the above embodiments, the configuration was explained using 3 bits so that the explanation could be easily understood, but it may also be configured using 6 bits, and the number of bits is not particularly limited. The number of bits of the programmable clock generator is not limited to 32 bits either.

Also, convert the digital switch to ROM or RAM,
Set the cycle information of the counting clock for multiple seeds,
The switching may be performed later according to arbitrary conditions using an external device, a central processing unit, a microprocessor, or the like. In some cases, it is of course possible to make this switching possible using an operation panel or the like so that the user can set the halftone.

As explained above, according to this embodiment, by adding the programmable clock generator, the period of the output clock of the programmable clock generator can be adjusted in the region where halftones can be resolved in the laser beam printer. The output clock period of the programmable crotter generator is slowed down in areas where halftones are difficult to resolve, and the modulation pulse width is roughly divided. The pulse width increase/decrease ratio can be adjusted according to each laser beam printer, and the halftone density in the image output is increased/decreased in uniform steps.

[Effects of the Invention] As explained above, according to the present invention, the increase/decrease ratio of the modulation pulse width can be adjusted according to each laser beam printer, and the halftone density in image output can be increased/decreased in uniform steps. Ru.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a general configuration of an embodiment according to the present invention, FIGS. 2 and 3 are diagrams for explaining the configuration and operation of a pulse width modulator according to the prior art, and FIG. A diagram for explaining the operation when the counting clock period of this embodiment is constant. FIG. 5 is a diagram showing the specific configuration of the code converter of this embodiment. FIGS. 6 (a) and (b) 7 is a diagram for explaining the configuration and operation of the programmable crotter generator of this embodiment, and FIG. 7 is a diagram for explaining the operation of the pulse width modulator of this embodiment. In the figure, 100...timing matching circuit, 200...
Comparator, 300...Counter, 400...Code converter, 500...Glitch removal circuit, 700...Programmable clock generator. Patent applicant Canon Co., Ltd.]

Claims (1)

[Claims] The comparison means compares the output of the counting means, which is reset every fixed period and constantly counts the clock signal, with the code signal, which is updated every fixed period and instructs the pulse width to be modulated. a pulse width modulator that generates a pulse having a pulse width corresponding to the code signal; a clock generating means that generates a clock signal to the counting means, the pulse train interval of which can be arbitrarily set; A pulse width modulator, comprising: a converting means for converting the output of the counting means into another predetermined value in order to define the temporal center position of the pulse to be modulated between the comparing means and the pulse width modulator.