JPS63151052U - - Google Patents
Info
- Publication number
- JPS63151052U JPS63151052U JP4473387U JP4473387U JPS63151052U JP S63151052 U JPS63151052 U JP S63151052U JP 4473387 U JP4473387 U JP 4473387U JP 4473387 U JP4473387 U JP 4473387U JP S63151052 U JPS63151052 U JP S63151052U
- Authority
- JP
- Japan
- Prior art keywords
- bus
- parallel
- printed circuit
- circuit board
- communication
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Information Transfer Systems (AREA)
- Small-Scale Networks (AREA)
- Communication Control (AREA)
Description
図は、本考案の一実施例を示す構成ブロツク図
である。
The figure is a block diagram showing an embodiment of the present invention.
Claims (1)
を伝送するパラレルバス、 このパラレルバスに接続されるプリント基板、 当該パラレルバスの通信を管理して他のプリン
ト基板と通信するバスマスタ基板、 とよりなるパラレルバスシステムにおいて、 前記パラレルバスと並列に設けられたバス通信
仕様線、 このバス通信仕様線と接続される各プリント基
板毎に設けられたバス仕様制御器、 アクセスするプリント基板に固有のバス仕様を
当該バス通信仕様線に出力する前記バスマスタ基
板に設けられたバス通信仕様マスタ、 とを具備し、 アクセスするプリント基板に応じてバス通信仕
様線に通信の仕様を出力して前記パラレルバスの
通信仕様を変更すること、 を特徴とするパラレルバスの多重化装置。[Claim for Utility Model Registration] A parallel bus that transmits address signals, data signals, and control signals, a printed circuit board connected to this parallel bus, and a bus master board that manages communications on the parallel bus and communicates with other printed circuit boards. , in a parallel bus system consisting of a bus communication specification line provided in parallel with the parallel bus, a bus specification controller provided for each printed circuit board connected to this bus communication specification line, and a printed circuit board to be accessed. a bus communication specification master provided on the bus master board that outputs a unique bus specification to the bus communication specification line, and outputs communication specifications to the bus communication specification line according to the printed circuit board to be accessed, and A parallel bus multiplexing device characterized by: changing communication specifications of the parallel bus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4473387U JPS63151052U (en) | 1987-03-26 | 1987-03-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4473387U JPS63151052U (en) | 1987-03-26 | 1987-03-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63151052U true JPS63151052U (en) | 1988-10-04 |
Family
ID=30862819
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4473387U Pending JPS63151052U (en) | 1987-03-26 | 1987-03-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63151052U (en) |
-
1987
- 1987-03-26 JP JP4473387U patent/JPS63151052U/ja active Pending
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