JPS63148696A - Electronic circuit substrate - Google Patents
Electronic circuit substrateInfo
- Publication number
- JPS63148696A JPS63148696A JP29484286A JP29484286A JPS63148696A JP S63148696 A JPS63148696 A JP S63148696A JP 29484286 A JP29484286 A JP 29484286A JP 29484286 A JP29484286 A JP 29484286A JP S63148696 A JPS63148696 A JP S63148696A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- plating
- electronic circuit
- film layer
- conductor pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims description 13
- 239000010409 thin film Substances 0.000 claims description 32
- 238000007747 plating Methods 0.000 claims description 21
- 238000000034 method Methods 0.000 claims description 18
- 229910052759 nickel Inorganic materials 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 4
- 239000012212 insulator Substances 0.000 claims description 3
- 239000004020 conductor Substances 0.000 description 17
- 229910052751 metal Inorganic materials 0.000 description 16
- 239000002184 metal Substances 0.000 description 16
- 229920002120 photoresistant polymer Polymers 0.000 description 11
- 238000004519 manufacturing process Methods 0.000 description 7
- 229910045601 alloy Inorganic materials 0.000 description 6
- 239000000956 alloy Substances 0.000 description 6
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 6
- 239000000919 ceramic Substances 0.000 description 6
- 229910052804 chromium Inorganic materials 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 239000010408 film Substances 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 238000007740 vapor deposition Methods 0.000 description 3
- 229910000990 Ni alloy Inorganic materials 0.000 description 2
- ROOXNKNUYICQNP-UHFFFAOYSA-N ammonium persulfate Chemical compound [NH4+].[NH4+].[O-]S(=O)(=O)OOS([O-])(=O)=O ROOXNKNUYICQNP-UHFFFAOYSA-N 0.000 description 2
- 241001164374 Calyx Species 0.000 description 1
- 229910000531 Co alloy Inorganic materials 0.000 description 1
- 229910020220 Pb—Sn Inorganic materials 0.000 description 1
- 229910001870 ammonium persulfate Inorganic materials 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 239000010953 base metal Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は電子回路基板に係り、信頼性、耐湿性と耐熱疲
労性にすぐれ、かつ、低コストで簡単な構造の電子回路
基板の１１造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an electronic circuit board, and relates to an electronic circuit board having excellent reliability, moisture resistance and thermal fatigue resistance, low cost, and simple structure. Regarding the method.
第２図（ａ）から（ｄ）は従来の電子回路基板を製造す
る工程段階を示す図である。基板１にはアルミナセラミ
ックス、ガラスなどの絶縁体あるいはＳｉなどの半導体
が一般に使用される。基板１上に蒸着、あるいは、スパ
ッタリング法などの、いわゆる、薄膜法により第一の金
属薄膜層２を形成し、真空を破らずに引きつづき、第二
の金属薄膜層３をめっきの下地層として形成する（第２
図（ａ））、通常、第一の金属薄膜層２は基板１として
使用されるアルミナセラミックス、ガラスな）どの絶縁
体、あるいは、Ｓｉなどの半導体と比較的、熱膨始係数
の値が近いために良好な密着力をもち、かつ、容易にエ
ツチングができるのでＣｒあるいはＴｉが用いられ、ま
た、第二の金属薄膜層３は後の工程で第三層にＡｕめっ
きするための下地として使用され、Ａｕとの密着力、さ
らには、第一の金属薄膜層２との密着力にすぐれ、かつ
、容易にエツチングできることがらＣｕあるいはＮｉが
用いられている（特開昭５２−１３１１５９号公報）次
に第二の金属薄膜３上をフォトレジスト４で覆い、フォ
トマスクを通して露光し、現像を行い、導体パターンと
なるべき所にフォトレジストパターン４を形成する（第
２図（ｂ））、次に、エツチング液でフォトレジストパ
ターン４の下部以外の第二の金属薄膜層３を選択的に除
去し、つづいて同様にエツチング液で第一の金属薄膜層
２を選択的に除去し、適当なばくり剤でフォトレジスト
４を除去して薄膜導体パターンを形成する（第２図（Ｃ
））・
次に第二の金属薄膜層３上に所望の厚さだけの−Ａｕめ
つき層５を設け、導体パターンを形成する（第２図（ｄ
））。FIGS. 2(a) to 2(d) are diagrams showing process steps for manufacturing a conventional electronic circuit board. For the substrate 1, an insulator such as alumina ceramics or glass, or a semiconductor such as Si is generally used. A first metal thin film layer 2 is formed on the substrate 1 by a so-called thin film method such as vapor deposition or sputtering, and the second metal thin film layer 3 is formed as a base layer for plating by continuing without breaking the vacuum. form (second
In Figure (a)), the first metal thin film layer 2 usually has a coefficient of thermal expansion relatively close to that of the insulator such as alumina ceramics or glass used as the substrate 1, or the semiconductor such as Si. Cr or Ti is used because it has good adhesion and can be easily etched, and the second metal thin film layer 3 is used as a base for Au plating on the third layer in a later step. Cu or Ni is used because it has excellent adhesion to Au and further to the first metal thin film layer 2, and can be easily etched (Japanese Patent Application Laid-Open No. 131159/1982). Next, the second metal thin film 3 is covered with a photoresist 4, exposed through a photomask, and developed to form a photoresist pattern 4 where the conductor pattern is to be formed (FIG. 2(b)). Next, the second metal thin film layer 3 other than the lower part of the photoresist pattern 4 is selectively removed using an etching solution, and then the first metal thin film layer 2 is similarly selectively removed using an etching solution. The photoresist 4 is removed using a stripping agent to form a thin film conductor pattern (see Figure 2 (C).
)) Next, a -Au plating layer 5 of a desired thickness is provided on the second metal thin film layer 3, and a conductor pattern is formed (see Fig. 2(d)).
)).
１）第一の金属薄膜層に用にられるＣｒあるいはＴｉは
Ａｕめつき膜に対して極めて密着力が弱く、またＡｕめ
つきがされ難い、このため、導体パターンへ水分が吸着
すると露出したＣｒあるいはＴｉとＡｕめつき膜の界面
では、電気化学的に卑な金属であるＣｒあるいはＴｉが
選択的に腐食され、導体パターンが基板より剥がれると
いう問題がある。1) Cr or Ti used for the first metal thin film layer has extremely weak adhesion to the Au plating film and is difficult to be plated with Au. Therefore, when moisture is adsorbed to the conductor pattern, the exposed Cr Alternatively, there is a problem that Cr or Ti, which are electrochemically base metals, are selectively corroded at the interface between the Ti and Au plating films, and the conductor pattern is peeled off from the substrate.
２）導体パターンが多層構造であるため膜応力が大きい
こと、さらに、熱膨張係数の異なる金属を多く用いて積
層しているため耐熱疲労性に劣ることなどの問題がある
。2) Since the conductor pattern has a multilayer structure, there are problems such as large film stress and poor thermal fatigue resistance because many metals with different coefficients of thermal expansion are laminated.
３）薄膜導体パターンが二層構造であるために薄膜形成
、エツチングなどの工程数が増え、これにより製作歩溜
りが低下し、基板のコストが高くなる。3) Since the thin film conductor pattern has a two-layer structure, the number of steps such as thin film formation and etching increases, which reduces the manufacturing yield and increases the cost of the substrate.
本発明の目的は、量産性、コスト性にすぐれ。The object of the present invention is to achieve excellent mass productivity and cost efficiency.
かつ信頼性にすぐれた電子回路基板の製造方法を提供す
ることにある。Another object of the present invention is to provide a method for manufacturing an electronic circuit board that is also highly reliable.
Ｃ問題点を解決するための手段〕
上記問題点は、めっき膜の下地となる金属薄膜層として
Ｆｅ、Ｎｉ、Ｃｏの中の少なくとも二種以上を含む金属
を用いることにより解決できる。Means for Solving Problem C] The above problem can be solved by using a metal containing at least two or more of Fe, Ni, and Co as the metal thin film layer serving as the base of the plating film.
本発明による導体パターン構造ではめっきの下地となる
薄膜導体パターンが完全にＡｕめっきで覆われるため、
導体パターンの水分が吸着しても下地の薄膜導体パター
ンが水分に触れることなく導体パターンが腐食により基
板より剥がれることはない。さらに導体パターンへ熱サ
イクルなどを生じても殆ど導体パターンが剥がれること
もない。In the conductor pattern structure according to the present invention, the thin film conductor pattern that serves as the base for plating is completely covered with Au plating.
Even if moisture is adsorbed on the conductor pattern, the underlying thin film conductor pattern will not come into contact with the moisture, and the conductor pattern will not peel off from the substrate due to corrosion. Furthermore, even if the conductor pattern is subjected to thermal cycles, the conductor pattern hardly peels off.
以下、図面を参照して本発明の一実施例について説明す
る。第１図（ａ）から（ｄ）は本発明による電子回路基
板を製造する工程の段階を示す一実施例である。まず、
基板１０は、一般に、アルミナセラミックスが使用され
る。基板１ｏ上に蒸着、あるいは、スパッタリング法の
、いわゆる、薄膜法により第一の金属薄膜層として重量
比でＦｅ５８％−Ｎｉ４２％合金薄膜層２０を形成する
（第１図（ａ））。この合金薄膜層は熱膨張係数が４．
４Ｘ１０″″６／”Ｃであり、アルミナセラミックスの
熱膨張係数６Ｘ１０″″８ ／ ”Ｃと値が比較的近く
、このため、アルミナセラミックスと極めて良好な密着
力をもち、また、容易にエツチングができること、さら
に、後の工程で第二層にＡｕめつきをするための下地層
として使用され、かつ、Ａｕとの密着力が良好であるこ
とから用いている。An embodiment of the present invention will be described below with reference to the drawings. FIGS. 1(a) to 1(d) show an embodiment of the process of manufacturing an electronic circuit board according to the present invention. first,
The substrate 10 is generally made of alumina ceramics. A 58% Fe-42% Ni alloy thin film layer 20 by weight is formed as a first metal thin film layer on the substrate 1o by vapor deposition or sputtering, a so-called thin film method (FIG. 1(a)). This alloy thin film layer has a coefficient of thermal expansion of 4.
The coefficient of thermal expansion is 4X10''6/''C, which is relatively close to the coefficient of thermal expansion of alumina ceramics, 6X10''''8/''C. Therefore, it has extremely good adhesion to alumina ceramics, and is easily etched. It is used because it can be used as a base layer for plating the second layer with Au in a later step, and because it has good adhesion to Au.
次にＦｅ５８％−Ｎ ｉ ４２５合金薄膜層２０上にフ
ォトレジスト４０を覆い、これをフォトマスクを通して
露光し、現像を行い、導体パターンとなるべき所にフォ
トレジストパターン４０を形成する（第１図（ｂ））、
このフォトレジストは、例えば、０ＦＰＲ（商標名）の
ようなポジ型のものがネガ型に比べて切れ良くエツチン
グすることができ高精度のパターンが得られることから
好ましく、さらに、現像後、０λプラズマ法を用いてフ
ォトレジストの灰化処理を行えば、より高精度のパター
ンが得られる。Next, a photoresist 40 is covered on the Fe58%-Ni425 alloy thin film layer 20, exposed through a photomask, and developed to form a photoresist pattern 40 in the place where the conductor pattern is to be formed (see Fig. 1). (b)),
For example, a positive photoresist such as 0FPR (trade name) is preferable because it can be etched more sharply than a negative photoresist and a highly accurate pattern can be obtained. If the photoresist is ashed using this method, a pattern with higher precision can be obtained.
次に、過硫酸アンモニウム系の水溶液を用いて、フォト
レジストパターン４０下部以外の露出したＦｅ５８％−
Ｎｉ４２％合金薄膜層２０をエツチングして除去し、つ
づいて適当なはくり剤でフォトレジストパターン４０を
除去し、薄膜導体パターン２０を形成する（第１図（Ｃ
））。この場合のエツチング方法はエツチング液を用い
た化学工ツチング法の他にプラズマエツチング、イオン
ビームエツチング、スパッタエツチングなどの手法も利
用できる６次に、薄膜導体パターン２０上に所望の厚さ
だけＡｕめつき層５０を設ける（第１図（ｄ））、通常
、Ａｕめつきはその物理的特性。Next, using an ammonium persulfate-based aqueous solution, 58% of the exposed Fe other than the lower part of the photoresist pattern 40 is
The Ni 42% alloy thin film layer 20 is etched and removed, and then the photoresist pattern 40 is removed using a suitable stripper to form a thin film conductor pattern 20 (see FIG. 1(C)).
)). In this case, in addition to the chemical etching method using an etching solution, plasma etching, ion beam etching, sputter etching, etc. can also be used. A plating layer 50 is provided (FIG. 1(d)), usually Au plating is a physical property thereof.
ボンディング性などに優れることから主に電子。Mainly electronic because of its excellent bonding properties.
電気工業部品に多用されている。また、Ａｕをめっき法
により設けるのは高価なＡｕを無駄なく能率的に使用し
、かつ、めっき法は蒸着法やスパッタリング法などの薄
膜法に比べて、はるかに高速で厚いＡｕめつき層を設け
ることができるからであり、手法として化学めっき法、
電気めっき法が利用できる。かくしてＦｅ５８％−Ｎｉ
４２％合金薄膜層とＡｕめつき層とからなる導体パター
ンが完成する。Widely used in electrical industrial parts. In addition, providing Au by plating allows efficient use of expensive Au without wasting it, and the plating method can form a thick Au plating layer much faster than thin film methods such as vapor deposition or sputtering. This is because it can be applied, and the methods include chemical plating,
Electroplating methods are available. Thus Fe58%-Ni
A conductor pattern consisting of a 42% alloy thin film layer and an Au plating layer is completed.
本実施例の説明では、Ａｕめつきのための下地層として
Ｆｅ５８％−Ｎｉ４２％合金を用いた場合について説明
したが、アルミナセラミックス。In the description of this example, a case was explained in which a 58% Fe-42% Ni alloy was used as the base layer for Au plating, but alumina ceramics.
ガラスなどの絶縁体基板、あるいは、Ｓｉなどの半導体
基板と比較的に近い熱膨張係数をもち、エツチングが容
易にできて、かつ、めっきが可能な金属１例えば、Ｆｅ
５０％−Ｎｉ８０％合金。A metal that has a coefficient of thermal expansion relatively close to that of an insulating substrate such as glass or a semiconductor substrate such as Si, can be easily etched, and can be plated.
50%-Ni80% alloy.
Ｆｅ５４％−Ｎｉ２９％−Ｃｏ１７％合金等を使用して
も同様な効果が得られることはいうまでもなく、また、
めっき層はＡｕ以外の金属１例えば。It goes without saying that similar effects can be obtained by using 54% Fe-29% Ni-17% Co alloy, etc.
The plating layer is made of a metal other than Au, for example.
Ａｇ、Ｎｉ、Ｃｕ、Ｃｒ、Ｐｄ、Ｓｎ、Ｐｂ−Ｓｎ合金
も適用できることもいうまでもない。Needless to say, Ag, Ni, Cu, Cr, Pd, Sn, and Pb-Sn alloys can also be applied.
本発明によれば、構造が簡単で、しかも、製造工程の時
間が短縮できるため、低価格で、かつ、高信頼性の電子
回路基板が得られる。According to the present invention, since the structure is simple and the manufacturing process time can be shortened, a low-cost and highly reliable electronic circuit board can be obtained.
第１図は本発明の一実施例の電子回路基板を製造する工
程段階を示す拡大断面図、第２図は従来の方法による電
子回路基板を製造する工程段階を示す拡大断面図である
。
１．１０・・・基板、２・・・Ｃｒ、Ｔｉ薄膜層、３・
・・Ｃｕ、Ｎｉ薄膜層、４．４０−・・フオレジスト、
５゜５０− Ａ ｕめつき層、２０＝Ｆｓ５８％−Ｎｉ
萼１図
（眞）
（ｌｏ）
（ｉ）
第２図
（久）
（Ｃ）
（勺FIG. 1 is an enlarged cross-sectional view showing the process steps of manufacturing an electronic circuit board according to an embodiment of the present invention, and FIG. 2 is an enlarged cross-sectional view showing the process steps of manufacturing an electronic circuit board according to a conventional method. 1.10... Substrate, 2... Cr, Ti thin film layer, 3...
...Cu, Ni thin film layer, 4.40-...phoresist,
5゜50-Au plating layer, 20=Fs58%-Ni
Calyx 1 (Shin) (lo) (i) Fig. 2 (ku) (C) (勺
Claims (1)
およびめつき法により製造された電子回路基板において
、 前記めつき法の下地となる前記薄膜法による薄膜層とし
てＦｅ、Ｎｉ、Ｃｏの中の少なくとも一種以上を含む金
属からなることを特徴とする電子回路基板。 ２、特許請求の範囲第１項において、 前記薄膜層の熱膨張率の範囲は２〜１５× １０＾−＾６／℃であることを特徴とする電子回路基板
。[Scope of Claims] 1. In an electronic circuit board manufactured by a thin film method and a plating method on a substrate made of an insulator or a semiconductor, Fe is used as a thin film layer formed by the thin film method as a base for the plating method. , Ni, and Co. 2. The electronic circuit board according to claim 1, wherein the thin film layer has a coefficient of thermal expansion in a range of 2 to 15×10^-^6/°C.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29484286A JPS63148696A (en) | 1986-12-12 | 1986-12-12 | Electronic circuit substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29484286A JPS63148696A (en) | 1986-12-12 | 1986-12-12 | Electronic circuit substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63148696A true JPS63148696A (en) | 1988-06-21 |
Family
ID=17812958
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29484286A Pending JPS63148696A (en) | 1986-12-12 | 1986-12-12 | Electronic circuit substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63148696A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11330652A (en) * | 1997-06-10 | 1999-11-30 | Canon Inc | Board and manufacture thereof |
-
1986
- 1986-12-12 JP JP29484286A patent/JPS63148696A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11330652A (en) * | 1997-06-10 | 1999-11-30 | Canon Inc | Board and manufacture thereof |
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