JPS63147229A - Microprogram controller - Google Patents

Abstract

PURPOSE:To decrease the number of steps when a physical address is produced by using an all-0 detecting circuit to whether the low-order N bits in a base address set at a base address register are equal to all-0 or not. CONSTITUTION:An all=0 detecting circuit 6 detects that the low-order N bits of a base address stored in a base address register 3 are equal to all-0. In such a case, the contents of physical address register 5 which are obtained from merging are defined as a desired physical address. If it is decided that low-order N bit are not equal to all-0, the result of addition of an adder 7 is stored in the register 5 as a desired physical address. As a result, the coincidence is secured between the output of the adder 7 and the data to be set at the register 5 if said low-order N bit are equal to all-0. Thus no addition arithmetic is needed when the low-order bits of the base address are equal to all-0 and therefore the processing speed is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microprogram control device, and particularly to a microprogram control device that can speed up the generation of physical addresses.

[Conventional technology]

A conventional microprogram control device that generates a physical address from a base address and an offset address is configured to always perform an addition operation between the base address and the offset address when determining the physical address.

[Problem that the invention seeks to solve]

As mentioned above, when a conventional microprogram control device generates a physical address, it always performs an addition operation between a base address and an offset address.
Furthermore, since address calculations for determining physical addresses are frequently performed in microprogram control devices, there is a problem in that the overhead caused by the addition step becomes large.

[Means for solving problems]

In order to solve the above-mentioned problems, the present invention provides a microprogram control device configured to generate a physical address from a base address and an offset address, which includes: a base address register in which the base address is stored; an offset address register in which the offset address is stored; a physical address register in which the physical address is stored; and a combination of the lower N bits of the base address stored in the base address register and the offset address stored in the offset address register. an adder that adds the base address and the offset address with the upper N bits having the same weight; and an adder that adds the base address and the offset address with the upper N bits having the same weight, and the lower N bits of the base address set in the base address register are all "0". an all-zero detection circuit for detecting whether there is an offset address, and when storing an offset address in the offset address register, the contents of the base address other than the lower N bits of the base address stored in the base address register and the The content merged with the offset address stored in the offset address register is stored in the physical address register, and the all-zero detection circuit detects that the lower N bits of the base address stored in the base address register are all ``0''. If it is detected that the content of the physical address register obtained by the above merging is the target physical address, and if it is detected that it is not all "0", then the addition result of the adder is used as the target physical address. The physical address register is configured to be stored as an address in the physical address register.

[For production]

If the lower N pintos of the base address are all “O”,
The output of the adder and the data sent to the physical address register will be equal. Therefore, when the lower N bits of the base address are all "0", there is no need to perform an addition operation, making it possible to improve the processing speed.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, in which a control unit 1 controls each part of the device according to a horizontal microprogram.
, a register file 2 in which base addresses and offset addresses are stored, a base address register 3 with a 16-hint width, an offset address register 4 with a 16-bit width, and a physical address register 5 with a 24-bit width.
, an all-zero detection circuit 6 that detects whether the data set in the lower 8 bits of the base address register 3 are all "O"s, an adder 7 for calculating the physical address, and the base address register 3. A selector 8 selects either the data set in the upper 8 bits of the adder 7 or the upper 8 bits of the output data of the adder 7, and the 16-bit offset address output from the register file 2 is added. 2 is a diagram showing a method for calculating a physical address by the adder 7. A physical address 23 having a 24-bit structure is obtained by adding the base address 21 shifted to the left by 8 bits and an offset address 22 having a 16-bit structure. That is, the physical address 23 is generated by adding the base address 21 and the offset address 22 with the lower 8 bits of the base address 21 and the upper 8 bits of the offset address 22 having the same weight.

FIG. 3 is a flowchart showing the processing content of the control unit 1 when determining a physical address from a base address and an offset address, and the operation will be explained below with reference to the same figure.

First, as shown in the step labeled ADR1 in FIG. 3, the 16-bit wide base address stored in the register file 2 is loaded into the base address register 3 under the control of the control section 1.

Next, as shown in the step labeled ADR2, the 16-bit width offset address stored in register file 2 is loaded into offset address register 4, and the data set in the upper 8 bits of base address register 3 is loaded. The process of writing to the upper 8 bits of the physical address register 5 via the selector 8 and setting the 16-bit width offset address to be set in the offset address register 4 to the lower 16 bits of the physical address register 5 via the selector 9. Processing occurs simultaneously. In addition, a conditional branch based on the detection result of the all-zero detection circuit 6 is specified in the sequence control field of the horizontal microprogram that executes the above processing, and the all-zero detection circuit 6 writes the branch to the base address register 3. If it is not detected that the lower 8 bits of the base address are all "0", execute the step of label ADR3 and then proceed to the next step. If so, proceed to the next step immediately.

That is, as mentioned above, the physical address is obtained by shifting the base address by 8 bits to the left and adding the offset. If the lower 8 bits of the base address are all 'Os', then the upper The 24-bit data obtained by merging 8 bits and the 16-bit wide offset address and the physical address obtained by adding are equal. In other words, the data stored in the physical address register 5 in the step of label ADR2 becomes the physical address as is.

Also, if the lower 8 bits of the base address are not all "0", as shown in the step of label ADR3,
The control unit 1 causes the adder 7 to add the base address shifted by 8 bits and the offset address,
The addition result is set in the physical address register 5 via the selector 8.9.

As described above, according to this embodiment, the conventional device performs three steps: loading the base address into the base address register, loading the offset address into the offset address register, and adding the base address and the offset address. Generating a physical address, which always required one step, can now be performed in two steps when the lower 8 bits of the base address are all "0".

〔Effect of the invention〕

As explained above, in the present invention, the part of the base address where the offset address and addition are performed are all "
A detection circuit is provided to detect whether the base address and the offset address are 0", and the case where the step of adding the base address and the offset address can be omitted can be determined. Therefore, the base address and the offset address are always added. This has the effect of reducing the number of steps required to generate a physical address, compared to the conventional example.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a diagram showing a physical address calculation method, and FIG. 3 is a diagram showing processing contents of the control unit 1. In the figure, 1...Control unit, 2...Register file, 3...Base address register, 4...Offset address register, 5...Physical address register, 6...All zero detection Circuit, 7... Adder, 8.9
···selector.

Claims (1)

[Claims] A microprogram control device configured to generate a physical address from a base address and an offset address, comprising: a base address register in which the base address is stored; and a base address register in which the offset address is stored. an offset address register, a physical address register in which the physical address is stored, and the lower N bits of the base address stored in the base address register and the upper N bits of the offset address stored in the offset address register are the same. an adder that adds the base address and the offset address as weighted bits; and an adder that detects whether the lower N bits of the base address set in the base address register are all "0". and a zero detection circuit, when storing an offset address in the offset address register, the contents of the base address stored in the base address register other than the lower N bits and the offset address stored in the offset address register are The merged contents are stored in the physical address register, and if the all-zero detection circuit detects that the lower N bits of the base address stored in the base address register are all "0", the merged contents are stored in the physical address register. The content of the physical address register obtained by the above is set as the target physical address, and if it is detected that it is not all "0", the addition result of the adder is stored in the physical address register as the target physical address. A microprogram control device comprising: