JPS63146614A - Drain current detection circuit for field effect transistor - Google Patents

Abstract

PURPOSE:To improve the detection accuracy through the elimination of induced noise and reduction of heat and power loss by providing a comparison means detecting a drain voltage and comparing it with a prescribed reference voltage and a drain current detection means, detecting the drain voltage and the gate voltage so as to obtain the drain current based on the detected value thereby eliminating the need for a shunt resistor. CONSTITUTION:A gate voltage VGS is detected and the turn-on state is declared by taking notice of the driven voltage VDS at turn-on changed in response to the drain current ID. Then, the drain voltage VGS is detected and the drain current ID is detected from a prescribed characteristic curve VDS-ID decided by using a gate voltage VGS and the drain voltage VDS as parameters. When the drain current ID reaches an objective drain current set based on an output voltage VOUT, the turn-off timing of a field effect TR Q1 is decided to control the drain current ID thereby varying the output voltage VOUT. Thus, a circuit insertion resistor Rs to detect the drain current ID is not required and various disadvantages caused by providing the resistor are excluded completely.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a drain current detection circuit for a field effect transistor used as a current control element in, for example, a switching regulator or a motor drive power supply.

(Prior art) In general, field effect transistors (FETs)
The output characteristics of the Effect Transistor are pre-dipolar characteristics (non-saturation region) before pinch-off.
It also shows pentode characteristics (saturation region) after pinch-off. Particularly in the triode region, it operates as a voltage-controlled resistor, and because its off-resistance to on-resistance ratio is extremely large, it functions as an excellent switching element. Also, switching.

In order to control the turn-off of an FET used as an element, conventionally the drain current (switching current) of the FET is monitored, and the gate voltage is controlled based on this monitored value to control the turn-off timing of the FET.

The conventional circuit for detecting this type of drain current is:
For example, there is one shown in FIG.

In this circuit, the source (S) of FET (Qll) and G
A shunt resistor Rs is interposed between ND, and the shunt resistor Rs
The drain current value is detected from the voltage generated across the .

(Problems to be Solved by the Invention) However, in such a conventional drain current detection circuit of a field effect transistor, a shunt resistor Rs for detection is provided in the middle of the flow path of the switching current (drain current ID). Because of this structure, there were problems as described below.

(I) Power loss proportional to the switching current occurs in the shunt resistor Rs, and furthermore, the power loss increases the temperature of the shunt resistor Rs, reducing the reliability of peripheral components.

(■) Inductive noise is generated by the inductance component LX of the shunt resistor Rs, and this noise is superimposed on the detection level and deteriorates the detection accuracy of the small signal level.

(III) Also, during the switching operation of the FET, the voltage Vs (Vs=LxX
d II, /d t) induces a shunt to the resistance Rs, reducing the switching speed.

(Object of the invention) Therefore, the present invention detects the drain voltage and the gate voltage,
By determining the drain current based on the detected value,
It is an object of the present invention to provide a drain current detection circuit for a field effect transistor that does not use a shunt resistor Rs.

(Structure of the Invention) In order to achieve the above object, the present invention provides that the drain current during conduction is determined by the gate applied voltage and the drain applied voltage during non-abuse, and the drain voltage corresponding to the drain current and internal resistance is determined. a field effect transistor generated at a drain terminal, a comparison means for detecting a drain voltage generated at the drain terminal and comparing it with a predetermined reference voltage;
Gate voltage detection means for detecting the gate applied voltage;
current detection means for detecting a drain current based on the detection result of the gate voltage detection means and the comparison result of the comparison means;
It is characterized by having the following.

Hereinafter, the present invention will be specifically explained based on examples.

FIG. 1.2 is a diagram showing an embodiment of the present invention, in which the present invention is applied to a switching regulator.

First, the configuration will be explained. In FIG. 1, Ql is a field effect transistor (FET: Field Eff
ectTransistor), and this field effect transistor Q1 is an enhancement type N-channel FE having a predetermined capacitance between the gate G and the channel.
T is used. The input voltage Vin is applied to the drain D of the field effect transistor Q1 via the coil L1, and the input voltage Vin is applied to the drain D of the field effect transistor Q1 via the resistor R1.
The output logic level from output terminal Q of /F is input. Note that the source S of the field effect transistor Q1 is connected to GND. The flip-flop F/F is an R-S flip-flop that is activated at the falling edge of the input signal (hereinafter referred to as a negative edge).

The rD detection signal Va is input to the force R, respectively.

On the other hand, the anode of a diode D1 is connected to the drain D of the field effect transistor Q1, and the output voltage Vout is taken out from the cathode of the diode D1.

The output voltage Vout is divided by resistors R2 and R3, and is input as an output voltage sample vb to the negative terminal of the differential amplifier ICI.

Further, the output voltage Vout is applied to the constant voltage diode ZDI via the resistor R4, and the voltage held at a predetermined value by the constant voltage diode ZDl is inputted as the reference voltage E2□ to the positive terminal of the differential amplifier ICI. . The differential amplifier ICI uses the output voltage sample vb and the reference voltage E.
The difference in 2Dl is inverted and amplified, and a predetermined FET characteristic curve (Vn
It is output to the negative terminal of the comparator COMP 1 as a target drain voltage Vc indicating the drain voltage at s ID). The positive terminal of the comparator COMP 1 is connected to the drain voltage VO of the field effect transistor Q1.
S is input, and the comparator COMP 1 is the above Vc and ■. A drain comparison signal Vd which becomes CH) level when VDS>VC is output to NAND1.

On the other hand, the input voltage Vin is applied to the constant voltage diode ZD2 via the resistor R5, and the voltage maintained at a predetermined value by the constant voltage diode ZD2 becomes the target gate voltage Ezo2.
The signal is input to the negative terminal of the comparator COMP2. The target gate voltage Ezax sets a target value of the gate voltage to obtain a predetermined FET characteristic curve (Vns-1o). Gate voltage ■ is applied to the positive terminal of comparator COMP2. , is input, and the comparator COMP 2
compares E2,2 and VGS and sets the gate comparison signal Ve to 2.
Output to human power NAND 1. Note that the gate comparison signal V
e is ■. When S>E2D2, it becomes the (H) level, indicating that the current gate voltage V (, 5) has reached the target value of the gate voltage for obtaining the above-mentioned predetermined FET characteristic curve.

When the output of the comparator COMP1 and the output of the comparator COMP2 are both at the (H) level, the two-manpower NAND 1 sets the ID detection signal Va to the (L) level and outputs it to the reset input T of the flip-flop (F/F). Set the logic level of output terminal Q of F/F to (L
) level.

The comparator COMP 1 has a function as a comparison means for detecting a drain voltage and comparing it with a predetermined reference voltage, and the comparator COMP 2 has a function as a gate voltage detection means for detecting a gate voltage. Furthermore, the two-man powered NANDI has a function as a current detection means for detecting drain current.

Next, the circuit operation will be explained with reference to the waveform diagrams of each part shown in FIGS. 2(a) to 2(h).

In general, switching regulators are used as power supplies for communication devices that often use DC power supplies, and as DC-DC comparators for mobile bodies and portable devices.

Its operation is to store electric energy corresponding to ON10FFL and ON10FF timings in the inductance using a switching element, and take out the current flowing through the inductance. Therefore, 0 of the switching element
A desired voltage output is obtained by appropriately controlling the N10FF timing according to the load. In this example,
The current flowing through the above inductance, that is, the drain current I when the FET is turned on, is determined from a characteristic curve (so-called drain voltage VDS - drain current ■ characteristic curve) determined using the gate voltage VG3 and the drain voltage ■ and S at turn-off as parameters. Focusing on what is required, detecting the above parameters and determining the drain current at turn-off■
, and based on this, the turn-off timing of the FET is appropriately controlled.

Input voltage V that becomes the DC input of the switching regulator
in is connected to the field effect transistor Q1 via the coil L1.
is applied to the drain D of the capacitor C1 through the diode D1. At this time, the field effect transistor Q1 has not yet been turned on, so the drain voltage is ■. , have the same value as the input voltage Vin.

In this state, as shown in FIG. 2(a), when the clock signal CLK transitions from the CLI) level to the (L) level (i.e., negative edge), the lodge level of the output terminal Q of the flip-flop F/F changes. is sent to the [H] level (see FIG. 2(b)). This (H) level is applied to the gate G of the field effect transistor Q1 via the resistor R1, and charges the capacitance of the field effect transistor Q1. The charging speed is determined by the time constant of the resistor R1 and the capacitance, and rises with a slope as shown in FIG. 2(c).

Such a charging waveform, that is, the gate voltage VG9, in its rising process, exceeds the potential required to turn on the field effect transistor Q1 (hereinafter referred to as threshold voltage Th), and the gate voltage VG9 exceeds the potential required to turn on the field effect transistor Q1.
turn on. Therefore, the input terminal Vin is connected to GND via the coil L1 and the field effect transistor Q1, and a closed circuit for the drain current 10 is formed. Drain current■. increases linearly with the slope shown in the following equation (■) due to the reactance component of the coil L1.
As shown in FIG.
occurs.

VDS"" RONX I n ・・・・・・■ Therefore, the drain voltage VDS when the field effect transistor Q1 is conductive is the voltage obtained by subtracting the voltage VLI (see the following formula ■) from the input voltage Vin. value, and its slope is the drain current ■ mentioned above.

(see FIG. 2(e)).

V Ll = L I As shown in c), the target gate voltage EZD2 is exceeded.Since the target gate voltage E2D2 is set slightly higher than the threshold voltage Th representing the turn-on start level of the field effect transistor Q1, ■GS> EZD2 indicates that the current gate voltage V has reached the target gate voltage value for obtaining a predetermined FET characteristic curve. Therefore,
Comparator COMP 2 outputs the gate comparison signal Ve (H
) level and declare the turn-on state (Figure 2 (d)
)reference). In addition, the drain voltage VOS in the turn-on state
is compared with a target drain voltage Vc, which will be described later, in a comparator COMPI. , >Vc, the drain comparison signal Vd becomes (H) level (Fig. 2 (e), (f)
)reference). That is, since the drain voltage VDS changes in correspondence with the drain current ID, when the drain comparison signal Vd is at the (L) level, the drain current is ■. This shows that the number is on the rise. Further, when the drain comparison signal Vd changes from (L) to [H] level, it indicates that the current drain voltage VOS has reached the drain voltage in a predetermined FET characteristic curve. The above gate comparison signal Ve and drain comparison signal Vd are generated by two people N
An AND is taken with A N D 1, and when both are at the (H) level, ID The detection signal Va is set to the (L) level, the flip-flop F/F is reset, and the logic level of the output terminal Q is set to the (L) level. As a result, the gate voltage ■6. (that is, the charging potential of the capacitance) is the output terminal Q
begins discharging towards the logic level of Discharging is performed with a slope corresponding to the time constant of the resistor R1 and capacitance, and first, the gate voltage V0. When the value becomes low, the gate comparison signal Ve is set to (L) level.

Furthermore, the discharge continues, and finally the gate voltage V6.
becomes below the threshold voltage Th, and the field effect transistor Q1 reliably enters the turn-off state. Therefore, as shown in FIG. 2(g), the drain current is . becomes zero, and the drain voltage ■. .

also tries to return toward the input voltage Vin. However, the drain current ■ in the coil L1. As a result of the flow, the voltage V L I shown in the previous equation (2) has already been accumulated, and 1. This voltage VLI becomes a flybank voltage and is superimposed on the input voltage Vin, resulting in a drain voltage ■. , (see Figure 2(e)). The drain voltages v, s exhibiting such changes are rectified by the diode D1 and the capacitor CI, and are supplied to a load (not shown) as an output voltage Vout. By the way, the drain voltage V mentioned above. , the target drain voltage Vc to be compared with is obtained by inverting and amplifying the difference between the output voltage sample v'b obtained by dividing the output voltage VouL and the reference voltage EZDI, and the target drain voltage Vc is inversely proportional to the output voltage Vout. be. That is, when the output voltage Vout increases due to a variation in the input voltage Vin or a variation in the load, the target drain voltage Vc decreases, and when the output voltage Vout decreases, the target drain voltage Vc increases. The target drain voltage Vc exhibiting such a change is determined by the drain voltage V9. of the field effect transistor Q1 in the above-mentioned comparator COMP1. This becomes an index for determining the turn-off timing of the field effect transistor Q1. That is, the target drain voltage Vc
When is high, it is when the output voltage Vout has decreased due to changes in the load, etc. In this case, it is necessary to increase the drain current I to increase the voltage V L 1 accumulated in the coil L1. Therefore, by delaying the turn-off timing of the field effect transistor Q1, the drain current I
continues to rise (that is, increases the drain current I) to increase the output voltage VOLIt. On the other hand, when the output voltage Vout is high, the target drain voltage Vc is low, so the turn-off timing is advanced,
Drain current I. The rise in Vo is stopped early, and the output voltage Vo
ut becomes low.

As described above, in this embodiment, focusing on the fact that the drain voltage VD at the time of turn-on changes in accordance with the drain current In, the gate voltage VaS is detected to declare the turn-on state, and the drain voltage Vcs is also detected. , the drain current I is detected from a predetermined characteristic curve (Vos In) determined using the gate voltage V (, 3 and the drain voltage VDS as parameters), and the drain current I is set based on the output voltage Vout. When the drain current reaches the drain current, the turn-off timing of the field effect transistor Q1 is determined and the drain current I is controlled, and the output voltage Vo
ut is variable. Therefore, the drain voltage Kt I
A circuit insertion resistor (conventional shunt resistor) for detecting n is no longer necessary, and various problems caused by providing the resistor are completely eliminated.

In other words, since the above-mentioned resistor is not provided, no power loss occurs,
Furthermore, heat generation due to power loss is avoided, reliability is improved, and problem (1) is solved. In addition, inductive noise caused by the inductance component Lx of the resistor is eliminated,
The detection accuracy of small level signals is improved and problem (II) is solved. Furthermore, since the source S of the field effect transistor Q1 is connected to GND, no unnecessary voltage is induced in the source S, and problem (III) is solved.

Note that a unique effect of this embodiment is that, for example, when the turn-off control of the field effect transistor Q1 is used as overcurrent protection, the target drain voltage Vc has a negative dependence on the temperature characteristics of the field effect transistor Q1. Therefore, heat generation due to the channel resistors R0,1 can be suppressed against the temperature rise of the field effect transistor Q1, and thermal runaway of the field effect transistor Q1 can be prevented.

(Effects) According to the present invention, drain voltage and gate voltage are detected,
Since the drain current is determined based on the detected value, the drain current can be controlled without using a shunt resistor, and various problems that would occur due to the use of a shunt resistor can be completely eliminated. . That is,
Improved reliability by reducing power loss and heat generation, and improved detection accuracy by eliminating inductive noise.
There is an excellent effect that unnecessary voltage is not induced in the source S and switching speed is improved.

[Brief explanation of the drawing]

Figure 1.2 is a diagram showing an embodiment of the drain current detection circuit of a field effect transistor of the present invention, and Figure 1 is a circuit diagram of a switching regulator to which the field effect transistor drain current detection circuit is applied. Figure 2(a)~
(h) is a timing chart showing waveforms of various parts to explain the circuit operation of the switching regulator shown in FIG. 1, and FIG. 3 is a circuit diagram showing a conventional drain current detection circuit of a field effect transistor. ■・・・Two-man power NAND (current detection means), C
OMP 1... Compare (comparison means), C
OMP 2...Comparator (Kate?JI
+ti output means). Ql...Field effect transistor.

Claims (1)

[Claims] A field effect transistor in which a drain current when conducting is determined by a voltage applied to the gate and a voltage applied to the drain when non-conducting, and a drain voltage corresponding to the drain current and internal resistance is generated at the drain terminal. a comparison means for detecting the drain voltage applied to the gate and comparing it with a predetermined reference voltage; a gate voltage detection means for detecting the gate applied voltage; A drain current detection circuit for a field effect transistor, comprising: current detection means for detecting current.