JPS63146365U - - Google Patents
Info
- Publication number
- JPS63146365U JPS63146365U JP3740887U JP3740887U JPS63146365U JP S63146365 U JPS63146365 U JP S63146365U JP 3740887 U JP3740887 U JP 3740887U JP 3740887 U JP3740887 U JP 3740887U JP S63146365 U JPS63146365 U JP S63146365U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- burst data
- reproducing
- digital
- reproduced
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
- 238000005070 sampling Methods 0.000 description 1
Landscapes
- Signal Processing For Digital Recording And Reproducing (AREA)
Description
第１図は本考案の一実施例に係る回路ブロツク
図、第２図は従来回路の回路ブロツク図を、それ
ぞれ示す。
１１ｂ……サンプリング制限回路、１１ｃ……
サンプルホールド回路、２……コンパレータ、１
１ｄ……デコーダ。
FIG. 1 shows a circuit block diagram according to an embodiment of the present invention, and FIG. 2 shows a circuit block diagram of a conventional circuit. 11b...Sampling limit circuit, 11c...
Sample hold circuit, 2...Comparator, 1
1d...decoder.
Claims (1)
ータを付加して成るデイジタル信号に映像信号を
多重してＦＭ変調記録して成る記録媒体を再生す
る再生装置に於て、 再生デイジタル信号と基準出力とのレベルを比
較して矩形波状の比較出力を導出するコンパレー
タと、再生バーストデータに対応する前記比較出
力のデユーテイサイクルに基づいて前記基準出力
のレベルを設定するレベル設定回路と、再生バー
ストデータ発生タイミングに於ける再生信号の欠
落を検出して前記レベル設定回路の設定動作を休
止せしめる制限回路とを、それぞれ配して成る再
生デイジタル信号読取制御回路。[Claims for Utility Model Registration] In a reproducing device for reproducing a recording medium formed by FM modulation and recording by multiplexing a video signal onto a digital signal in which burst data is added to a position preceding the digital data, reproducing digital a comparator that compares the levels of the signal and a reference output to derive a rectangular wave-like comparison output; and a level setting circuit that sets the level of the reference output based on the duty cycle of the comparison output corresponding to reproduced burst data. and a limiting circuit that detects a loss of the reproduced signal at the reproduction burst data generation timing and suspends the setting operation of the level setting circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3740887U JPS63146365U (en) | 1987-03-13 | 1987-03-13 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3740887U JPS63146365U (en) | 1987-03-13 | 1987-03-13 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63146365U true JPS63146365U (en) | 1988-09-27 |
Family
ID=30848709
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3740887U Pending JPS63146365U (en) | 1987-03-13 | 1987-03-13 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63146365U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6013362A (en) * | 1983-06-30 | 1985-01-23 | Matsushita Electric Ind Co Ltd | Auto-slicing circuit |
| JPS6229675B2 (en) * | 1981-10-29 | 1987-06-27 | Kearney & Trecker Corp |
-
1987
- 1987-03-13 JP JP3740887U patent/JPS63146365U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6229675B2 (en) * | 1981-10-29 | 1987-06-27 | Kearney & Trecker Corp | |
| JPS6013362A (en) * | 1983-06-30 | 1985-01-23 | Matsushita Electric Ind Co Ltd | Auto-slicing circuit |
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