JPS63146276A - Digital limiter - Google Patents

Abstract

PURPOSE:To realize a satisfactory soft limiting operation without deteriorating the linearity by setting the first and final data that exceedes a limit level at the mean level between the immediately processing and next data limit levels. CONSTITUTION:The output S15 of a detecting circuit 15 shown whether an input video signal SiD exceeded a limit level or not. The selecting circuit 3, 5 and 11 limit the amplitudes of the first and final data that exceeded the limit level are limited to the outputs S7 of data generating circuit 6-10 corresponding to those first and final data by the switch signals SW2-SW4 received from a switch signal generating circuit 20. At the same time, the amplitudes of other data that exceeded the limit level are limited to the prescribed levels. As a result, the signal SiD is softly limited. And a satisfactory soft limiting operation is attained without deteriorating the linearity owing to replacement with a mean level.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital limiter suitable for use, for example, in limiting the amplitude of a video signal subjected to contour correction processing.

[Summary of the invention]

In a digital limiter that limits the amplitude of a video signal, the present invention impairs linearity by setting the first and last data exceeding the limit level to the average level of the limit level and the data immediately before and after the limit level. First, it is possible to achieve a good soft limit.

[Conventional technology]

FIG. 4 shows a circuit for processing video signals from, for example, a video camera. In the figure, input video signal St
is converted into a 1-sample 8-bit digital signal by an A/D converter (31). The straight binary 8-pin video signal from this A/D converter (31) is added to E! (
32) and the contour correction signal forming circuit (33).
).

Offset binary from this signal forming circuit (33)
Then, the 8-bit contour correction signal SAP is supplied to an adder (32). Then, in the adder (32), the contour correction signal SAP is added to the video signal, and the adder (32) adds the contour correction signal SAP to the video signal.
32) provides a 9-bit video signal with enhanced edge portions. In this case, for example, the range of "00" to rFFJ (hexadecimal) in 8-bit data is set to the range of "80" to r180J (hexadecimal) in 9-bit data, and by adding the contour correction signal SAP described above, 9 The video signal in focus may be outside the range of "80" to r180J.

Further, the 9-bit video signal from the adder (32) is supplied to the digital limiter (34), and the 9-bit video signal from the adder (32) is
The amplitude of the portion outside the range of 0J is limited, and an 8-bit video signal in the range of "00" to rFFJ is obtained from this digital limiter (34).

Further, the 8-bit E video signal from the digital limiter (34) is supplied to the D/A converter (36) via the gamma correction circuit (35), and from this D/A converter (36) An analog video signal SO is obtained.

[Problem that the invention seeks to solve]

In this example in FIG. 4, the digital limiter (34) is
For example, it is composed of a conversion table such as a ROM, and has input/output characteristics (limiter characteristics) as shown in FIG. That is, in order to suppress overshoot and undershoot caused by the interpolation filter after conversion to an analog signal, the slope near the upper limit rFFJ in the white direction and the lower limit "OO" in the black direction are made gentle, and the video signal is processed by the so-called soft limit. be done.

However, in the case where the soft limit is applied in this manner, data near the upper limit and the lower limit that have not reached the limit level are also compressed, resulting in a disadvantage that linearity is impaired.

The present invention enables a good soft limit without such inconvenience.

[Means for solving problems]

In the present invention, a digital video signal of n+l bytes (n is a natural number) is input, and the MSB of this input video signal Sho
and a detection circuit (15) that detects the state of 2SB, and an output StS of this detection circuit (15) is supplied and a switching signal SW is provided.
2 to SW4, a first signal forming circuit (20) that forms an n-bit signal S2 consisting of n-bit data excluding data of 2SB of the input video signal Sho, and an input The second signal forming circuit (2) forms an n-bit signal S2' in which the MSB data of the video signal SID becomes the data of each bit, and the first signal forming circuit (2) ) generates average value data S7 of output signal S2 of
) to (10), and the output signals of the first and second signal forming circuits (2) and data generating circuits (6) to (lO) are selectively output by switching signals from the switching signal generating circuit (20). A selection circuit (
31, (5), and (11).

[Effect]

In the above configuration, the output Sxs of the detection circuit (15) is
This indicates whether the input video signal SID exceeds the limit level. and a selection circuit (3).

In (5) and (11), the switching signal generation circuit (
The amplitude of the first and last data exceeding the limit level is limited by the switching signals SW2 to SW4 from 20) to the outputs S7 of the data generation circuits (6) to (10) corresponding to immediately before and after the data generation circuits (6) to (10), and The amplitude of other data exceeding the limit level is limited to the limit level. Therefore, the input video signal SIo is soft limited.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG.

In the figure, (1) is an input terminal to which, for example, a 9-bit video signal S1D obtained from the adder (32) in the example of FIG. 4 is supplied. The video signal Slo supplied to this terminal +1) is supplied to the D terminal of the D flip-flop (2). Output terminal Q' of this flip-flop (2)
In this case, an 8-bit signal S2' is obtained in which the MSB (pin point 9) data of the video signal SID is the data of each bit, and this signal S21 is supplied to the L side terminal of the switch circuit (3). . This signal S2' is the video signal Sh
When the MSB data of o is high level 11", "
11111111'' (rFFJ in hexadecimal), and when the MSB data is a low level 0, it becomes r00000000'' (rooJ in hexadecimal), which is the upper or lower limit of the 8-pinto data. Furthermore, at the output terminal Q of the flip-flop (2), an 8-pin signal S2 consisting of the remaining 8 bits of data excluding the 2SB (bit 8) of the video signal Sio is obtained, and this signal S2 is connected to the switch circuit ( 3) is supplied to the H side terminal. This signal S2 is a 9-bit video signal S+
The range from "80" to r18QJ (to be exact, 17Fl) of o is converted to correspond to the range from "00" to rFFJ of 8-bit data. For example, "80" to 9-bit data. r 17F J is r 0100000
00 J~r 101111111" and 2SB
The 8-bit data consisting of the remaining 8-bit data excluding the data of (bit 8) is r 0OOOOOOJ^r 1
1111111” and becomes “00” to rFFJ.

゛The output S3 of this switch circuit (3) is supplied to the D terminal of the D flip-flop (4), and the signal S4 obtained at the output terminal Q of this flip-flop (4) is supplied to the H side of the switch circuit (5). is supplied to the terminal.

Further, the signal S2 obtained at the output terminal Q of the flip-flop (2) is halved by the level adjuster (6) and then supplied to the L side terminal of the switch circuit (7). Further, the signal S2 is supplied to the level adjuster (9) via the inverter (8), and after being set to 1/2 level by the level adjuster (9), the signal S2 is sent to the switch circuit (7) via the inverter (10).
is supplied to the H side terminal of. The switch circuit (7) includes
The data of any bit of the signal 82' obtained at the output terminal Q' of the flip-flop (2) is the switching signal SW.
1, and the switch circuit (7) is connected to the I( side and the L side, respectively) when the switching signal SW1 is at the high level "lo" and the low level "0". In this case, the MSB of the video signal Sho '' (focus 9) is at a low level "O", the switching signal SWI is at a low level "θ", so the switch circuit (7) is connected to the L side. Therefore, the switch circuit (7) The output S? is the signal with the signal S2 set to 1/2 level, that is, the lower limit value r 0OOOOOOOOJ (rooJ in hexadecimal) of the 8-pinto data and the average value data of the signal S2.On the other hand,
When the data of the MSB (bit 9) of the video signal SID is at a high level "1", the switching signal SW1 is at a high level "1", so the switch circuit (7) is connected to the H side. Therefore, the output S7 of the switch circuit (7) is
The signal S2 is inverted and becomes l/2, and the inverted signal, that is, the upper limit value r of 8-bit data
This is the average value data of IJ (rFFJ in hexadecimal) and signal S2.

Further, the output S7 of this switch circuit (7) is supplied to the L side of the switch circuit (5), and the output S5 of this switch circuit (5) is supplied to the H side of the switch circuit (11).

In addition, the output S7 of the switch circuit (7) is supplied to the D terminal of the D flip-flop (12), and the signal obtained at the output terminal Q of this flip-flop (12) is supplied to the D terminal of the D flip-flop (13). The signal Sxi obtained at the output terminal Q of this flip-flop (13) is supplied to the L side of the switch circuit (11).

Moreover, the output of the switch circuit (11) is the output video signal S
It is led out to the output terminal (14) as OD.

Furthermore, of the video signal Sio supplied to the terminal (11), the MSB (pin 9) and 2SB (bit 8) data are supplied to an exclusive OR circuit (hereinafter referred to as rEX-OR circuit) (15). Ru.

In this case, the output Sss of the EX-OR circuit (15) is such that the video signal SID is rolooooooooo J (1
r80J in hexadecimal) ≦Sto< r 1100000
When 00 J (r180J in hexadecimal notation) is satisfied, the high level is "1", and when it is not satisfied, the low level is 10''.

(7) The output S15 of the EX-OR circuit (15) is a D flip-flop (
21) is supplied to the D61 child of this flip-flop (
The signal obtained at the output terminal Q of 21) is supplied to the D terminal of the flip-flop (22). Then, the signal obtained at the output S15 of the EX-OR circuit (15) and the output terminals Q of the flip-flops (21) and (22) is the OR circuit (2
3), and the output of this OR circuit (23) is supplied to the switch circuit (3) as a switching signal SW2. In the switch circuit (3), the switching signal S'W2 is at a high level.
1" and low level "θ", it is connected to the H side and the L side, respectively.

Further, the output Shs of the EX-OR circuit (15) and the signal obtained at the inverting output terminal δ of the flip-flop (21) are supplied to the NAND circuit (24). This NAND circuit (2
4) is supplied to the D terminal of the D flip-flop (25), and the signal obtained at the output terminal Q of this flip-flop (25) is supplied to the switch circuit (5) as a switching signal SW3.
). The switch circuit (5) receives a switching signal SW
3 is connected to the II side and the L side, respectively, when the high level is "1" and the low level is "0°".

In addition, the signal obtained at the output terminal Q of the flip-flop (21) and the inverted output terminal Q of the flip-flop (22)
The signal obtained is supplied to the OR circuit (26). The output of this OR circuit (26) is a D flip-flop (27)
The signal obtained at the output terminal Q of this flip-flop (27) is supplied to the switch circuit (11) as a switching signal SW4. Switch circuit (11)
are connected to the H side and the L side, respectively, when the switching signal S W 4 is at a high level "1" and a low level "O".

In the above configuration, consider the case where a video signal Sio as shown in FIG. 2A is supplied to the input terminal (1).

In this video signal SID, the part indicated by the "x" mark is r 010000000 J (r8 in hexadecimal notation)
0J)≦Sin< [110000000J (16
If the amplitude-limited part does not satisfy r180J in base system and is limited in amplitude, the output S8 of the EX-OR circuit (15)
5 is the "x" of the video signal SID, as shown in FIG.
The low level “0” corresponds to the marked portion, and the high level “1” corresponds to the other portions. Therefore, the OR circuit (2
Switching signal SW supplied from 3) to the switch circuit (3)
a becomes as shown in figure C, and a flip-flop (25
) is supplied to the switch circuit (5) as shown in the figure, and the switching signal SW is supplied from the flip-flop (
The switching signal SW4 supplied from 27) to the switch circuit (11) is as shown in FIG.

Further, the signal S2 obtained at the output terminal Q of the flip-flop (2) is delayed by one clock in timing from the video signal SiD, as shown in FIG. In the figure, the portion marked with an "X" corresponds to the amplitude limited portion of the video signal SID.

Furthermore, when the switching signal S W 2 is at the high level "11" and the low level "0", the switch circuit (3) is connected to the H side and the L side, respectively, so that the output S of the switch circuit (3)
3 is as shown in FIG. That is, the output S3 becomes the signals S2 and 32' when the switching signal SW2 is at the high level "1" and the low level "0", respectively. Further, the signal S4 obtained at the output terminal Q of the flip-flop (4) is delayed by one clock in timing from the output S3 of the switch circuit (3), as shown in H in the figure.

Further, as described above, when the MSB (bit 9) data of the video signal Sho is low level "0", the output S7 of the switch circuit (7) is the lower limit value r 0OOOOOOOOJ (hexadecimal notation) of the 8-pin data. So roo
J) and the average value data of the signal S2, and when the data of the MSB (bit 9) of the video signal SID is a high level "1", the data upper limit value r
1111.1111J (rFFJ in hexadecimal) and the average value data of the signal S2. In Figure 2 ■,
The parts indicated by rOJ mark and “・” mark are respectively video signal S.
Average value data corresponding to immediately before and immediately after the amplitude limited portion of tO is shown. Further, the signal S13 obtained at the output terminal Q of the flip-flop (13) is delayed by two clocks from the output S7 of the switch circuit (7), as shown in J of the figure.

Furthermore, when the switching signal SW3 is at a high level "l" and a low level mOs, the switch circuit (5) is connected to the H side and the L side, respectively, so the output S5 of this switch circuit (5) is the same. The result is as shown in Figure K. That is, when the switching signal 5V1h is at the high level "11" and the low level "0", the output S5 becomes the signals S4 and S7, respectively.

Furthermore, when the switching signal SW4 is at a high level "1" and a low level "09", the switch circuit (11) is connected to the H side and the L side, respectively, so that the output terminal (14) is connected to the switch circuit (11). The video signal Soo derived is as shown in the same figure. That is, when the switching signal SW4 is at the high level "l'" and the low level "0", the video signal SoD becomes the signals S5 and S13, respectively.

Looking at this output video signal SOO, we see that it is the video signal S2 converted to 8 bits from the flip-flop (2).
Only the portion corresponding to the amplitude limited portion of the input video signal Sio is amplitude limited. In this case, in the amplitude limited part where three or more pieces of data continue, the first data is replaced with the average value data (indicated by "○" mark) of the previous data and the limit level, and the last data is It is replaced with the average value data (indicated by "・" mark) of the immediately following data and the limit level, and the intermediate data between the first and last data is replaced with the limit level data ("H").
”). Also, data is continuous (in the amplitude limit part, the first data is replaced with the average value data of the data immediately before it and the limit level, and the last data is replaced with the average value data of the data immediately after it and the limit level). In addition, in an amplitude limited portion where there is one data, that data is replaced with average value data of the immediately preceding data and the limit level.

In this way, according to this example, the limit level ("80" or r180J in the input video signal SID, rOOJ or rF in the signal S2 after 8-bit conversion)
The first or last data that exceeds FJ) is replaced by the average value data of the data immediately before or after it and the limit level, so that it is soft limited. That is, in FIG. 3, the data before amplitude limitation is
”, the data is amplitude-limited and soft limited as shown by the “•” mark in the figure. Moreover, according to the present example, no limit is imposed on the data that does not exceed the limit level, so there is no problem with the conventional method that impairs linearity.

In the above-mentioned embodiment, in the amplitude limiting part where there is one data, that data is replaced with the average value data of the immediately preceding data and the limit level, but the average value of the immediately following data and the limit level is replaced. It may be replaced with data.

Further, the above embodiment uses a 9-pin video signal Sh.

, and outputs an 8-bit video signal Soo. However, the present invention can generally be applied to a device that inputs an n+1-bit video signal and outputs an n-bit video signal.

〔Effect of the invention〕

According to the present invention described above, since the first and last data exceeding the limit level are replaced with the average value level of the data immediately before and after that and the limit level, good software can be achieved without impairing linearity. Limits are possible.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the present invention, Figs. 2 and 3 are diagrams for explaining the same, Fig. 4 is a block diagram of an example of a video signal processing circuit, and Fig. 5 is a digital FIG. 3 is a diagram for explaining a limiter. (1) is an input terminal, (2) (4) (12) and (13
) is a D flip-flop, (3) (5) (7) and (11) are switch circuits, (6) and (9) are level adjusters, (8) and (10) are inverters, (14) is output terminal, (15) is exclusive OR circuit, (20
) is a switching signal generation circuit.

Claims (1)

[Claims] (a) A digital video signal of n+1 bits (n is a natural number) is input, and the MSB and 2SB of this input video signal are
(b) A switching signal generation circuit that is supplied with the output of this detection circuit and generates a switching signal; (c) Consisting of n-bit data excluding 2SB data of the input video signal. a first signal forming circuit that forms an n-bit signal; (d) a second signal forming circuit that forms an n-bit signal in which each bit of data is MSB data of the input video signal; ) a data generation circuit that generates upper and lower limit values of n-bit data and average value data of the output signal of the first signal forming circuit; 2. A digital limiter comprising a signal forming circuit of 2 and a selection circuit for selectively selecting an output signal of the data generating circuit to obtain an n-bit output video signal.