JPS6314527B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a phase control circuit that controls the phase of a desired signal using, for example, a DC voltage, and particularly relates to a phase control circuit that controls the phase of each desired signal while maintaining a predetermined phase difference between the desired signals. The present invention relates to a phase control circuit that can be implemented and is suitable for being integrated into a semiconductor integrated circuit.

It is generally known that, for example, in a color television receiver, a hue adjustment circuit is provided within a chroma signal processing circuit. A phase control circuit for controlling the phase of the subcarrier is used in this hue adjustment circuit.

The configuration of this phase control circuit uses the block diagram shown in FIG.

In FIG. 1a, numeral 1 is an input terminal,
The desired signal input from this input terminal 1 is converted into two signals e〓 ₁ and e〓 ₂ having at least a phase difference from each other by phase shift circuits 2 and 3, and these signals e〓 ₁ and e〓 ₂ are relatively The signal is configured to be input to a synthesis circuit 4 that adds the signal while changing the amplitude ratio.

These signals e〓 ₁ and e〓 ₂ are combined in the synthesis circuit 4 and outputted from the output terminal 5 as a signal e〓 ₃ whose phase is variable.

Reference numeral 6 denotes a control signal input terminal for controlling the synthesis circuit 4, and a control signal, for example, a DC voltage, is input to this terminal 6 to control the phase of the output signal _e〓3 .

FIG. 1b is a vector representation of the phase relationship of the signals e〓 ₁ , e〓 ₂ , e〓 ₃ . The symbol P in the figure is a variable coefficient, and the variable range is 0≦P≦ by the control signal.
It is set to be 1.

Therefore, in the synthesis circuit 4, the signals are synthesized so that the relationship Pe〓 ₁ + (1 - P) e〓 ₂ = e〓 ₃ ...(1) holds, and the signal e〓 ₃
is a signal that varies the range Θ of the phase difference between the signals e〓 ₁ and e〓 ₂ .

It has already been explained that this phase control circuit is used, for example, in a chroma signal processing circuit, particularly a hue adjustment circuit, of a color television receiver. FIG. 2 is a block diagram showing a known chroma signal processing circuit to which this phase circuit is applied.

In FIG. 2, reference numeral 21 is an ACC (automatic chromaticity signal adjustment) circuit that keeps the amplitude of the color signal constant;
22 is a burst gate circuit, 23 is a chroma amplifier, 24 is a demodulator, 25 is an ACC detector, 26 is a
An APC (automatic phase control) detection circuit, 27 a VCO (voltage control oscillator), 28 a killer detector, and 29 a hue adjustment circuit.

These circuits are now integrated circuits, and since there is a limit to the number of pins on an IC package, circuits are configured to minimize the number of pins. The phase of the subcarrier is controlled in this hue adjustment circuit 29, and the subcarrier is inputted to the demodulator 24 as shown in FIG. 2a, or as shown in FIG. 2b.
APC detector 26 and killer detector 2 as shown in
8.

At this time, when the output signal of the hue adjustment circuit 29 is supplied to the demodulator 24 as shown in FIG. 2a,
Since two demodulation axes [(RY) and (BY)] are required, subcarriers whose phases are controlled with a phase difference of 90 degrees are required.

In addition, even in the case shown in FIG. 2b, since it is necessary to supply the APC detector 26 and the killer detector 28 and to maximize the sensitivity of the killer detector 26, the sub-wavelength is controlled with a phase difference of 90 degrees. A carrier wave is required.

In this way, a phase control circuit is required to maintain the phase difference of the desired signal at a predetermined phase difference and perform phase control, and as described above, the circuit shown in the block diagram shown in FIG. 1 has conventionally been used.

FIG. 3 shows a specific circuit example of this phase control circuit, and FIG. 4 is a vector diagram for explaining the operation of the phase control circuit shown in FIG. 3.

In FIG. 3, transistors 31 to 40
constitutes a double-balanced differential amplifier. Transistors 31 and 32 constitute a first differential amplifier, their emitters are grounded via a current source 41, the collector of transistor 31 is connected to the emitters of transistors 35 and 36, and transistor 32 is connected to the emitters of transistors 35 and 36.
The collectors of the transistors 37 and 38 are connected to the emitters of the transistors 37 and 38, the base of the transistor 31 is connected to the first output terminal of the phase shift circuit 30, and the base of the transistor 32 is connected to the positive electrode of a bias power supply 42 whose negative electrode is grounded.

Transistors 33 and 34 constitute a second differential amplifier, and their emitters are grounded via a current source 43, the collector of transistor 33 is connected to the emitters of transistors 39 and 40, and the collector of transistor 34 is connected to power supply Vcc. Transistor 3 to
3 is connected to the second output terminal of the phase shift circuit 30,
The bases of the transistors 34 are each connected to the positive terminal of a bias power supply 44 whose negative terminal is grounded.

Further, the bases of the transistors 35, 38, and 39 are respectively connected to the phase control input terminal _P1 , and the bases of the transistors 36, 37, and 40 are respectively connected to the phase control input terminal _P2 . The collectors of these transistors 35 and 37 are connected to the power supply Vcc. The collectors of the transistors 38 and 40 are connected to the power supply Vcc via a resistor 45 and to the output terminal _P3 . transistor 36,
The collector of 39 is connected to the power supply Vcc via a resistor 46 and also to the output terminal _P4 .

The phase shift circuit 30 outputs a signal e〓 ₁ to a first output terminal and outputs a signal e〓 ₂ to a second output terminal, and the signals e〓 ₁ and e〓 ₂ are in phase with each other. It is configured to have a phase difference.

The operation of the phase control circuit configured as above will be explained with reference to FIG. 4.

In FIG. 4, the amplitude display of each vector is a relative display to see the phase relationship, so it is not an accurate display. The symbols e〓 ₁ and e〓 ₂ in the figure are the phase shift circuit 30
The signal e〓 ₁ output from the first and second output terminals of
e〓 ₂ , they have a phase difference of 90 degrees, and |e〓 ₁ |
=｜e〓 ₂ ｜. Here, for convenience of explanation, e〓 ₁ is assumed to be the reference phase of 0 degrees, and ∠e〓 ₂ is assumed to be -90 degrees.

It is assumed that the transistors 31 to 40 in FIG. 3 have similar characteristics, and the currents of the current sources 41 and 43 are made equal. The collector current signals of transistors 31, 32, 33
I〓 ₁ , −I〓 ₁ , I〓 ₂ and transistors 31 and 32,
3
Let K be the coefficient of the differential amplifier composed of each pair of 3 and 34, I〓 ₁ = Ke〓 ₁ ......(2) I〓 ₂ = Ke〓 ₂ ......(3) Terminals P ₁ , P ₂ A DC control voltage for phase control is printed on the differential amplifiers 35, 36, 37, and 3.
Control the dividing ratios of 8, 39 and 40. In each differential amplifier, transistors 35, 3
The shunt coefficient of transistor 8,39 is (1-P)
If the dividing coefficients of transistors 36, 37, and 40 are P, the currents Ia and Ib flowing through resistors 46 and 45 are
Let the values of resistors 46 and 45 be R ₁ and R ₂ and R ₁ =
If R ₂ , then I〓a=PI〓 ₁ + (1-P) I〓 ₂ ... (4) I〓b = (1-P) I〓 ₁ + PI〓 ₂ ...... (5).

Therefore, the voltage e〓a output to the output terminals P ₄ and P ₅ ,
e〓b is obtained from equations (2), (3), (4), and (5) as e〓a=−R ₁ I〓a=−R ₁ K[Pe〓 ₁ + (1 −P)e〓 ₂ ]=K ₀ [Pe〓 ₁ +(1-P)e〓 ₂ ]...(6) e〓b=-R ₂ I〓b=-R ₂ K[-(1-P)e〓 ₁ +Pe〓 ₂ ] = K ₀ [Pe = ₂ - (1 - P) e = ₁ ] ... (7) However, K ₀ = -R ₁ K = -R ₂ K. e〓a, e〓b are as shown in Figure 4, and 0≦P
When variable within the range of ≦1, e〓a is 90 degrees to 180 degrees,
e〓b is variable in the range of 0 degrees to 90 degrees, and the phase difference between e〓a and e〓b is always maintained at 90 degrees. However, this circuit can only provide a constant phase difference of 90 degrees, and cannot provide an arbitrary phase difference.

When the phase difference is fixed in this way, problems occur as described below.

Firstly, a demodulator 2 as shown in FIG.
When giving the demodulation phases of (R-Y) and (B-Y) to the demodulation axis of 4, the logical demodulation of the chroma signal in the NTSC system is as follows: (R-Y), (B-Y)
The phase difference between the axes may be 90 degrees. however,
In reality, the emission characteristics of the fluorescent paint in cathode ray tubes are not ideal, so in order to achieve optimal color reproduction,
The phase difference between the (RY) and (B-Y) axes is 105 degrees or more.
It is set at 110 degrees.

Therefore, the phase control circuit shown in FIG. 3 has the disadvantage that, as described above, the phase difference between its output signals is fixed, and therefore optimal color reproduction cannot be obtained.

Second, in the chroma signal processing circuit shown in FIG. 2B, subcarriers having a phase difference are input to the APC detector 26 and the killer detector 28. In this case, the phase difference was set to 90 degrees as described above in order to maximize the efficiency of the killer detector 28. Furthermore, such a phase difference is possible because the configuration and operation of the killer detector 28 is substantially the same as that of the APC detector 26.

However, when the input impedance of the killer detector 28 is different from the input impedance of the APC detector 26 due to setting the detection efficiency of the killer detector 28 to be low, or due to a difference in the wiring pattern between these circuits, abnormalities may occur. When a difference in capacity occurs, the phase difference between the two subcarriers may not be exactly 90 degrees.

As a result, in the phase control circuit shown in FIG. 3, the phase difference between its output signals is fixed, so it has the disadvantage that it cannot be corrected to an optimum value.

The present invention has been made in view of the above-mentioned points, and provides a phase control circuit that can arbitrarily variably control the phase of two desired signals while maintaining a predetermined phase difference between the two signals, and that can be easily integrated into an integrated circuit. The purpose is to provide

Embodiments of the present invention will be described below based on the drawings.

FIG. 5 is an explanatory diagram in which signals are expressed as vectors for explaining the principle of the present invention. In Fig. 5, consider three axial directions OA, OB, and OC extending radially from O with the center as O, and the phase of two of these axial directions, for example, the phase angle of axial directions OA and OB is ∠
Display it like AOB and write ∠BOA=∠COB=Θ...(8). In the axial direction OA, vector OA→ ₁ (=A〓 ₁ ), in OB, vector OB→ ₁ (=B〓 ₁ ), OC→
Let us create a signal vector such that (=C〓 ₁ ).

Let A〓 ₁ , B〓 ₁ , B〓 ₂ , and C〓 ₁ be vectors controlled with the following relationship.

That is, A〓 ₁ = (1-P)A〓 ……(9) B〓=PB〓 ……(10) B〓 ₂ = (1-P)B〓 (11) C〓 ₁ =PC〓 ……( 12) Here, OA→=A〓, OB→B=B〓, OC→=C〓,
and |A〓|=|B〓|=|C〓| (13) Let P be a coefficient that varies the range of 0≦P≦1.

Under these conditions, the composite vectors D〓(=OD→) and E〓(=OE→) in the figure are (9), (10), (11
), from formula (12), D〓(1-P)A〓+PB〓...(14) E〓=(1-P)B〓+PC〓...(15), and if P is in the range of 0 to 1 For variable,
(13) and (14) From both equations, D〓 changes from the phase of B〓 to the phase of Å, and E〓 changes by the same angle in the same direction from the phase of C to the phase of B.

Next, find the phase difference ∠E〓−∠D〓=∠EOD between E and D.

First, considering the size of each vector, (9), (10),
From equations (11), (12), and (13), OA ₁ = |A〓 ₁ |=OB ₂ = |B〓 ₂ |……(16) OB ₁ = |B〓 ₁ |=OC ₁ = |C〓 ₁ ｜……(17) becomes.

Furthermore, from equations (16), (17), and (8), △OA ₁ B ₁ = △OB ₂ C ₁ ... (18) ∴C ₁ B ₂ = A ₁ B ₁ ... (19) Therefore, parallel Quadrilateral OC ₁ EB ₂ and parallelogram
OA ₁ DB ₁ is a congruent parallelogram according to equation (19). That is, OE = | E = | = OD = | D = | ... (20) C ₁ E = OB ₂ = OA ₁ = B ₁ D ... (21) Therefore, (17), (20), ( From formula 21), △OEC ₁ = △ODB ₁ ... (22). Therefore, C ₁ OE = B ₁ OD ... (23) Therefore, from both equations (23) and (8), ∠EOD = ∠B ₁ OD + ∠EOB ₁ = ∠C ₁ OE + ∠EOB ₁ = ∠C ₁ OB ₁ = ∠COB=Θ ...(24), and even if the phase of E〓 and D〓 changes, the phase difference is always constant, and the phase difference Θ given in equation (8) is maintained at the beginning. do.

The object of the present invention can be achieved by forming and synthesizing signals having the relationship as described above.

Therefore, if the configuration is as shown in the embodiments shown in FIGS. 6 and 8, the desired purpose can be achieved.

FIG. 6 shows an embodiment of the phase control circuit according to the present invention for providing the above-mentioned vector relationship, in which transistors 51 to 58 constitute a differential amplifier, and the emitters of transistors 51 and 52 are The emitters of transistors 53 and 54 connect current source 60 to transistors 55 and 5.
The emitter of transistor 6 connects current source 61 to transistor 5.
Emitters 7 and 58 are grounded via current sources 62, respectively.

The bases of these transistors 51, 54, 55, 58 are connected to the input terminal _P5 into which the DC control voltage for the phase control signal is input, and the transistors 52, 53,
The base phase control signals 56 and 57 are connected to input terminals _P6 , respectively. transistor 5
The collectors of transistors 3, 55, and 58 are connected to the power supply Vcc via a resistor 63 and to the output terminal _P7 . The collectors of the transistors 52, 54, and 56 are connected to the power supply Vcc via a resistor 64 and to the output terminal _P8 . The collectors of the transistors 51 and 57 are connected to the power supply Vcc.

The operation of the circuit having the above configuration will be explained below.

FIG _. 7 shows _a vector diagram for explaining the operation of the circuit _shown in _FIG . ,6
0,
The current values of 61 and 62 are expressed as vectors as I _A0 I _B1 , I _B2 , and I _C0 , respectively. For convenience of explanation, I〓 _A0 is used as the reference, I〓 _A0 =, and each signal condition is set as ∠I〓 _A0 = −∠I〓 _C0 ……(25), that is, reverse phase, and |I〓 _A0 |= |I〓 _C0 | ...(26) Assume that the amplitudes are equal. Next, the relationship between I〓 _B1 and I〓 _A0 is ∠I〓 _B1 ⊥∠I〓 _A0 ……(27) In other words, it is assumed that there is a right angle relationship, and ∠I〓 _B1
The relationship between and ∠I〓 _B2 is assumed to be ∠I〓 _B1 = ∠I〓 _B2 , or ∠I〓 _B1 = −∠I〓 _B2 (28), which is an in-phase or anti-phase relationship.

FIG. 7 shows the case where the phase of equation (28) is reversed.

Furthermore, it is assumed that the following relationship holds true.

｜I〓 _A0 +I〓 _B2 ｜=｜I〓 _B1 ｜=｜I〓 _C0 +I〓 _B2 ｜……
(29) ｜I〓 _A1 ｜=｜I〓 _B1 ｜=｜I〓 _C1 ｜ ……(30) However, I〓 _A1 = I〓 _A0 +I〓 _B2 , I〓 _C1 = I〓 _C0 + I〓 _B2 Therefore, As is clear from FIG. 7 and equations (25) to (30), the phase difference between I〓 _A1 and I〓 _B1 and the phase difference between I〓 _B1 and I〓 _C1 are equal.

If P is the coefficient that determines the shunt ratio of the differential amplifier under the above conditions, each transistor 51 to 58
The signal current vector generated at the collector of is expressed as follows. PI〓 _A0 , (1-P) I〓 _A0 , (1-P)
I〓 _B1 , PI〓 _B1 , PI _B2 , (1-P)I〓 _B2 (1-P)I〓 _C
0 ,
PI〓 _C0 , therefore, the signal current vectors I〓 _D and I〓 _E flowing through the resistors 64 and 63 can be obtained from the following equations.

I〓 _D = (1-P) I〓 _A0 +PI〓 _B1 + (1 -P) I〓 _B2 = (1-P) (I〓 _A0 +I〓 _B2 ) +PI〓 _B1 = (1-P) I〓 _A1 +PI〓 _B1 ...(31) I〓 _E = (1-P) I〓 _B1 +PI〓 _B2 +PI〓 _C0 = P(I〓 _C0 +
I〓 _B2 ) + (1 - P) I〓 _B1 = PI〓 _C1 + (1 - P) I〓 _B1 ... (32) When these signal current vectors correspond to the vectors in Fig. 5, I〓 _A1 = A〓, I〓 _B1 = B〓, I〓 _C1 = C〓...(38) Therefore, equations (31) and (32) correspond to equations (14) and (15), respectively. , the effects of the present invention found in FIG. 5 are obtained as voltage signals from the output terminals P ₇ and P ₈ .

Further, in FIG. 7, vectors are expressed as ∠I〓 _B1 =∠I〓 _B2 , but it goes without saying that the same effect can be obtained even if ∠I〓 _B1 = ∠I〓 _B2 .

FIG. 8 shows the current sources 59, 60, and
61 and 62, which are circuits that supply signals to the embodiment shown in FIG. In the figure, numerals 65 to 69 are transistors having approximate characteristics, and the emitters of transistors 65 and 66 connect current source 70 to transistors 67 and 6.
Emitters 8 and 69 are grounded via current sources 71, respectively, and constitute a differential amplifier.

The base of the transistor 65 receives the signal voltage e〓 ₃ from one output terminal of the phase shift circuit 72, and the base of the transistor 67 receives the signal voltage e〓 ₄ from the other output terminal of the phase shift circuit 72. It is configured as follows. The phase shift circuit 72 is configured so that the phase difference between the signal voltages e〓 ₃ and e〓 ₄ is 90 degrees.

Further, the base of the transistor 66 is connected to the positive electrode of a bias power supply 73 whose negative electrode is grounded.

The bases of the transistors 68 and 69 are connected to the positive electrode of a bias power supply 74 whose negative electrode is grounded.

It is assumed that the same amount of bias is applied to the bases of the transistors 66, 68, and 69 by the bias power supplies 73 and 74.

The collector of transistor 65 is transistor 5
The collector of transistor 66 is connected to the emitters of transistors 57 and 58, and the collector of transistor 67 is connected to the emitters of transistors 53 and 52.
The emitter of transistor 68 is connected to the emitter of transistor 54, the collector of transistor 68 is connected to the emitters of transistors 55 and 56, and transistor 69 is connected to power supply Vcc.

The operation of the above embodiment will be explained.

FIG. 9 is a vector diagram for explaining the operation of the above embodiment. In the figure I〓 _C19 , I〓 _C20 , I〓 _C22 , I〓 _C
22 is the collector current I _C19 of transistors 65 to 68,
It is a vector representation of I _C20 , I _C21 , and I _C22 ,
The collector current of transistors 65 and 66 is ∠I〓 _C19
＝−∠I〓 _C20 , ｜I〓 _C19 ｜=｜I〓 _C20 ｜. and,
As shown in Figure 7, ∠I〓 _A0 =∠I〓 _C0 , |I〓 _A0 ｜=｜I〓 _C0 |
will be obtained. Here, ∠e〓 ₃ = ∠I〓 _A0 .

Next, in the differential amplifier constituted by transistors 67, 68, 69, transistors 67, 6
When the emitter areas of 8 and 69 are respectively A ₂₁ , A ₂₂ , and A ₂₃ , the respective emitter signal currents are I _E21 , I _E22 ,
If I _E23 , I _E21 : I _E22 : I _E23 = A ₂₁ : A ₂₂ : A ₂₃ , and I _C21 ≒ I _E21 , I _C22 ≒ I _E22 , I _C23 ≒ I _E23
(However, I _C21 , I _C22 , and I _C23 are transistors 67,
68, 69 collector signal current).
The ratio of I〓 _C21 and I〓 _C23 can be selected depending on the area. Also, the currents I ₀₃ and I ₀₄ of the current sources 70 and 71
By appropriately selecting the magnitude of and the magnitude of the signal e ₃ e ₄ , I〓 _C19 , I〓 _C20 , I〓 _C21 , I〓 _C22 shown in Fig. 6 can be obtained as I〓 _A0 , I〓 _C0 , It can be supplied as the conditions of I〓 _B1 and I〓 _B2 .

FIG. 10 shows the current sources 59, 60, and
This shows other embodiments of Nos. 61 and 62.

The emitters of transistors 75, 76 and 77 and the emitters of transistors 78 and 79 are grounded via current sources 80 and 81 to form a differential amplifier. The base of the transistor 75 is grounded through a series circuit of a signal source 81 of signal voltage e ₃ and a bias power supply 83, and also through a series circuit of a resistor 84 and a capacitor 85. The bases of the transistors 76, 77, and 78 are connected to a connection point between a resistor 84 and a capacitor 85. The base of the transistor 79 is grounded via a bias power supply 86.

Therefore, transistors 75, 77, 78, 79
The collector currents of the transistors are set as I _C24 , I _C2E , I _C26 , and I _C27 , and the collector of the transistor 76 is connected to the power supply Vcc.

FIG. 11 is a vector diagram showing the signals of each part of the embodiment shown in FIG. 10 as vectors and explaining the operation of this embodiment. In the figure, the vector
I〓 _C24 , I〓 _C26 , I〓 _C27 , I〓 _C28 are transistors 75
,7
7, 78, 79 collector currents I _C24 , I _C26 ,
I _C27 and I _C28 are shown respectively. Also, the vector e〓 ₅ indicates the output voltage e〓 ₅ of the signal source 82, and the vector
e〓 ₆ indicates the voltage e ₆ obtained by delaying the phase by the resistor 84 and the capacitor 85. The vector e〓 ₇ is obtained from e〓 ₇ = e〓 ₅ − e〓 ₆ .
Actually, the collector currents I _C24 and I _C26 of the differential amplifier constituted by the transistors 75, 76, and 77 are determined by the differential voltage e ₇ between e ₅ and e ₆ .

Therefore, vector-related signals as shown in FIG. 11 can be obtained, and each collector current I _C24 , I _C26 ,
I _C27 and I _C28 are current sources 60, 61, 59, and
62 current values I _B1 , I _B2 , I _A0 , and I _C0 can be supplied.

FIG. 12 shows another configuration example of the embodiment shown in FIG. 10, in which the base of transistor 77 is connected to the base of transistor 75, and other configurations remain unchanged. In this case, ∠
I〓 _C24 =∠I〓 _C26 , and a relationship is obtained in which the phase difference between the final vectors I〓 _E and I〓 _D obtained in Fig. 7 is smaller than 90 degrees.

In addition to the embodiment described above, various other means for supplying signals to the embodiment of FIG. 6 can be considered. Therefore, the characteristics of each signal in these signal supply means are as follows.

That is, the following condition is obtained between the four signals I〓 _A0 , I〓 _C0 , I〓 _B1 , and I〓 _B2 .

First, I〓 _A0 and I〓 _C0 have opposite phases and the same amplitude.

Second, I〓 _B1 and I〓 _B2 are in phase or out of phase, and either one has a smaller amplitude than the other.

Third, I〓 _A0 , I〓 _C0 and I〓 _B1 , I〓 _B2 are in a right-angled relationship.

In addition to the above conditions, all of the circuits shown in FIGS. 6, 8, 10, and 12 are suitable for integration into integrated circuits, and stable operation can be obtained.

FIG. 13 shows another circuit configuration example of the embodiment shown in FIG. 6.

Transistors 91 and 92, 93 and 94, 9
5 and 96 have their emitters connected in pairs and are grounded via current sources 97, 98, and 99 to form three differential amplifiers.

The bases of the transistors 91, 94, and 95 are input terminals into which a DC voltage, which is a phase control signal, is input.
Connected to P ₉ and also transistors 92, 93, 96
The base of is connected to an input terminal _P10 which receives a DC voltage as a phase control signal. A control signal is applied to the input terminals P ₉ and P ₁₀ to determine the current shunt ratio of the differential amplifier.

The collectors of the transistors 92 and 94 are connected to a resistor 1.
It is connected to the power supply Vcc via 00 and also to the output terminal _P11 . Similarly, the collectors of transistors 93 and 95 are connected to the power supply Vcc via a resistor 101 and to the output terminal _P12 . Collectors of transistors 91 and 96 are connected to power supply Vcc.

In this example, the current shunt ratio is P, and each collector current is expressed as a vector, PI〓 _A1 , (1-P) I〓 _A1 ,
Assuming (1-P)I〓 _B1 , PI〓 _B1 , PI〓 _C1 , and (1-P)I〓 _C1 , this can be explained using the vector diagram shown in FIG.

The amplitude and phase relationships are the same as in FIG. 7. That is, the amplitudes of each signal vector are equal to each other, and
It is assumed that the phase difference between I〓 _A1 and I〓 _B1 and the phase difference between I〓 _B1 and I〓 _C1 are equal. The signals output to the terminals P ₁₁ and P ₁₂ due to the signals having these conditions are as follows. That is, I〓 _D = (1-P) I〓 _A1 + PI〓 _B1 I〓 _E = (1-P) I〓 _B1 + PI〓 _C1 , which is the same as equations (31) and (32), and is shown in Figure 6. The same effects as in the example can be obtained.

FIG. 14 shows a circuit for supplying current values I _A1 , I _B1 , and I _C1 of current sources 97, 98, and 99 in the embodiment of FIG. 13, that is, a circuit for supplying signals to the embodiment of FIG. 13. This shows the circuit. 14th
In the figure, numerals 105 to 110 are transistors, and transistors 105, 106, 10
The emitters of transistors 7 and 108 are grounded via a current source 111, and the emitters of transistors 109 and 110 are grounded via a current source 112, respectively.

The base of the transistor 105 is grounded through a series circuit of a signal source 113 and a bias power supply 114, and also through a series circuit of a resistor 115 and a capacitor 116. The connection point between the capacitor 116 and the resistor 115 is connected to the bases of the transistors 106, 107, 108, and 109.

The base of transistor 110 is grounded via bias power supply 117.

The collector of transistor 105 is connected to the emitters of transistors 93 and 94, the collector of transistor 109 is connected to the emitters of transistors 91 and 92, and the collector of transistor 110 is connected to the emitters of transistors 95 and 96, respectively.

The embodiment having the above configuration operates as follows.

FIG. 15 is a vector diagram showing the signals of each part of the embodiment of FIG. 14 as vectors and explaining its operation. Therefore, the explanation will be given with reference to this figure.

The signal e〓 ₈ of the signal source 113 is the transistor 105
The resistor 115 and capacitor 116 provide a phase-delayed signal _e〓9 , which is supplied to the transistors 106-109. Then, the signals e〓 ₈ and
An in-phase signal current flows through the difference vector e〓 ₁₀ or −e〓 ₁₀ of e〓 ₉ as shown. That is, I〓 _C35 , I〓 _C36 ,
I〓 _C37 , I〓 _C38 , flow, and these are each transistor 1
05, 106, 107, and 108 collector currents. I〓 _C35 is in phase with e〓 ₁₀ , I〓 _C36 , I〓 _C37 , I
〓 _C38 is in phase with −e 〓 ₁₀ . Furthermore, each transistor 1
The magnitude of the current values 05 to 108 is determined in proportion to the ratio of the emitter areas of these transistors.

The collector signal currents I _C39 and I _C40 of the transistors 109 and 110 are in phase and anti-phase with the signal e〓 ₉ , and I〓 _C37 and I〓 _C38 are added to these, respectively (I〓 _C39 +
I〓 _C37 ), (I〓 _C40 +I〓 _C36 ) and I〓 _C35 respectively, I〓 _A1
, I〓 _B1 , I〓 _C1 are supplied by current sources 97, 98, 99 in FIG. At this time, circuit constants, etc. are determined so that the relationships among I〓 _A1 , I〓 _C1 , and I〓 _B1 are the same as the vectors with the same symbols in FIG.

As described above, according to the present invention, there is a means for setting the phase of a signal to a desired phase difference, and a means for arbitrarily controlling the phase of this signal while maintaining this phase difference. This has the advantage that a signal that can be phase controlled while maintaining the phase difference is obtained, and the circuit constants can be easily set to obtain a desired phase difference, so that the number of design steps can be reduced. Furthermore, it is easy to integrate the circuit, and the number of parts can be reduced by reducing the number of parts around the circuit.

[Brief explanation of the drawing]

Fig. 1 is a block diagram and vector diagram showing the basic configuration of a conventional phase control circuit, Fig. 2 is a block diagram showing a chroma signal processing circuit having a hue control circuit, and Fig. 3 is a conventional phase control circuit. FIG. 4 is a vector diagram illustrating the operation of the example circuit shown in FIG. 3. FIG. 5 is a vector diagram illustrating the principle of the present invention. FIG. The circuit diagram shown in FIG. 7 is a vector diagram for explaining the operation of the embodiment of FIG. 6, and FIG. 8 is a circuit diagram showing a signal supply circuit that supplies signals to the embodiment of FIG. 6. 9 is a vector diagram for explaining the operation of the embodiment shown in FIG. 8, FIG. 10 is a circuit diagram showing a signal supply circuit that supplies signals to the embodiment shown in FIG. 6, and FIG. 12 is a circuit diagram showing another embodiment of the signal supply circuit that supplies signals to the embodiment of FIG. 6, and FIG. 13 is a vector diagram for explaining the operation of the embodiment of the present invention. 14 is a circuit diagram showing a signal supply circuit that supplies signals to the embodiment of FIG. 13, and FIG. 15 is a vector diagram for explaining the operation of the embodiment of FIG. 14. It is a diagram. 51 to 58, 65 to 69, 75 to 79,
91 to 96, 105 to 110...transistor, 59 to 62, 70, 71, 80, 81, 9
7 to 99, 111, 112... current source, 73,
74, 83, 86, 114, 117... Bias power supply, 84, 115... Resistor, 85, 116...
capacitor.

Claims (1)

[Claims] 1. A means for generating a first vector signal, and a second vector signal having the same or opposite phase with the first vector.
means for generating a signal of a vector, and a third vector that is perpendicular to the first vector.
means for generating a fourth vector signal having an opposite phase to the third vector; means for generating a fifth vector signal located between the vectors, and generating a sixth vector signal located between the two vectors by vector-synthesizing each of the second and fourth vector signals. voltage control means for generating first and second control voltages whose magnitudes change relatively; and a signal whose magnitude is controlled by the first control voltage for the first vector signal; , means for vector-synthesizing the signal of the fifth vector with a signal whose magnitude is controlled by the second control voltage to obtain a first output signal; and means for vector-synthesizing the signal whose magnitude is controlled by the control voltage and the signal of the sixth vector whose magnitude is controlled by the first control voltage to obtain a second output signal. . A phase control circuit, characterized in that the phase of the first and second output signals can be controlled while maintaining a predetermined phase difference. 2 each having a first and a second transistor pair, the emitters of each pair are connected in common, and the signals of the first, second, third, and fourth vectors are respectively supplied to each common emitter; applying the first control voltage to the bases of the first, second, third, and fourth differential amplifiers, and the first transistors of the first, second, third, and fourth differential amplifiers; means for applying the second control voltage to the bases of each second transistor of the first, second, third, and fourth differential amplifiers; and a first control voltage of the first differential amplifier. means for synthesizing the collector output of the transistor, the collector output of the second transistor of the second differential amplifier, and the collector output of the second transistor of the third differential amplifier to obtain a first output signal. and a collector output of the second transistor of the first differential amplifier, a collector output of the first transistor of the second differential amplifier, and a collector output of the first transistor of the fourth differential amplifier. 2. The phase control circuit according to claim 1, further comprising means for synthesizing the signals to obtain a second output signal. 3. Fifth and fifth transistors each having a first and a second transistor pair, the emitters of each pair are commonly connected, and the signals of the first, fifth and sixth vectors are supplied to each common emitter, respectively. 6. a seventh differential amplifier; means for applying the first control voltage to the bases of the first transistors of the fifth, sixth, and seventh differential amplifiers; , means for applying the second control voltage to the base of each second transistor of the seventh differential amplifier; a collector output of the first transistor of the fifth differential amplifier; means for synthesizing the collector output of the second transistor of the amplifier to obtain a first output signal; the collector output of the second transistor of the fifth differential amplifier and the first output signal of the seventh differential amplifier; 2. The phase control circuit according to claim 1, further comprising means for synthesizing the collector outputs of the transistors to obtain a second output signal.