KR910007843B1 - Coring circuit - Google Patents

Abstract

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Description

Core ring circuit

1 is a block diagram of a contour correction circuit including a core ring circuit according to the present invention.

FIG. 2 is a waveform diagram illustrating the operation of the circuit of FIG. 1. FIG.

3 and 4 are block diagrams and configuration diagrams of a contour correction circuit including a conventional core ring circuit.

5 is a waveform diagram illustrating the operation of the circuit.

* Explanation of symbols for main parts of the drawings

1: delay line 2: adder

10: first differential amplifier 11, 12: first and second slice circuits

13 slice level setting circuit 14 second differential amplifier

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a core ring circuit embedded in a contour correction circuit such as a video tape recorder, a video disk, a video camera, and used to remove high frequency noise components of a contour correction signal or to remove a small amplitude output of a color signal. will be.

Since the reproduced luminance signal of the video tape recorder and the luminance signal such as a video camera are limited to, for example, a band of about 3 MHz, there is a drawback in lacking sharpness in the contour portion.

Therein, in the video apparatus, the outline of the luminance signal is corrected using the outline correction circuit. However, only by correcting the contour of the luminance signal in the contour correction circuit, since the contour correction signal contains a high frequency noise component, the S / N ratio is lowered when the contour correction signal is applied to the delayed luminance signal. Throw it away. For this reason, in general, a core ring circuit is incorporated in the contour correction circuit to remove high frequency noise components of the contour correction signal.

An example of the contour correction circuit is shown in FIG. 3, and the delay line 1 is connected to the input terminal A via the input resistance Rin. The input side of the core ring circuit 3 is connected to the input / output side of the delay line 1, and the output side of the core ring circuit 3 and the output side of the delay line 1 are connected to the adder 2. It is. The core ring circuit 3 is provided with the differential amplifiers 4 and 5, as shown in FIG. The differential amplifier 4 is composed of NPN transistors Q ₁ and Q ₂ , and the emitters of these transistors Q ₁ and Q ₂ are connected via a resistor R ₁ and grounded through a constant current source.

The bases of these transistors Q ₁ and Q ₂ are connected to the input side and the output side of the delay line 1, and the collector to obtain the output is connected in parallel to the power supply Vcc via a resistor R ₃ . The other differential amplifier 5 is composed of NPN transistors Q ₃ and Q ₄ , and the emitters of these transistors Q ₃ and Q ₄ are connected via a resistor R ₂ and grounded via a constant current source. Of transistor Q ₃ is connected to the base to the base of the transistor Q _2, In addition, the collector is connected to the power source Vcc. The base of transistor Q ₄ is connected to the base of transistor Q ₁ , and its collector is connected to the collector of transistor Q ₂ via a resistor R ₄ . So, the collector of the transistor Q ₄ is connected, and the base of the NPN transistor Q ₅ for amplification, are connected to the collector and emitter of power supply Vcc and an adder (2) of the transistor Q _5.

However, the input terminal A, so that the luminance signal shown in claim 5a is also inputted, the delay line (1) is output and the luminance signal delayed by td degrees claim 5b, in this delayed luminance signal transistor Q _2, Q ₃ It is entered into the base. In addition, since the output terminal of the delay line 1 is set to high impedance, a signal in which the reflection signal delayed by 2td and the signal of FIG. 5A is added to the input terminal of the delay line 1 is generated (FIG. 5C). The signal of Fig. 5C is input to the bases of the transistors Q ₁ and Q ₄ .

However, the input dynamic range of the differential amplifier 5 consisting of the transistor Q _3, Q ₄ is the FIG. 5b, is sufficiently larger than the degree 5c voltage level difference of each of the delayed luminance signal. In contrast, the input dynamic range of the differential amplifier 4 constituted by the transistors Q ₁ and Q ₂ is set by the noise component to be removed within the range of the voltage level difference. The voltage gain of the differential amplifier 5 on the other hand is (R ₃ + R ₄ ) / {R ₂ +2 (KT / q)}, and the voltage gain of the other differential amplifier 4 is R ₃ / {R. ₁ +2 (KT / q)}. Therefore, the voltage gains of the two differential amplifiers 4 and 5 are set the same. KT / q also shows the thermal voltage.

Therefore, when the 2td delayed luminance signal of FIG. 5c is input to the bases of the transistors Q ₁ and Q ₄ , and the td delayed luminance signal of FIG. 5b is input to the transistors Q ₂ and Q ₃ , the differential amplifier 4, Since the output (collector voltage) of (5) is reversed and synthesized, the high frequency noise component is canceled, and the contour correction signal shown in FIG. 5d is output from the emitter of the transistor Q ₅ . That is, the signal component whose amplitude is larger than the dynamic range of the differential amplifier 4 is converted into low impedance by the transistor Q ₅ and output as a contour correction signal. Therefore, in the adder 2, the contour correction signal from which the high frequency noise component has been removed is added to the brightness of FIG. 5b, and therefore, the corrected brightness signal of FIG. 5e is output from the output terminal B. FIG.

By the way, the core ring circuit has a problem that the high-frequency small amplitude signal is removed in addition to the high frequency noise component. Therefore, if the S / N ratio of the input signal is good, it is desirable to change the input dynamic range of the differential amplifier to make the base creep width small or zero, and if the S / N ratio is bad, increase the base creep width. Do. However, the conventional core ring circuit, and the emitter of the emitter current I ₁ (= I _2), the transistors Q ₃ (Q ₄₎ of the transistor Q ₁ (Q ₂₎ in order to change the input dynamic range of emitter current I ₃ You need to change (= I ₄ ). Therefore, when the emitter current is changed in this way, there is a drawback that the gain of the differential amplifiers 4 and 5 decreases.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and inputs the in-phase and inverse-phase signals output from the first differential amplifier to the first and second slice circuits set at the desired slice levels by the slice level setting circuit. It is an object of the present invention to provide a corering circuit having a configuration of synthesizing and outputting in-phase and reversed-phase signals sliced in these slice circuits by a second differential amplifier.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an example in which the core correction circuit of the present invention is incorporated in the contour correction circuit. The delay line 1 is connected to the input terminal A via the input resistance Rin, and an adder (1) is provided on the output side of the delay line 1. 2) is connected.

The core ring circuit of the present invention is provided with a first differential amplifier 10, which is connected to an NPN transistor Q ₁₁ , Q ₁₂ having a base connected to an input side and an output side of a delay line 1, respectively. Is formed. The collectors of these transistors Q ₁₁ and Q ₁₂ are connected to the power supply Vcc via resistors R ₁₁ and R ₁₂ having the same resistance value, and each emitter is connected via a resistor R ₁₃ . The first and second slice circuits 11 and 12 are connected to each collector of the transistors Q ₁₁ and Q ₁₂ . The first slice arc 11 comprises a NPN transistor Q ₁₃ having a base connected to the collector of the transistor Q ₁₁ via a base resistor R ₁₉ , and a collector and emitter connected to the collector and emitter of the transistor Q ₁₃ . It is formed of a transistor Q _14, which may both be the collector connected to the power supply Vcc. Second slice circuit 12 is of the same configuration has to be NPN transistors Q _15, Q _16, Q ₁₆ of the transistor base via a base resistor R ₂₀ connected to the collector of the transistor Q _12. The bases of the NPN transistors Q ₁₇ and Q ₁₈ are connected to the collectors of the transistors Q ₁₁ and Q ₁₂ constituting the first differential amplifier 10. Each collector of these transistors Q ₁₇ , Q ₁₈ is connected to a power supply Vcc, and each emitter is connected to each other via an additional resistor R ₁₄ , R ₁₅ .

These resistors R ₁₄ and R ₁₅ have the same resistance value, and the base of the NPN transistor Q ₁₉ constituting the slice level setting circuit 13 is connected to the connection point. The collector of this transistor Q ₁₉ is connected to the power supply Vcc, and the emitter is connected to the emitter of the NPN transistor Q ₂₁ . The base of the transistor Q ₂₁ is connected to a collector, and the emitter of another NPN transistor Q ₂₀ is connected to the collector. The base of the transistor Q ₂₀ is connected to the collector, which is commonly grounded to the bases of the transistors Q ₁₄ and Q ₁₅ of the first and second slice circuits 11 and 12, and also has a constant current. It is connected to the power supply Vcc via. The collector of the PNP transistor Q ₂₂ is connected to the connection points of the resistors R ₁₄ and R ₁₅ for addition. The transistor Q ₂₂ has an emitter that is connected to the power source Vcc, constitute a current mirror circuit together with another PNP transistor Q _23. The collector of the NPN transistor Q ₂₄ is connected to the collector of the transistor Q ₂₃ , and the power supply V ₀ is connected to the base of the transistor Q ₂₄ . The emitter of the transistor Q ₂₄ is connected to the emitter of the NPN transistor Q ₂₅ via a resistor R ₁₆ . In the transistor Q _25, the collector is connected to the power supply, and the base is connected to the control terminal C.

A second differential amplifier 14 is formed in the emitters of the transistors Q ₁₃ and Q ₁₄ of the first slice circuit 11 and the emitters of the transistors Q ₁₅ and Q ₁₆ of the second slice circuit 12. The bases of the NPN transistors Q ₂₆ and Q ₂₇ are connected. Each collector of the transistors Q ₂₆ , Q ₂₇ is connected to the power supply Vcc via an integration and a resistor R ₁₈ , and each emitter is connected to each other at a resistor R ₁₇ . The collector of transistor Q ₂₇ has a base of an NPN transistor Q ₂₈ is connected to the impedance transformation. The transistor Q ₂₈ is the collector is connected to the power supply Vcc, is connected to the emitter of the adder (2).

The emitters of the transistors Q ₁₁ to Q ₁₉ , the transistors Q ₂₁ , and the transistors Q ₂₄ to Q ₂₈ are grounded through a constant current source, respectively. Thus, the emitter currents of these transistors have a relationship of I ₁₁ = I ₁₂ , I ₁₃ = I ₁₄ , I ₁₅ = I ₁₆ , I ₁₇ = 1/2 · I ₈ , and I ₂₀ = I ₂₁ .

Next, the operation of the core ring circuit of the present invention will be described with reference to the delay line 1 and the like.

When the input terminal A in the first 2a-degree luminance signal, first and the transistor Q _11, the degree of claim 2c signal of the differential amplifier 10 of the first type, and the transistor Q ₁₂ is because the luminance signals td retardant 2b separate input The differential voltages of these signals are amplified so that the in-phase signal S of the waveform shown in FIG. 2d is collected in the collector of transistor Q ₁₁ , and the reverse phase signal S 'of the waveform shown in FIG. 2e is collected in the collector of transistor Q ₁₂ , respectively. Is output. Therefore, these in-phase and reversed-phase signals S and S 'are the bases of the transistors Q ₁₃ and Q ₁₆ of the first and second slice circuits 11 and 12 and the transistor Q ₁₇ of the slice level setting circuit 13. is input to each base of Q _18.

However, when a sufficiently high voltage is not added to the control terminal C by (V ₀ + R ₁₅ · I ₁₉ ), the collector current of the transistor Q ₂₄ becomes zero. Therefore, the collector current of the transistors Q ₂₀ and Q ₂₂ also becomes zero. As will be described later, the base voltages of the transistors Q ₁₄ and Q ₁₅ of the first and second slice circuits 11 and 12 are maintained at the reference voltage Vs of the signals of 2f and 2g degrees. Thus, higher than the portion in the first slice circuit 11 in because the phase signal to the base of the transistor Q ₁₃ S been input, the emitter, the base (slice level) of the transistor Q ₁₄ of the phase signal S of the transistor Q ₁₃ For example, a portion higher than the reference potential Vs of the in-phase signal S is output as the slice signal S ₁ (see also 2f). Further, in the second slice circuit 12, the inverted signal to the transistor Q ₁₆ base S is the higher part than the reference potential Vs of "is because it is input, the transistor Q ₁₆ of the emitter, the reverse phase signal S 'slice circuit S ₁ Output as' (see also 2g).

The slice signals S ₁ , S ₁ ′ are input to respective bases of the transistors Q ₂₆ , Q ₂₇ of the second differential amplifier 14. Accordingly, since these sliced signal S _1, the voltage difference of the S ₁ 'is added to the base of transistor Q _28, the emitter of the transistor Q ₂₈ are outputted to the contour correction signal as shown in the 2h Figure, the signal adder (2 Is supplied. Therefore, at the output terminal B, the corrected luminance signal shown in FIG. 2i is output.

On the other hand, for example, when a control voltage smaller than the power supply V ₀ is added to the control terminal C, the emitter current of the transistor Q ₂₄ increases and the collector current of the transistor Q ₂₃ increases through the resistor R ₁₆ . Accordingly, even increasing the collector current of the transistor Q _22, and supplied to the connection point of the added resistors R _14, R ₁₅ for. On the other hand, these resistors R ₁₄ and R ₁₅ cancel out by adding the low-impedance in-phase signal S and the reversed-phase signal S 'which have been converted by the transistors Q ₁₇ and Q ₁₈ . Thus, when the collector current of transistor Q ₂₂ is zero, a voltage lower than the reference voltage Vs by a voltage between the base emitters of transistors Q ₁₇ or Q ₁₈ is supplied to the base of transistor Q ₁₉ .

By the way, the transistors Q _19, Q _21, Q ₂₀ acts as a level shift circuit for compensating for the transistor Q _17, deterioration of the base emitter voltage of Q _18. Therefore, the reference voltage Vs is supplied to the bases of the transistors Q ₁₄ and Q ₁₅ . Next, when the collector current in transistor Q ₂₂ Ic cylinder by, by the collector current Ic voltage shares (2/1 R ₁₄ · Ic) increases the base voltage of transistor Q ₁₉ as by, the base voltage of transistor Q ₁₉ The base potentials of the transistors Q ₁₄ and R ₁₅ of the first and second slice circuits 11 and 12 rise by the rising share. That is, the slice level rises by 1 / 2R ₁₄ · Ic voltage. Therefore, in the emitters of the transistors Q ₁₃ and Q ₁₈ , a portion higher than the slice level shown by broken lines is output as the slice signals S ₁ and S ₁ ′, as shown in FIGS. 2f and 2g, so that these slice signals S _By inputting ₁ , S ₁ 'to the second differential amplifier 147, the contour correction signal shown in FIG. 2h' is obtained. In other words, the contour correction signal is obtained by removing the high frequency noise components by arbitrarily changing the slice level without lowering the gain.

In the above embodiment, since the core ring circuit is composed of a transistor and a resistor without using a capacitor or the like, the integrated circuit can be easily formed.

According to the present invention, the in phase and reverse phase signals output from the first differential amplifier are input to the first and second slice circuits, and the slice levels of these slice circuits are converted to the S / N ratios of the input signals in the slice level setting circuit. Correspondingly changed, the common-phase and reverse-phase signals output from the slice circuits are synthesized by the second differential amplifier and outputted, so that high-frequency noise components and unnecessary small amplitude components of the input signal can be removed without reducing the gain. A core ring circuit can be provided.

Claims (1)

A first differential amplifier 10 for outputting the difference between the input signals as in-phase and inverse phase signals, first and second slice circuits 11 and 12 for sliceting the in-phase and inverse phase signals at desired levels, respectively; A slice level setting circuit 13 for setting slice levels of the first and second slice circuits, and a second differential amplifier 14 for synthesizing and outputting the sliced in-phase and reversed-phase signals. Core ring circuit.

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