JPS63144269A - Logic circuit testing device - Google Patents

Abstract

PURPOSE:To facilitate the generation of data and to accurately allow a timing signal to coincide with the time of logic simulator output data by controlling a FF with the outputs of fine delay parts which is obtained by delaying timing signals from respective memories. CONSTITUTION:Timing information and counting information to be generated are stored in memories 23, 24, and 25 corresponding to the counting result of a reference signal counting part 22 which counts a reference signal from a reference signal generation part 21. The timing signals outputted from the memories 23 and 24 are delayed by fine delay parts 41 and 42 according to delay information read out of a memory. The FF 49 is set and reset with the outputs of the fine delay parts 41 and 42 and the output of the FF 49 is supplied as a test signal to the logic circuit to be tested. Then when the counted value of the counting part 22 reaches the stored timing of the memory 25, the delay information is read out of the memory 25 to output the timing signal, which is delayed by a fine delay part 43 and supplied to a comparator 51. here, it is decided through the comparator 51 whether the output of the circuit 14 has a prescribed logic level or not.

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a logic circuit testing device suitable for testing logic circuits, particularly large-scale, SI-based logic circuits.

``Prior Art'' As shown in FIG. The logic test button is also supplied to the logic waveform shaping section 12, and the input logic test button is converted into an NRZ waveform according to the AC characteristics of the logic circuit under test 14.

Waveform shaping to RZ waveform etc. and driver 15? : to the corresponding input pin of the logic circuit under test 14.

On the other hand, the output bump from the output bin of the logic circuit under test 14 is compared with the logic level vH9vL by the comparators 16 and 17, and is shaped into a logic level bump (2). The logical comparison is made with the expected value of the bang from the bang generator 11, and it is determined whether the logic circuit under test 14 is a good product or a defective product.Comparator 1
The timing of converting to the logic level in 6.17 and the timing of determining the comparison result in the logic comparison control section are performed by each timing signal from the timing generator 13, respectively.

When a logic LSI is designed, real-time operation is simulated using a logic simulator to check whether it operates correctly. The output data of the logic simulator includes, for example, the state of each input pin and the state of each output pin at each time, as shown in FIG. 5C. Conventionally, the input pin of the logic circuit under test 14 in the output data of this logic simulator (: A logic test slam that does not include time information that should be generated by the button generator 11 from the applied test button and a timing generator 13 are generated. For example, as the logic circuit under test becomes more complex, there are types of logic button cycles of, for example, 2:5.fiK. The blue report requires about 32 bits, and the phase of the timing clock is about 64, so it requires an extremely large amount of 1F (250K In addition, it is difficult to read out this data in real time and control the timing phase.

By referring to the output data of the logic simulator from this point of view, we divide the relatively side-by-side slams into groups, and then divide them into groups, and then divide them into logic test bumps that represent the groups, and the timing and timing.
The test was conducted after creating an expected value. For this reason, it takes a lot of time to group them and create each button, and furthermore, because the test is conducted with a slight deviation from the actual data,
It was not possible to conduct an accurate test.

"Means for Solving the Problems" According to the present invention, the reference signal from the reference signal generating section is counted by the reference signal counting section. Timing information and delay to be generated corresponding to the counting result of the reference signal counting section ii
# information is stored in the third memory at least ml and $2°, respectively. When the count value of the reference signal counter reaches the storage timing of the first and second memories [Blue 1%j+2, respectively,
1st each. The second reading means reads the first. The delay information is read from the second memory and the timing signal is output.

The timing signal output from the first memory is delayed by the first minute delay section according to the delay information C read out from the first memory, and the timing signal output from the second memory is similarly delayed by the second minute delay section. The delay is performed according to the delay information read from the second mailbox. These first. The flip-flops are set and reset controlled by each output of the second minute delay section.

The output of the flip-flop is supplied to the logic circuit under test as a test signal. Further, when the count value of the reference signal counter becomes the timing information stored in the third memory, the third reading means reads the delay information from the third memory and outputs a timing signal, and the timing signal is transmitted to the third minute delay section. is delayed according to the delay information read from the third memory. A comparator is operated by the output of the third minute delay section, and the comparator C: is supplied with the output of the logic circuit under test, and it is determined whether or not this is at a predetermined logic level.

The reference signal counting section and the first. By the second memory, the first and second minute delay sections, and the flip-flop.

A test signal with the desired waveform and timing is obtained, but the timing of the leading edge of the test signal.

The timing of the trailing edge can be made directly by looking at the logic simulator output data and depending on the value shown there.Similarly, it can be determined from the output of the S3 minute delay section. The desired timing can also be created directly by looking at the output data of the logic simulator.For these reasons, it is possible to perform the most suitable test for the logic circuit under test. It is also extremely easy to prepare.

"First Embodiment" FIG. 1 shows a first embodiment of the present invention. A reference signal 1 having a constant frequency is generated from a reference signal generating section 21, and the reference signal is counted by a reference signal counting section 22. On the other hand, first to fourth memories 23 to 26 are provided respectively, timing information and delay information are stored in these first to fourth memories 23 to 26, and the counted value of the reference signal counting section 22 is calculated at the stored timing. When it comes to information, it reads the delay information from the memory and outputs the timing signal.

For example, the first to fourth memories 23 to 26 are the reference signal counting section 2
The count value of 2 is read out as an address.

In the first to fourth memories 23 to 26, 1115 is stored as timing information at the address position where the timing signal should be output, and MO'' is stored at the other addresses. Also, the address where 1'' is stored Also stores delay information. 1st to 4th memories 23 to 26 to 11
” is read out.

The readout outputs are output to terminals 31 to 34, respectively,
The outputs of these terminals 31-34 are the gates 35-3, respectively.
8. The gates 35 to 38 (: are input with a reference signal from the reference signal generation section 21. Therefore, for example, when timing information @1'' is read from the memory 23, the reference signal is passed through and output from the gate 35 as a timing signal. be done.

Each output timing signal of gates 35 to 38 is 4
1 to 44 are input. On the other hand, the delay information read from the memories 23-26 is supplied to the minute delay units 41-44 as a delay amount control signal through terminals 45-48, respectively.

For example, in the minute delay section 41, the timing signal from the gate 35 is delayed in accordance with the delay information (==) of the terminal 45 and output.

This amount of delay is a delay within the period of the reference signal.

When delaying digitally, the minimum unit of delay is determined according to the time resolution (:) that determines the front of the test signal.

A flip-flop 49 is controlled to be set or reset by each output of the minute delay sections 41 and 42, and the output of the flip-flop 49 is supplied as a test signal to one input pin of the logic circuit under test 14 through the driver 15. 1 = Although not shown, the first memory 23 . Second memory 24. A set of gates 35 and 36, minute delay sections 41 and 42, a flip-flop 49, and a driver 15 are provided, respectively.

The respective outputs of the minute delay sections 43 and 44 are supplied to comparators 51 and 52 as operation commands, so-called strobes, and only when this is given, a comparison result is output.

Others are in a high output impedance state.

The output pin of the logic circuit under test 14 is supplied to the inverting input side of a comparator 51 and the non-inverting input side of a comparator 52. Comparator 5
The logic level @ HII basic value v is on the non-inverting input side of 1.
oH is at the logic level 1L'' on the inverting input side of the comparator 52.
A reference value voL is given for each.

Third. The fourth memories 25 and 26 store timing information for determining the output logic level of the logic circuit under test 14.

When determining whether the expected value is a high level @H, "1" and delay information are stored in the third memory 25, and when determining whether the expected value is a low level "L", "1" is stored in each corresponding address of the fourth memory 26. is memorized. (=Although not shown, the set of third memory 25, fourth memory 26, gate 37, 38, minute delay unit 43, 44, comparator 51, 52 is connected to other output pins of the logic circuit under test 14. It is also provided for.

Next, the operation will be explained with reference to FIG. The base signal is the second
Figure AC: As shown, the period T is constant, and the count contents of the reference signal counting section 22 change as shown in Figure 2B-C.

If timing information "1" and delay information t11, t141t, and 6 are respectively stored at address 1.4.6 of the first memory 23, then when the count value of the reference signal counting section 22 becomes 132, as shown in FIG. As shown in C, the output of terminal 31 of the second memory becomes high level 11", and the output of terminal 4
tIf is read from 5 (21st gD). This terminal 3
The timing signal (base signal) that passes through the gate 35 at a high level of 1 is delayed by the delay information t11 in the minute delay section 41.

A delay timing signal indicating the second factor F (= is output).

Similarly, in the counting content 4.6, the delayed timing signal is the second factor F.
As shown in (= output.

The second memory 24 has the address 3 h 5 o n+ I +=timing j blue report “1” and delay information t231 t251 t2n+ as shown in the second factors F and G, respectively.
Assuming that 1 is stored respectively, the count contents 3 and 5
t231 and t2 respectively for the reference position at ゜0+1
The timing signal delayed by 5-12n-1-1 is the second
Factor F (as shown in Figure 2) (-obtained.

Since the flip-flop 49 is set by the timing signal of the second factor F and reset by the timing signal of the second factor F, the test signal shown in FIG. 2 is supplied from the driver 15 to the logic circuit under test 14.

On the other hand, it is assumed that timing information "1" and delay information t34 @ t37 are stored at address 4.7 of the third memory 25, respectively, as shown in FIGS. J and K in S52. Therefore, in the same way as described above, when the content of the C2 reference signal counting section 22 reaches 4.7 as shown in the second diagram, a strobe pulse delayed by t341'37 from the reference is generated, and this is input to the comparator 51. Ru. Comparator 5
1 is supplied with the output button shown in FIG. 2 M from the output bin of the logic circuit under test 14, the count content 4
When the strobe occurs, the output button is at a logic level.”
Since the level is higher than the reference value VOH of “H”, the comparator 51
However, when the strobe occurs at count content 7, the level of the output button is lower than the reference value VOR of the logic level ``H'', so failure information is output as shown in the second factor F. Ru.

? 54 memory 26. Gate 38. Although the minute delay section 44 and the comparator 52 will not be specifically explained with reference to the drawings, they generate a strobe at a desired time, and if the output slam is higher than the reference level voL at that time, defect information is output.

"952 Embodiment" FIG. 3 shows a second embodiment of the present invention, in which parts corresponding to those in FIG. 1 are given the same reference numerals. In this embodiment, the counting contents of the reference signal counting section 22 correspond to the first to fourth memories 23 to 23.
26 is not directly read. 1st to 4th memory 2
3 to 26, the count value and delay information of the reference signal counting section 22 which is to output the timing signal are stored as timing information in order at each address position. For example, in order to output the delay timing signal shown in the second factor F (2) from the information stored in the first memory 23, 1 and tl are input to address 1 of the first memory 23.
1, 4 and t14 are stored at address 2, and 6 and t16 are stored at address 3. These timing information 1.4.
6 is read out to the terminal 31, and the delay clear f4i'z l'+
411+s is read out from terminal 45 (-).

Each timing information of the terminals 31 to 34 of the first to fourth memories 23 to 26 is compared with the count value of the reference signal counting unit 22 by the coincidence detection units 61 to 64, and when the two match, the respective timing information is gated as a gate control signal. 35 to 38, respectively. The first to fourth memories 23 to 26 (2 pairs of address counters 65 to 68 are respectively provided, and the address counters 65 to 68 are initially set to the initial value 1, and the address counters 65 to 68 The first count value is
- the fourth memories 23-26 are each addressed; When each of the match detection units 61 to 64 detects a match, each of the corresponding address counters 65 to 68 becomes 1.
be advanced. Therefore, for example, in the first memory 23, since the terminal 31 (21) is output, the reference signal counter 22
When the count content of becomes 1, the gate 35 opens and a timing signal is output, and the content of the address counter 65 becomes 2, and address 2 is read out from the second memory, that is, 4 + 114 are input to terminals 31 and 45, respectively. is read out.

Because of this configuration, the first to fourth memories 23 to
26, each address will be effectively used. Other operations are the same as in the case of FIG.

"Effect of the invention" This invention is configured as described above.

For example, looking at the output data of the logic simulator shown in FIG. 12500f) and write the timing information and delay information to the second memory 24 so that the delayed timing signal can be obtained from the minute delay section 41. Therefore, there is no need to create data separately for test patterns that do not include time information and timing that does not include pattern tri, and
Creating data for the fourth memories 23-26 is extremely easy. Moreover, in the past, testing was performed with limited timing resolution and test pattern combinations, making it impossible to match logic simulator output data and test patterns accurately.Test patterns were created by grouping them to some extent, but this made the work much easier. It was difficult and it was not possible to perform accurate tests, but with this invention, it is possible to accurately match the timing signals of the logic simulator output data, and the more accurate tests can be performed.

In addition, in the past, the logic level of the output button was first determined and then logically compared with the expected value, but in this invention, it is possible to simultaneously determine the logic level and detect whether or not it matches the expected value using a strobe pulse. , the logic comparison circuit can be omitted.

[Brief explanation of the drawing]

41 is a block diagram showing the first embodiment of the present invention, FIG. 2 is a time chart for explaining the operation of FIG. 1, FIG. 3 is a block diagram showing the second embodiment of the invention, and FIG. The figure is a block diagram showing a conventional logic circuit testing device.
FIG. 1 is a diagram showing an example of logic simulator output data. Patent applicant: Atopantest Co., Ltd. Agent: Takuo Kusano 4 Figure 75

Claims (1)

[Claims] (1) A reference signal generating section that generates a reference signal, a reference signal counting section that counts the reference signal, and timing information and delay information that should be generated in correspondence with the counting results of the reference signal counting section. a first, second, and third memory; and a first memory that reads delay information from the first memory and outputs a timing signal when the count value of the reference signal counting section becomes the timing information stored in the first memory. reading means; a first minute delay section that delays the timing signal according to the read delay information; and when the counted value of the reference signal counting section becomes the storage timing information of the second memory, a second reading means for reading delay information from the second memory and outputting a timing signal; and a second minute delay section for delaying the timing signal outputted by the second reading means in accordance with the delay information read from the second memory. and a flip-flop that is set and reset by the output of the first minute delay section and the output of the second minute delay section, respectively, and outputs the output as a test signal to the logic circuit under test, and a count value of the reference signal counting section. When it comes to the timing information stored in the third memory, a third reading means reads delay information from the third memory and outputs a timing signal;
A third minute delay section that delays according to the delay information read from the memory, and is operated by the output of the third minute delay section, and the output of the logic circuit under test is input, and it is set at a predetermined logic level. A logic circuit testing device comprising a comparator that determines whether or not there is an object.