JPS63143950U - - Google Patents
Info
- Publication number
- JPS63143950U JPS63143950U JP3531487U JP3531487U JPS63143950U JP S63143950 U JPS63143950 U JP S63143950U JP 3531487 U JP3531487 U JP 3531487U JP 3531487 U JP3531487 U JP 3531487U JP S63143950 U JPS63143950 U JP S63143950U
- Authority
- JP
- Japan
- Prior art keywords
- pulse signal
- timer circuit
- watchdog
- output
- detection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 230000004069 differentiation Effects 0.000 description 1
Landscapes
- Debugging And Monitoring (AREA)
Description
第１図はこの考案の一実施例の構成を示す回路
図、第２図は従来のウオツチドツグタイマ回路の
構成を示す回路図である。
３，４……シユミツトトリガ回路、Ｃ１，Ｃ３
……コンデンサ、Ｒ１，Ｒ２……抵抗、Ｄ３……
ダイオード（以上の構成要素はタイマ回路を構成
する）、１０……微分回路（変化検出回路）。
FIG. 1 is a circuit diagram showing the structure of an embodiment of this invention, and FIG. 2 is a circuit diagram showing the structure of a conventional watchdog timer circuit. 3, 4... Schmitt trigger circuit, C1, C3
... Capacitor, R1, R2 ... Resistor, D3 ...
diode (the above components constitute a timer circuit), 10... differentiation circuit (change detection circuit).
Claims (1)
るように構成されているコンピユータの暴走を前
記パルス信号に基づいて検知するウオツチドツク
タイマ回路において、前記パルス信号のレベルが
変化したか否かを検出し、変化検出時には検出パ
ルス信号を出力する変化検出回路と、前記検出パ
ルス信号が所定期間出力されなかつた場合に前記
コンピユータにリセツト信号を供給するタイマ回
路とを具備することを特徴とするウオツチドツク
タイマ回路。 In a watchdog timer circuit configured to output a pulse signal of a constant period during normal operation, the watchdog timer circuit detects runaway of a computer based on the pulse signal, and detects whether or not the level of the pulse signal has changed. A watchdog comprising: a change detection circuit that outputs a detection pulse signal when a change is detected; and a timer circuit that supplies a reset signal to the computer when the detection pulse signal is not output for a predetermined period. timer circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3531487U JPS63143950U (en) | 1987-03-11 | 1987-03-11 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3531487U JPS63143950U (en) | 1987-03-11 | 1987-03-11 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63143950U true JPS63143950U (en) | 1988-09-21 |
Family
ID=30844694
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3531487U Pending JPS63143950U (en) | 1987-03-11 | 1987-03-11 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63143950U (en) |
-
1987
- 1987-03-11 JP JP3531487U patent/JPS63143950U/ja active Pending
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