JPH0334143U - - Google Patents
Info
- Publication number
- JPH0334143U JPH0334143U JP9234689U JP9234689U JPH0334143U JP H0334143 U JPH0334143 U JP H0334143U JP 9234689 U JP9234689 U JP 9234689U JP 9234689 U JP9234689 U JP 9234689U JP H0334143 U JPH0334143 U JP H0334143U
- Authority
- JP
- Japan
- Prior art keywords
- reset
- output
- circuit
- capacitor
- microcomputer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 6
- 238000007599 discharging Methods 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Debugging And Monitoring (AREA)
Description
第1図は本考案のリセツト回路を示す回路図、
第2図は第1図の各部波形を示すタイミングチヤ
ートである。
2,6……抵抗、3……第1のコンデンサ、4
……リセツト制御回路、5……マイクロコンピユ
ータ、7……第2のコンデンサ、8,9……トラ
ンジスタ。
FIG. 1 is a circuit diagram showing the reset circuit of the present invention.
FIG. 2 is a timing chart showing waveforms of various parts of FIG. 1. 2, 6...Resistor, 3...First capacitor, 4
...Reset control circuit, 5...Microcomputer, 7...Second capacitor, 8, 9...Transistor.
Claims (1)
第1の積分回路と、 前記第1の積分回路の積分出力が第1のレベル
以上の時、リセツト解除信号を発生するリセツト
制御回路と、 前記リセツト解除信号によつてリセツト解除さ
れ、リセツト解除されて正常動作する時、一定周
期のパルス信号を出力するマイクロコンピユータ
と、 第2のコンデンサを含み、前記リセツト制御回
路の出力を積分する第2の積分回路と、 前記第2の積分回路の積分出力が第2のレベル
以上の時、前記第1のコンデンサに蓄えられた電
荷を放電する第1の放電回路と、 前記パルス信号が出力された時、前記第2のコ
ンデンサに蓄えられた電荷を放電する第2の放電
回路とを備え、 前記マイクロコンピユータから一定周期の前記
パルス信号が出力されなくなつた時、前記マイク
ロコンピユータから一定周期の前記パルス信号が
出力される迄、前記リセツト制御回路の出力によ
つて、前記マイクロコンピユータを間欠的にリセ
ツトすることを特徴とするリセツト回路。[Claims for Utility Model Registration] A first integrating circuit that includes a first capacitor and integrates a power supply voltage, and generates a reset release signal when the integrated output of the first integrating circuit is equal to or higher than a first level. a microcomputer that is reset by the reset release signal and outputs a pulse signal of a constant period when the reset is released and operates normally; and a second capacitor, a second integrating circuit that integrates the output; a first discharging circuit that discharges the charge stored in the first capacitor when the integrated output of the second integrating circuit is equal to or higher than a second level; a second discharging circuit that discharges the charge stored in the second capacitor when the pulse signal is output, and when the pulse signal of a certain period is no longer output from the microcomputer, the microcomputer The reset circuit is characterized in that the microcomputer is intermittently reset by the output of the reset control circuit until the pulse signal of a constant period is output from the computer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9234689U JPH0334143U (en) | 1989-08-04 | 1989-08-04 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9234689U JPH0334143U (en) | 1989-08-04 | 1989-08-04 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0334143U true JPH0334143U (en) | 1991-04-03 |
Family
ID=31641783
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9234689U Pending JPH0334143U (en) | 1989-08-04 | 1989-08-04 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0334143U (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63103338A (en) * | 1986-10-21 | 1988-05-09 | Canon Inc | Display device |
-
1989
- 1989-08-04 JP JP9234689U patent/JPH0334143U/ja active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63103338A (en) * | 1986-10-21 | 1988-05-09 | Canon Inc | Display device |