JPS63142674A - Bipolar transistor - Google Patents

Abstract

PURPOSE:To improve the current capacity and the current-amplification factor of a transistor by a method wherein a cut-out part of an emitter surface electrode is formed on a part of the electrode and the distribution of a potential at each point in an emitter region is made uniform. CONSTITUTION:A post-stage emitter electrode 7 has a protruding region 71 where an emitter outside-connecting part 13 is mounted at the outside of a part surrounded by emitter finger-shaped parts 41-48. Cut-out parts 72, 73 are formed toward the central part from the neighborhood of the part where the protruding region 71 lies at right angles to emitter finger-shaped parts 41, 45. An electric current flowing into an emitter surface electrode near the cut-out parts flows along the cut-out parts. Accordingly, the distance of a current path of an electric current i flowing through the finger-shaped parts 45, 41 is made longer by the length, and the wiring resistance becomes big. Because the distance of the current path near the emitter outside- connecting part 13 can be made long, the wiring resistance can be made uniform as a whole; the distribution of a potential at each part at a post-stage emitter 4 can be made uniform; the non-uniform operation of a transistor can be limited. Accordingly, it is possible to limit the non-uniform operation of the transistor and to improve the current capacity and the current-amplification factor of the transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bipolar transistor, and more particularly, to a bipolar transistor having an emitter external connection portion formed on an emitter surface electrode for electrical connection with the outside.

[Conventional technology]

FIG. 10 shows a Darlington-connected bipolar transistor (hereinafter referred to as "DTr") as a conventional bipolar transistor. FIG. 4(a) is a top view thereof, and FIG. Φ) is a sectional view taken along the line CC in FIG. 4(a). In the figure, 10a is an N-type low resistance collector layer;
0a! is an N-type high-resistance collector layer laminated on the low-resistance collector layer 1loal;
0a and the high-resistance collector layer 10a constitute a semiconductor substrate that becomes the collector regions of the front and rear stages. 1a
2a is the base region of the front-stage transistor made of a P-type diffusion layer formed in the high-resistance collector layer 10a2 (hereinafter referred to as the "front-stage base"), and 2a is the N-type scattering layer formed in the front-stage base la. 3a is the base region (hereinafter referred to as "later base J") of the latter transistor made of a P-type diffusion layer formed in the high-resistance collector J'W10a2.
4a is the N formed in the subsequent base 3a.
The emitter region of the latter stage transistor is made of ゛-type scattering layer (
(hereinafter referred to as a "second-stage emitter"), and has a plurality of finger-shaped portions 41a to 50a in order to increase its peripheral length and improve characteristics such as current capacity and current amplification factor. 5a is a surface electrode of the front stage base 1a (hereinafter referred to as "front stage base electrode"), and 6a is a surface electrode of the front stage emitter 2a and the rear stage base 3a, electrically connecting the two. 7a is a surface electrode of the latter emitter (hereinafter referred to as "later emitter electrode"), 8a is an oxide film formed on the main surface of the semiconductor substrate to protect the PN junction, and 9a is a surface protection film.

11a is a collector electrode, 12a is a base external connection part formed at the center on the surface electrode 5a, 13a is an emitter external connection part formed at the center on the rear emitter electrode 7a, and 14a is formed on the collector electrode 11a. This is the collector external connection part.

Next, the operation of this DTr will be explained. Front stage base electrode 5
When the front stage transistor is operated by applying a positive bias to a and causing a base current to flow from the front stage base 1a to the front stage emitter 2a, the base current is amplified by the current amplification factor of the front stage transistor. The current flows from the low resistance collector layer 10al to the high resistance collector layer 1.
0a2 and flows to the previous stage emitter 2a. Since the former emitter 2a and the latter base 3a are electrically connected by the surface electrode 6a, the collector current flows from the latter base 3a to the latter emitter 4a, operating the latter transistor, and increasing the current amplification factor of the latter transistor. A collector current having a magnitude that is amplified by the current flows from the low resistance collector layer 10a1 to the high resistance collector layer 10a2 to the subsequent emitter 4a. In this way, when the base current of the transistor is passed, a large output current can be obtained.

[Problem that the invention seeks to solve]

However, according to the conventional DTr described above, when a large current flows through the rear emitter 4a, the rear emitter electrode 7
The resistance component of a cannot be ignored, and the potential of the rear emitter 4a increases due to the potential drop caused by the resistance component, and the bias voltage between the rear base 3a and the rear emitter 4a becomes smaller as the distance from the emitter external connection portion 13a increases. Also, in FIG. 10(a), for example, if we pay attention to the part surrounded by the dotted line, in this part, the current i4□i+147m flows from the finger-like parts 42a and 47a, and the current flows from the emitter external connection part 13a from these finger-like parts. A current i4 flows from the finger-shaped portions 41a and 46a that are separated from each other.

i46. There is a mixture of these currents, and some of these currents pass through the same path. For that purpose, the finger-like parts 4Ia, 46
At a, the current i4 from there.

In addition to the potential drop of 146%, the potential drop of the current i4□m+j4'7a is added, so that the potential of the rear emitter 4a further increases, and the bias voltage becomes smaller. Therefore, since the operation of the transistor is suppressed in a portion away from the emitter external connection portion 13a, the transistor operation is biased toward the vicinity of the emitter external connection portion 13a. Here, if the transistor operation is uneven, the current capacity and current amplification factor (hy
This is a problem as it reduces E).

The above is a description of a Darlington-connected bipolar transistor, but the same applies to a single bipolar transistor, and although the extent is different compared to a DTr, it is still a problem that the transistor operation is biased near the emitter external connection part. In particular, when these devices are used for high power applications, consideration must be given to bias in transistor operation.

The present invention has been made in view of the above points, and improves the current capacity and current amplification factor of the transistor by reducing bias in transistor operation near the external connection part of the emitter even when a large current flows. The purpose is to provide a bipolar transistor with a structure that allows measurement of

[Means for solving problems]

In order to achieve the above object, the bipolar transistor of the present invention includes a semiconductor substrate of a first conductivity type that is electrically connected to a collector electrode and serves as a collector region, and a bipolar transistor that is formed on the main surface side of the semiconductor substrate and that is electrically connected to a collector electrode and serves as a collector region. a base region of a second conductivity type electrically connected to a base surface electrode on a surface; an emitter region of a first conductivity type formed in the base region and electrically connected to an emitter surface electrode on the main surface; In a bipolar transistor formed on a surface electrode and provided with an emitter external connection portion for making an electrical connection with the outside, the emitter surface electrode is formed by forming a cutout portion of the electrode in a part thereof. , the potential distribution at each point of the emitter region is made uniform.

〔Example〕

Hereinafter, the present invention will be explained using embodiments shown in the drawings. FIG. 1 shows a first embodiment of the present invention, in which the present invention is applied to a DTr. The figure (a) is a top view, the figure (b)
) is a sectional view taken along the line A--A in FIG. First, let's focus on 10. has an N-type impurity concentration of lXl0” atoms/cf
The above is an N type low resistance collector layer, and 10□ has an N type impurity concentration of about 1×101" atoms/CTl1,
This is an N-type high-resistance collector layer laminated on the low-resistance collector N10°, and the low-resistance collector layer 101 and the high-resistance collector layer 10□ constitute a semiconductor substrate that becomes the front-stage and rear-stage collector regions. 1 is a high resistance collector layer 10□
2 is a front-stage emitter formed in the front-stage base 1, 3 is a rear-stage base formed in the high-resistance collector layer 10□, and 4 is a front-stage base formed in the rear-stage base 3. This is the second-stage emitter. The P-type impurity concentration of the front base 1 and the rear base 3 is 1×10′6~
The ON-type impurity concentration of the front emitter 2 and the rear emitter 4 may be about 1X10'' atoms/afl.

Next, the layout will be mainly explained with reference to FIGS. The aforementioned front stage base 1 and rear stage base 37 are electrically connected through a connection path 15, and the resistance layer R is inserted through this connection path 15. Note that a resistor R2 is inserted in parallel between the rear-stage emitter 4 and the rear-stage base 3. The rear emitter 4 has an emitter finger portion 41 whose planar shape is finger-like.
．． 42', 43, 44, and emitter finger portions 45, 46, 47, 48 which are parallel to these and face in opposite directions, and in the center of both, there is a portion 31 of the rear stage base 3.
appears on the surface, and the portion 31 is directly electrically connected to the subsequent emitter electrode 7. Note that the interval between adjacent emitter finger portions is approximately 120 μm. Further, protrusions 49 □ extend from the emitter fingers 41 , 45 in a direction perpendicular to the longitudinal direction of the emitter fingers so that a portion thereof is electrically connected to an emitter external connection portion 13 to be described later.
49□ is formed. Note that the above-mentioned portion 31 is a protrusion 49I.

It appears on the surface up to an angle of 49° and reaches the emitter external connection portion 13. Further, the protruding portion 49. .

49□ is formed in order to insert a resistor in the rear stage base 3 directly below this, and does not necessarily have to be connected to the emitter external connection portion 13, and may be placed in the vicinity thereof. Note that this protrusion 49. ．． No substantial transistor operation is performed in the 49□ portion.

A rear emitter electrode 7 electrically connected to the rear emitter 4 and formed on the main surface of the semiconductor substrate is connected to the emitter finger portion 4 .
1 to 48, the emitter finger portions 41 to 48 are arranged inside the emitter finger portions 41 to 48, and are also formed in their central portions, and extend from the central portions in a direction perpendicular to the longitudinal direction of the emitter finger portions 41 to 48. It has a protruding region 71 on which the emitter external connection portion 13 is mounted outside the portion surrounded by the emitter fingers 41 to 48 . Then, a cutout portion 72.7 having a width of about 30 μm is formed from the vicinity of the portion orthogonal to the protrusion region 71 and the emitter finger portion 41.45 toward the center portion.
3 (that is, the portion where the latter emitter electrode 7 is not formed) is formed. Note that the notch in the present invention is a part where a groove penetrating the semiconductor substrate or an insulating film (oxide film) on the substrate is formed by cutting out a part of the emitter surface electrode. Current flowing in the nearby emitter surface electrode flows along (or around) this notch. Moreover, this notch part is the emitter finger-like part 4.
Unlike the indented part formed between 1 and 48, a base finger-like electrode portion, which will be described later, is not formed thereon. and,
This notch formation process involves, for example, forming an oxide film on the semiconductor substrate at the desired position where the notch is to be formed and at the position where the PN junction formed by diffusion exists, and then covering the upper part of the oxide film and the entire semiconductor substrate. It is formed by forming a conductive component such as An that will become the emitter surface electrode, and then etching away the emitter surface electrode in a desired region including the top of the oxide film. The emitter external connection part 13 consists of a metallization layer,
It is formed in the protruding region 71, and electrical connection with the outside is made at this portion.

Next, in the front-stage transistor, the front-stage emitter 2 also has a plurality of finger-like parts, and the end thereof is connected to the connection path 15.
It extends to The surface electrode (previous base electrode) 5 of the pre-stage heath 1 has a finger-like electrode portion so as to fit into the indentation formed by the finger-like portion of the pre-stage emitter 2, and
A corner portion on the semiconductor substrate has a large area portion 51 in which the base external connection portion 12 is mounted. Surface electrodes 6 are formed in predetermined areas on the surfaces of the front emitter 2 and the rear base 3 to electrically connect them.

To explain the arrangement of the surface electrode 6 in detail, the front emitter 2
The base finger electrode portions 61 to 6 are disposed inside the rear base 3 portion, and the base finger electrode portions 61 to 6 are arranged inside the rear base 3 portion so as to enter the indentation formed between the emitter finger portions 41 to 48 of the rear emitter 4.
6 is formed, and base finger-like electrode portions 63 and 6
6 and the emitter fingers 41 .
45, base finger-shaped electrode portions 68, 69 are formed which are arranged on the emitter external connection portion 13 side. Here, the base finger-like electrode portion 69 has its tip 69 . is formed apart from the protrusion 49□.

A collector electrode 11 is formed on the other main surface of the semiconductor substrate, electrically connected to a low resistance collector N10, and a collector external connection portion 14 is formed on the collector electrode 11. Note that since the collector electrode 11 is normally electrically connected directly by soldering or the like, there is no need to newly form this collector external connection portion 14. 8 is an oxide film formed on the main surface of the semiconductor substrate to protect the PN junction; 9
is a surface protective film.

Therefore, in this embodiment, the operation is similar to that of the DTr shown in FIG. 10 described as the conventional technique, but in this case, the emitter external connection portion 13 is a portion surrounded by the rear-stage emitter 4 where heat easily accumulates. (Because it is placed on the protruding area 71 in a position that protrudes from that part, a large current flows to the rear emitter 4 and the collector area directly under the latter emitter 4 generates heat.) Even if this occurs, the shadow V can be reduced and thermal fatigue can be reduced.

However, this arrangement increases the difference in distance from the emitter external connection portion 13 to each point of the subsequent emitter 4. For example, since the finger-like portions 41, 42° 45.46 are closer than the finger-like portions 43, 44, 47.48, when the current flowing to the rear-stage emitter 4 becomes large, the rear-stage emitter electrode 7 It is conceivable that the transistor operation will be biased around this area due to the difference in wiring resistance, reducing the current capacity and current amplification factor. However, the present invention is extremely effective in such an arrangement, and According to the embodiment, notches 72 and 73 are formed in the rear-stage emitter electrode 7, so that, for example, the finger-like portions 45 and 41 can be cut out as shown in the partially enlarged view of FIG. 1(a) in FIG. Since the flowing current i bypasses each of the notches 72 and 73, the current path distance becomes correspondingly longer, and therefore, the wiring resistance increases accordingly. Therefore, the distance of the current path near the emitter external connection portion 13 can be increased, so for example, the distance between the emitter external connection portion 1
The current path distance from 3 to the finger-like portions 43, 44, 47° 48 and the distance from the finger-like portions 41, 42° 45,46 can be made approximately equal, and the wiring resistance is made uniform as a whole. , it is possible to equalize the potential distribution in each part of the rear-stage emitter 4, and to alleviate the bias in transistor operation.

The experimental results of the present inventors are shown in the graphs of FIGS. 3 and 4. First, in FIG. 3, the horizontal axis represents the distance from the emitter external connection portion 13 to each point of the subsequent emitter 4, and the vertical axis represents the emitter current i at each point, which is the total emitter current (2).

= 8A, the detected value when the collector-emitter voltage ' is 3. As you can see from the graph, the notch part 72.73
In the configuration without (white circle), emitter external connection part 1
The emitter current i, decreases as it moves away from 3, but by forming the notches 72 and 73 (hatched circles), the emitter current 10 is made uniform. Next, the graph in FIG. 4 represents the magnitude of the current amplification factor hFE with respect to the collector current IC when 5cm is applied between the collector base, and the solid line is the present invention, and the dotted line is the notch 72 This is a configuration without .73. As is clear from the graph, according to this example, the collector current ■. The larger the current amplification factor hFE is, the larger the current amplification factor hFE is compared to the case without the cutout portions 72 and 73, and it can be seen that by equalizing the wiring resistance, the bias in transistor operation is alleviated when the collector current IC is large.

Further, according to this embodiment, as shown in FIG. 2, the tip portion 69 of the base finger portion 69. is formed at a distance from the protrusion 49□, and a part of the current injected into the rear base 3 from the surface electrode 6 flows through the rear base 3 at a distance of 2.
The current flows through the emitter external connection portion 13 through the emitter external connection portion 13, but the amount becomes smaller as the distance l becomes longer. According to this embodiment, the amount of current is relatively small, and the emitter external connection portion 13, where the transistor operation tends to be biased, becomes smaller. Transistor operation near the portion 13 can be suppressed. Note that in this embodiment, the first
Since the base fingers 69 and 68 are arranged symmetrically in the figure, the tip of the base fingers 68 is formed into a protrusion 49. However, in order to further suppress the transistor operation in the vicinity of the emitter external connection portion 13, its tip and protrusion 49. In other words, the length of the base finger-like portion 68 in the longitudinal direction may be shortened.

Next, a second embodiment of the present invention is shown in FIG. Figure (a)
1 is a top view thereof, and FIG. 3(b) is a sectional view taken along the line DD in FIG. In the figure, the conventional DTr shown in FIG.
First, let us briefly explain the components that have the same functions as:
10dl is a low resistance collector layer, 10d2 is a high resistance collector layer, 1d is a pre-stage base, 2d is a pre-stage emitter, 3d
is a rear-stage base, 4d is a rear-stage emitter, 41d to 47d and 51d to 57d are emitter finger-shaped portions of the latter emitter 4d, 5d is a front-stage base electrode, and 6d is formed in a predetermined area on the surface of the front-stage emitter 2d and the rear-stage base 3d. 7d is a subsequent emitter current; 8d is an oxide film formed on the PN junction and on the semiconductor substrate where notches 71d to 76d to be described later are to be formed; 9d is a surface protective film; lid
is the collector electrode, 12d is the base external connection part, 13d
14d is an emitter external connection part, and 14d is a collector external connection part.

In this embodiment, the cutout portions 71d and 72d formed in the same manner as in the first embodiment are connected to the indented portions formed between the emitter finger portions 43d to 45d and 53d to 55d, and the emitter external connection portion 13d, respectively. The emitter fingers are formed with a predetermined interval therebetween, and the longitudinal direction thereof is perpendicular to the longitudinal direction of the emitter fingers. Furthermore, cutout portions 73d are formed from the distal ends of the indented portions at the base portions of the emitter finger portions 41d, 51d, 47d, and 57d toward the emitter external connection portion 13d.

74d, 75d, and 76d are formed.

Therefore, according to this embodiment, first, the notch portion 71d.

72d, for example, the current i4 flowing through the emitter fingers 44d, 54d bypasses the notches 71d, 72d as shown by the arrows in the figure.
The wiring resistance from the emitter finger portions 44d, 54d to the emitter external connection portion 13d increases, and the transistor operation in this vicinity is suppressed, so that the bias in transistor operation, which has been a problem in the prior art, can be alleviated.

Next, the effect of the notches 73d to 76d is shown in FIG.
) will be explained using FIG. 6, which is a partially enlarged view. Paying attention to the part surrounded by the dotted line in the figure, first, the notch 73d (
74d), the potential is determined by the wiring resistance of the subsequent emitter electrode 7d and the current flowing there, so the sheet resistance of the subsequent emitter electrode 7d is R.
If current i flows from point F and point G, the potential ■ from point E at point F is the potential ■ from point E at point G because the currents flowing from each point are mixed. is the potential ■, and the current 1
Since the value is the sum of the potential drop when 1 flows for a distance of 11, ......■ Therefore, the potential difference between points G and F is from the formulas ■ and ■, I! ,
1 Vc Vy= i 1 R> Q ”=・・・・・・
(1-α)W, and since this value cannot be set to O, a potential difference will always occur between point G and point F, and the transistor operation will always be biased toward point F.

When the notch 73d exists, the current path is restricted, and the potential VFI from point F to point E is only the potential drop due to the current 11 flowing from point F, and α W from point E to point G Therefore, the potential V G I of G
The potential difference between point and point F is given by formulas ■ and ■.
・■Here, in order to make the value of ■2 O, it is sufficient to satisfy 1. -12, so 0
The formula is: 2 A, ffi.

(1-α)W αW ■, and α=-, that is, the emitter fingers 42d and 43
In this case, the distance from the point P to the notch 73d is 3 for the distance W from the point P at the tip of the indented part between the point P and the center line S of the opposing emitter fingers. If the design is reduced to 1/2, the potential difference between point G and point F can be eliminated.
By doing so, the potential distribution of each part of the subsequent emitter 4d can be made uniform, and the bias in transistor operation can be alleviated. Furthermore, from formulas ■' and ■, if α is %, then point G and F
The potential difference between the points can be made smaller than in the case without the notch 73d, which is effective in alleviating bias in transistor operation.

Next, FIG. 7 shows a third embodiment of the present invention, in which the present invention is applied to a single bipolar transistor. Figure (a) is a top view, Figure (b) is Figure (a).
It is a sectional view taken along the line BB inside. This embodiment is formed in the same way as the transistor in the latter stage of the embodiment shown in FIG. 1, and the same effect can be expected; 10b is a low-resistance collector layer, 10b2 is a high-resistance collector layer, and llb is a high-resistance collector layer. Collector electrode, 14b is the collector external connection part, 3b and 4b are the rear base 3 and rear emitter 4 in FIG. 1, respectively.
The base region and emitter region correspond to the . Reference numeral 6b denotes a base electrode, one end of which is placed in a corner of the semiconductor substrate over a relatively large area, and a base external connection portion 1 is placed on top of the base electrode.
It has 2b. The base electrode 6b has a finger-like electrode part formed so as to enter into a recessed part formed by the finger-like part of the emitter region 4b, and the other end 6b has a recessed part closest to the emitter external connection part 13b. It is not formed at 6bz, but is formed up to this side.

The emitter region 4b has a plurality of emitter finger-shaped parts, the central part of which is not formed, and a protruding part is formed so that a part thereof is electrically connected to the emitter external connection part 13b. . The emitter electrode 7b is formed on the inside of the emitter finger-shaped portion and also on the center portion, and one end thereof is placed at a corner of the semiconductor substrate at a position protruding from the emitter region 4b, and an emitter electrode 7b is formed on the top of the emitter finger-shaped portion. It has a connecting portion 13b. Furthermore, the notch 72 in FIG.
．． Notches 72b and 73b are bent and formed for the same purpose as 73. In the figure, 8b is an oxide film, and 9b is a surface protection film.

Next, FIG. 8 shows a fourth embodiment of the present invention, in which the present invention is applied to a multi-emitter bipolar transistor. Figure (a) is a top view, Figure (b) is an enlarged view of section H in Figure (a), Figure (C) is a sectional view of the stairs taken along line I-1 in Figure (b). be. In the figure, 3c is a base region, 4C is an emitter region, 6C is a base electrode, and 7C is a base region.
is an emitter electrode, 8C is an oxide film, 9c is a surface protective film, 1
0C8 is a low resistance collector layer, 10C2 is a high resistance collector layer, llc is a collector electrode, 12c is a base external connection part, 13c is an emitter external connection part, and a large number of emitter regions 4C are formed in the base region 3c, Base region 3C1 in each emitter region 40 portion
High resistance collector N11 Cm, low resistance collector layer 10
c1 constitutes one transistor unit, and one transistor is constituted by electrically connecting these many transistor units with a base electrode 6C and an emitter electrode 7C.

Also in this embodiment, notches 71c and 72c are formed in the emitter electrode 7c, and as in the above embodiment, it is possible to suppress bias in transistor operation near the emitter external connection portion 13C.

Note that the present invention is not limited to the above two embodiments,
Various modifications can be made without departing from the spirit of the invention. For example, although the above embodiment uses an NPN type bipolar transistor, a PNP type may also be used, or a structure in which two or more bipolar type transistors are connected can also be adopted. be. Furthermore, as shown in the schematic top view of the fifth embodiment of the present invention in FIG. (, a notch 71e formed in the emitter electrode 7e,
72e may be formed by cutting out from the end of the emitter electrode 7e parallel to the side in the direction perpendicular to the longitudinal direction of the emitter finger-shaped portion of the emitter external connection portion 13e, and the cutout portions 73e and 74e The notch formed from the base of the emitter finger is formed with a predetermined length in parallel to the longitudinal direction of the emitter finger, and is bent from there to allow the emitter to be emitted.
7 may be formed to extend toward the external connection portion 13e. It goes without saying that the notch may have a shape that is bent multiple times or a curved shape.

(Effects of the Invention) As described above, according to the present invention, notches are formed in the emitter surface electrode and the potential distribution in each part of the emitter region is made uniform, so that bias in transistor operation can be alleviated.
It has the excellent effect of improving electrical characteristics such as current capacity and current amplification factor of the transistor.

[Brief explanation of the drawing]

FIG. 1(a) is a top view of the first embodiment of the present invention, FIG. 1(C) is a sectional view taken along line A-A in FIG. Figure 2 is a partially enlarged view of Figure 1 (a), Figure 3 is a graph showing the current distribution at each point of the emitter,
FIG. 4 is a graph showing the magnitude of current amplification factor with respect to collector current, FIG. 5(a) is a top view of the second embodiment of the present invention, and FIG. - D line sectional view, 6th
The figure is a partially enlarged view of Figure 5 (a), and Figure 7 (a).
is a top view of the third embodiment of the present invention, and FIG. 7(b) is a top view of the third embodiment of the present invention.
8(a) is a sectional view taken along line B-B in a), and FIG.
A top view of the embodiment, FIG. 8(b) is an enlarged view of part 11 in FIG. 8(a), and FIG. 9 is a schematic top view of the fifth embodiment of the present invention, FIG. 10(a) is a top view of a conventional DTr, and FIG.
b) is a sectional view taken along the line CC in FIG. ■...Front stage base, 2...Front stage emitter, 3...
Rear stage heath, 4... Rear stage emitter, 5... Front stage base electrode. 6...Surface snow removal, 7...Late stage emitter electrode, 10.
...Low resistance collector layer, 10□...High resistance collector layer. 11...Collector electrode, 12...Base external connection part. 13...Emitter external connection part, 14...Collector external connection part, 71...Protrusion part, 12.73...Notch part.

Claims (4)

[Claims] (1) A semiconductor substrate of a first conductivity type that is electrically connected to a collector electrode and serves as a collector region, and a second conductivity type that is formed on the main surface side of the semiconductor substrate and electrically connected to a base surface electrode on the main surface. a base region of the mold; an emitter region of a first conductivity type formed in the base region and electrically connected to the emitter surface electrode on the main surface; and an emitter region of a first conductivity type formed on the emitter surface electrode and electrically connected to the outside. In a bipolar transistor having an emitter external connection portion for
A bipolar transistor characterized in that the potential distribution at each point of the emitter region is made uniform by forming a notch in a part of the electrode. (2) The bipolar transistor according to claim 1, wherein the emitter region has an emitter finger-like portion whose planar shape is partially finger-like. (3) The bipolar transistor according to claim 2, wherein the notch portion is formed to extend from the root portion side of the emitter finger portion toward the emitter external connection portion side. (4) The emitter external connection part is arranged outside the part surrounded by the emitter region, and the cutout part is arranged from the emitter external connection part side to the center of the part surrounded by the emitter region. The bipolar transistor according to any one of claims 1 to 3, wherein the bipolar transistor is formed to extend toward the bottom side.