JP2020150250A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device capable of enlarging an SOA by raising a transition voltage.SOLUTION: A semiconductor device includes a collector layer, a base layer, and an emitter which are disposed on a substrate, an emitter mesa layer being disposed on a partial region of the emitter layer. In a plan view, a base electrode is disposed in a region which does not overlap the emitter mesa layer. The base electrode allows base current to flow to the base layer. In a plan view, a first edge forming part of edges of the emitter mesa layer extends in a first direction, and a second edge forming part of edges of the base electrode faces the first edge. A gap between the first edge and the second edge in a terminal portion located on one end portion side of the emitter mesa layer in the first direction is wider than a gap in an intermediate portion of the emitter mesa layer.SELECTED DRAWING: Figure 4

Description

The present invention relates to a semiconductor device.

A heterojunction bipolar transistor (HBT) is mainly used as an active element constituting a power amplifier module of a mobile terminal (Patent Document 1). Desirable characteristics required for this HBT include various items such as high efficiency, high gain, high output, and high withstand voltage. Envelope tracking systems, which have recently attracted attention, require HBTs that operate at high collector voltages. In order to realize the high voltage operation of the HBT, it is necessary to expand the safe operation area (SOA: Safety Operating Area).

Japanese Unexamined Patent Publication No. 2005-101402

When the collector voltage of the HBT is increased in the graph showing the collector current-collector voltage characteristic (Ic-Vce characteristic), the boundary line (SOA line) between the range and the outside of the SOA gradually decreases. According to the evaluation experiments of the inventors of the present application, it has been found that a phenomenon in which the SOA line drops discontinuously appears at a certain collector voltage. In the present specification, the collector voltage when the SOA line drops discontinuously is referred to as a “transition voltage”. The characteristic that the SOA line decreases discontinuously will be described later with reference to FIG.

If the operating voltage is equal to or higher than the transition voltage, there is an increased risk that the actual operating range will deviate significantly from the SOA range if the load fluctuates during the operation of the HBT. If the operating range deviates significantly from the SOA range, the HBT may be damaged. Therefore, it is desired to increase the transition voltage and expand the SOA in order to operate at a high collector voltage without damaging the HBT even if the load fluctuation occurs.

An object of the present invention is to provide a semiconductor device capable of increasing the transition voltage and expanding the SOA.

According to one aspect of the invention
It comprises a collector layer, a base layer, an emitter layer arranged on a substrate, and an emitter mesa layer arranged on a part region of the emitter layer, and the collector layer, the base layer, and the emitter layer are the same. It is stacked in order and
further,
A region that does not overlap with the emitter mesa layer in a plan view, and has a base electrode for passing a base current through the base layer.
In plan view, the emitter layer has a first edge that is long in the first direction.
In plan view, the base electrode has a second edge that is long in the first direction.
The first edge of the base electrode faces the first edge of the emitter mesa layer and is located on one end side of the emitter mesa layer in the first direction. Provided is a semiconductor device in which the distance between the edge and the second edge is wider than the distance between the first edge and the second edge in the intermediate portion of the emitter mesa layer in the first direction.

Assuming that the distance between the first edge and the second edge at the end portion of the emitter mesa layer located on one end side in the first direction is wider than the distance at the middle portion of the emitter mesa layer, the unit at the end portion. The base access resistance per length is higher than the base access resistance per unit length in the middle part. As the base current increases, the voltage drop due to the base access resistor causes the net base-emitter voltage at the end to be lower than the net base-emitter voltage at the middle. As a result, during operation with a large current, the region where the emitter current mainly flows is generally limited to the intermediate portion of the emitter mesa layer, and the stability of the position of the region where the emitter current mainly flows is improved. This makes it difficult for the region in which the emitter current mainly flows to move in the emitter mesa layer. This makes it possible to increase the transition voltage and expand the SOA.

FIG. 1 is a plan view of the HBT according to a reference example that was the subject of the evaluation experiment. FIG. 2 is a graph showing the actual measurement results of the SOA line of the HBT. FIG. 3 is a graph showing the actual measurement results of the collector current-base voltage characteristic (Ic-Vb characteristic) and the base current-base voltage characteristic (Ib-Vb characteristic). FIG. 4 is a plan view of one of the plurality of unit transistors constituting the semiconductor device according to the first embodiment. FIG. 5 is a cross-sectional view taken along the alternate long and short dash line 5-5 of FIG. FIG. 6 is a cross-sectional view taken along the alternate long and short dash line 6-6 of FIG. FIG. 7 is a plan view of the semiconductor device according to the first embodiment. FIG. 8 is a diagram showing a planar positional relationship between the emitter mesa layer and the base electrode of the semiconductor device according to the first embodiment. 9A, 9B, and 9C are diagrams showing the shape and positional relationship of the emitter mesa layer and the base electrode of the semiconductor device according to the modified example of the first embodiment in a plan view. FIG. 10 is a cross-sectional view of a semiconductor device according to a modified example of the first embodiment. FIG. 11 is a plan view of one of the plurality of unit transistors constituting the semiconductor device according to the second embodiment. FIG. 12 is a graph showing the actual measurement results of the SOA line of the semiconductor device according to the second embodiment. FIG. 13 is a graph showing the relationship between the dimensions of the terminal portions at both ends of the emitter mesa layer in the first direction and the transition voltage. FIG. 14 is a plan view of the semiconductor device according to the modified example of the second embodiment. FIG. 15 is a plan view of one of the plurality of unit transistors constituting the semiconductor device according to the third embodiment. FIG. 16 is a plan view of a semiconductor device according to a modified example of the third embodiment. FIG. 17 is a plan view of the semiconductor device according to another modification of the third embodiment. FIG. 18 is a plan view of the semiconductor device according to still another modification of the third embodiment. FIG. 19 is a plan view of the semiconductor device according to still another modification. FIG. 20 is a plan view of one of the plurality of unit transistors constituting the semiconductor device according to the fourth embodiment. FIG. 21 is a plan view of one of the plurality of unit transistors constituting the semiconductor device according to the fifth embodiment. FIG. 22 is a cross-sectional view taken along the alternate long and short dash line 22-22 of FIG. FIG. 23 is a plan view of one of the plurality of unit transistors constituting the semiconductor device according to the sixth embodiment. FIG. 24 is a plan view of the semiconductor device according to the seventh embodiment.

Before explaining the examples, one factor hindering the expansion of SOA in a general HBT will be described with reference to the drawings of FIGS. 1 to 3 based on the evaluation experiment conducted by the inventors of the present application. To do.

FIG. 1 is a plan view of the HBT according to a reference example that was the subject of the evaluation experiment. A sub-collector layer 20 made of a conductive semiconductor is provided on the surface layer of the substrate. A collector layer 21, a base layer 22, and an emitter layer 23 are arranged on the sub-collector layer 20. The collector layer 21, the base layer 22, and the emitter layer 23 are substantially aligned in a plan view, and are arranged inside the sub collector layer 20 in a plan view. The emitter mesa layer 25 is arranged on a part of the region of the emitter layer 23. In a plan view, the emitter mesa layer 25 is arranged inside the emitter layer 23. The collector layer 21, the base layer 22, the emitter layer 23, and the emitter mesa layer 25 form a bipolar transistor, for example, an HBT.

The emitter mesa layer 25 has a long planar shape in one direction (horizontal direction in FIG. 1) in a plan view. For example, the planar shape of the emitter mesa layer 25 is rectangular. The emitter electrode 33 is arranged on the emitter mesa layer 25. In a plan view, the emitter electrode 33 is arranged inside the emitter mesa layer 25. The emitter electrode 33 is made of metal and makes ohmic contact with the emitter mesa layer 25.

In a plan view, the region of the emitter layer 23 that overlaps with the emitter mesa layer 25 operates as an HBT emitter. In the present specification, the portion of the emitter layer 23 that overlaps with the emitter mesa layer 25 is referred to as an intrinsic emitter layer 23A. In a plan view, the portion of the emitter layer 23 that does not overlap with the emitter mesa layer 25 is called the ledge layer 23B.

The base electrode 32 is arranged on the ledge layer 23B. The base electrode 32 passes through the ledge layer 23B and is connected to the base layer 22 by an alloying process, and a base current is passed through the base layer 22. In FIG. 1, the base electrode 32 is hatched. The base electrode 32 includes two base electrode main portions 32A and a base electrode pad portion 32B. The two base electrode main portions 32A are arranged on both sides of the emitter mesa layer 25 in the width direction in a plan view, and extend in the longitudinal direction of the emitter mesa layer 25. The base electrode pad portion 32B connects two base electrode main portions 32A to each other outside one end portion (left end in FIG. 1) in the longitudinal direction of the emitter mesa layer 25. The base electrode 32 including the base electrode main portion 32A and the base electrode pad portion 32B surrounds the emitter mesa layer 25 in a U shape.

Collector electrodes 31 are arranged on both sides of the collector layer 21 inside the sub-collector layer 20. Each of the collector electrodes 31 has a long planar shape in a direction parallel to the longitudinal direction of the emitter mesa layer 25. The collector electrode 31 is connected to the collector layer 21 via the sub collector layer 20.

An insulating film is arranged on the collector electrode 31, the base electrode 32, and the emitter electrode 33. The collector wiring C1, the base wiring B1, and the emitter wiring E1 are arranged on the insulating film so as to overlap the collector electrode 31, the base electrode pad portion 32B, and the emitter electrode 33 in a plan view, respectively. The collector wiring C1 is connected to the collector electrode 31 through a collector opening 35 provided in the insulating film below the collector wiring C1. The base wiring B1 is connected to the base electrode 32 through a base opening 36 provided in the insulating film below the base wiring B1. The emitter wiring E1 is connected to the emitter electrode 33 through the emitter opening 37 provided in the insulating film below the emitter wiring E1.

The emitter opening 37 is arranged inside the emitter electrode 33 in a plan view, and has a planar shape long in the longitudinal direction of the emitter mesa layer 25. The collector opening 35 is arranged inside the collector electrode 31 in a plan view, and has a planar shape long in the longitudinal direction of the collector electrode 31. The base opening 36 is arranged inside the base electrode pad portion 32B in a plan view.

The emitter wiring E1 is pulled out in a direction away from the base electrode pad portion 32B. The base wiring B1 is pulled out in a direction away from the emitter mesa layer 25. A second layer of wiring may be further arranged on the emitter wiring E1, the collector wiring C1, and the base wiring B1.

In a plan view, the emitter mesa layer 25, the emitter electrode 33, and the emitter opening 37 have symmetry in both the longitudinal direction and the width direction. Further, the distance between the edge of the emitter mesa layer 25 and the edge of the base electrode main portion 32A is substantially constant.

Usually, the area of the emitter electrode 33 is designed to be as large as possible in order to secure a wide region in which the current flows in the emitter mesa layer 25 and the intrinsic emitter layer 23A. For example, the distance between the outer peripheral line of the emitter mesa layer 25 and the outer peripheral line of the emitter electrode 33 is designed to be 1 μm or less. In FIG. 1, an example of the distribution of the emitter current contour line 38 is conceptually shown by a thin solid line. As described above, in the plan view, the magnitude of the emitter current is not uniform and has a certain distribution. The distribution of the contour line 38 will be described in detail later.

When a monolithic microwave integrated circuit element (MMIC) incorporating a power amplifier is configured, a plurality of HBTs shown in FIG. 1 are arranged per MMIC formed on one semiconductor substrate. The plurality of HBTs are electrically connected to each other directly or indirectly via an element such as a resistor via the emitter wiring E1, the collector wiring C1, the base wiring B1, and the wiring of the second layer above the base wiring B1. Be connected. As a result, a power amplifier in the power stage and the driver stage is configured.

FIG. 2 is a graph showing the actual measurement results of the SOA line of the HBT. The horizontal axis represents the collector voltage Vce in the unit "V", and the vertical axis represents the collector current density Jc in the unit "kA / cm ² ". Circles and triangles in the graph indicate SOA lines based on actual measurements of samples with different emitter dimensions. The circle symbol and the solid line in the graph of FIG. 2 show the actual measurement results of the sample having the width of the emitter electrode 33 of 3 μm and the length of 40 μm, and the triangle symbol and the broken line indicate the width of the emitter electrode 33 of 3 μm and the length of 20 μm. The actual measurement result of the sample of is shown. The region on the low voltage side of the SOA line corresponds to SOA.

It can be seen that when the collector voltage Vce increases from 6V to 6.5V, the SOA line drops discontinuously and sharply. The collector voltage Vce when the SOA line drops discontinuously corresponds to the transition voltage Vt.

In the reference examples shown in FIGS. 1 and 2, the number of emitter electrodes 33 is one and the number of base electrode main portions 32A is two, but the number of emitter electrodes 33 and the number of base electrode main portions 32A are other combinations. A discontinuous decrease in the SOA line was also confirmed in the HBT. For example, an HBT having both an emitter electrode 33 and a base electrode main portion 32A, an HBT having two emitter electrodes 33 and one base electrode main portion 32A, and a base electrode main portion 32A having two emitter electrodes 33. In the HBT having three electrodes and the HBT having three emitter electrodes 33 and four base electrode main portions 32A, a discontinuous decrease in the SOA line has been confirmed.

FIG. 3 is a graph showing the actual measurement results of the collector current-base voltage characteristic (Ic-Vb characteristic) and the base current-base voltage characteristic (Ib-Vb characteristic). The horizontal axis represents the base voltage Vb in arbitrary units, and the vertical axis represents the collector current Ic and the base current Ib in arbitrary units. In FIG. 3, the solid line represents the Ic-Vb characteristic, and the broken line represents the Ib-Vb characteristic. The scale of the vertical axis representing the collector current Ic and the scale of the vertical axis representing the base current Ib are different. In the measurement, the base voltage Vb and the collector current Ic were measured while sweeping the magnitude of the base current Ib with a current source. The measurement was performed at a plurality of voltages of collector voltage Vce = V1, V2, V3, V4 and V5. Here, the magnitude relationship between the voltages V1 to V5 is V1 <V2 <V3 <V4 <V5.

As shown by the solid line in FIG. 3, in the range where the collector current Ic is small, the collector current Ic increases monotonically as the base voltage Vb increases, and the slope of the collector current Ic with respect to the base voltage Vb gradually increases. Similarly, as shown by the broken line in FIG. 3, the slope of the base current Ib also gradually increases. When the collector current Ic becomes larger, the snapback point SB where the slope of the collector current Ic with respect to the base voltage Vb becomes infinite is reached. At this time, the slope of the broken line base current Ib also becomes infinite. When the collector current Ic is increased beyond the snapback point SB, the slopes of the solid collector current Ic and the dashed base current Ib with respect to the base voltage Vb change to negative, and the solid collector current Ic and the dashed base current Ib increase. At the same time, the base voltage Vb drops.

As shown by the solid line in FIG. 3, when the collector voltages Vce are V4 and V5, a kink K in which the collector current Ic drops discontinuously appears after the collector current Ic passes through the snapback point SB. When the collector voltage Vce is V1, V2, V3 lower than V4, V5, the kink K does not appear. The minimum collector voltage Vce at which the kink K appears corresponds to the transition voltage Vt (FIG. 2). Here, the kink K is a region in which the base voltage Vb tends to decrease and the collector current Ic tends to increase in the Ic-Vb characteristic, and the base voltage Vb temporarily increases or the collector current Ic temporarily decreases. Refers to the characteristic area that appears (see FIG. 3).

Next, the reason why the kink K appears in the region beyond the snapback point SB of the collector current-base voltage characteristic will be described.

The appearance of Kink K is presumed to be due to the thermal or electrical asymmetry of HBTs. Inside the emitter mesa layer 25 (FIG. 1), the arrangement of the emitter electrode 33 and the emitter opening 37 maintains symmetry. However, around the emitter mesa layer 25, base electrodes 32 and various wirings that are asymmetrically arranged with respect to the emitter mesa layer 25 are arranged. Further, a bird's-eye view of the arrangement of the plurality of HBTs constituting the power amplifiers of the power stage and the driver stage and the lead wiring, circuit elements, via holes, etc. around them shows that one emitter mesa layer 25 of interest is thermally and electrically. There is an asymmetric factor.

Until the collector current Ic reaches the snapback point SB, the current distribution in the region where the emitter current Ie mainly flows has a maximum value near the center of the emitter mesa layer 25 (FIG. 1) in the longitudinal direction and spreads to both sides in the longitudinal direction. .. When the collector current Ic increases beyond the snapback point SB, the current distribution in the region where the emitter current Ie mainly flows becomes longitudinal from the vicinity of the center of the emitter mesa layer 25 (FIG. 1) due to the asymmetric factor around the emitter mesa layer 25. It changes to have the maximum value at the displaced position. For example, the distribution of the emitter current contour lines 38 shown in FIG. 1 is biased from the vicinity of the center to the side where the base electrode pad portion 32B is located. As used herein, the term "asymmetry" means a factor having a maximum current value at a position where the region in which the emitter current Ie mainly flows is displaced in the longitudinal direction from the vicinity of the center of the emitter mesa layer 25 (FIG. 1). It is considered that the kink K (FIG. 3) appears due to the displacement of the position having the maximum current value in the region where the emitter current Ie mainly flows. In the embodiment described below, the position of the maximum current value in the region where the emitter current Ie mainly flows is not easily affected by the asymmetric factor around the emitter mesa layer 25.

[First Example]
Next, the semiconductor device according to the first embodiment will be described with reference to the drawings of FIGS. 4 to 8. Hereinafter, the description of the configuration common to the semiconductor device according to the reference example shown in FIG. 1 will be omitted.

FIG. 4 is a plan view of one of the plurality of unit transistors 70 constituting the semiconductor device according to the first embodiment. The emitter mesa layer 25 has a long shape in one direction in a plan view. The longitudinal direction of the emitter mesa layer 25 is referred to as the first direction. In a plan view, the first edges 41 on both sides of the emitter mesa layer 25 in the width direction extend in the first direction. Of the edges of the two base electrode main portions 32A of the base electrode 32, the second edge 42, which is a portion facing the first edge 41, extends in the first direction. When the first edge 41 and the second edge 42 face each other in a plan view, it means that the two edges are arranged so as to face each other. The state in which the two edges face each other includes not only a state in which the two edges are parallel to each other but also a state in which the two edges are in an oblique positional relationship.

The distance G1 between the first edge 41 and the second edge 42 at the end portion 44 of the emitter mesa layer 25 closer to the base electrode pad portion 32B is wider than the distance G0 between the two in the intermediate portion 45 of the emitter mesa layer 25. More specifically, the second edge 42 is a straight line parallel to the first direction, and the first edge 41 of the end portion 44 is a second edge 42 than the first edge 41 of the intermediate portion 45. It is arranged in a retracted position in a direction away from the first edge 41 and has a bent shape. Here, the "terminal portion" means a portion located at the end in the first direction, and the "intermediate portion" means a portion sandwiched between the end portions at both ends.

Even in the terminal portion 46 farther from the base electrode pad portion 32B, the shape and positional relationship between the first edge 41 and the second edge 42 are the same as the shape of both in the terminal portion 44 closer to the base electrode pad portion 32B. And the positional relationship is the same. Therefore, the emitter mesa layer 25 has a planar shape in which the end portions 44 and 46 at both ends are thinner than the intermediate portion 45.

The shortest distance from the edge of the base electrode pad portion 32B to the edge of the emitter wiring E1 is longer than the shortest distance from the base electrode pad portion 32B to the edge of the emitter mesa layer 25. In other words, the end of the emitter mesa layer 25 on the base electrode pad portion 32B side protrudes in the first direction from the end of the emitter wiring E1 on the base electrode pad portion 32B side toward the base electrode pad portion 32B. Therefore, there is a region not covered by the emitter wiring E1 at the end of the emitter mesa layer 25 closer to the base electrode pad portion 32B.

FIG. 5 is a cross-sectional view taken along the alternate long and short dash line 5-5 of FIG. An n-type GaAs layer is arranged on a substrate 60 made of semi-insulating GaAs, and a part of the n-type GaAs layer is insulated by ion implantation technology. The sub-collector layer 20 is formed by the non-insulated n-type GaAs layer. Of both sides of the substrate 60, the side on which the sub-collector layer 20 is formed is referred to as a "main surface". The collector layer 21, the base layer 22, and the emitter layer 23 are laminated in this order on a part of the region of the sub-collector layer 20. The emitter mesa layer 25 is arranged on a part of the region of the emitter layer 23. The emitter layer 23 is divided into an intrinsic emitter layer 23A directly below the emitter mesa layer 25 and a ledge layer 23B not covered by the emitter mesa layer 25. The intrinsic emitter layer 23A substantially coincides with the emitter mesa layer 25 in a plan view, and an operating current mainly flows through the intrinsic emitter layer 23A. In the present specification, "in plan view" and "in plan view" mean a state in which the main surface of the substrate 60 is viewed in a plan view from a direction orthogonal to the main surface of the substrate 60. The emitter mesa layer 25 includes a cap layer 25A on the emitter layer 23 side and a contact layer 25B arranged on the cap layer 25A.

The collector layer 21 is made of n-type GaAs, and the base layer 22 is made of p-type GaAs. The sheet resistance ρs of the base layer 22 is, for example, 130 Ω / □ or more and 400 Ω / □ or less. The emitter layer 23 is formed of, for example, an n-type InGaP having a Si doping concentration of 2 × 10 ¹⁷ cm ^-3 or more and 5 × 10 ¹⁷ cm ^-3 or less, and its thickness is 20 nm or more and 50 nm or less. The cap layer 25A is formed of, for example, an n-type GaAs having a Si doping concentration of 2 × 10 ¹⁸ cm ^-3 or more and 4 × 10 ¹⁸ cm ^-3 or less, and its thickness is 50 nm or more and 200 nm or less. The contact layer 25B is formed of, for example, an n-type InGaAs having a Si doping concentration of 1 × 10 ¹⁹ cm ^-3 or more and 3 × 10 ¹⁹ cm ^-3 or less, and its thickness is 100 nm or more and 200 nm or less. In addition, other compound semiconductors may be used for these semiconductor layers.

The collector electrode 31 is arranged on the sub-collector layer 20. The collector electrodes 31 are arranged on both sides of the collector layer 21 in the cross section shown in FIG. The base electrode 32 arranged on the ledge layer 23B is connected to the base layer 22 via an alloy layer 24 penetrating the ledge layer 23B. The alloy layer 24 is formed by diffusing the material of the base electrode 32 into the ledge layer 23B by a heat treatment process and alloying the alloy layer 24. Of the base electrodes 32, the base electrode main portion 32A (FIG. 4) appears in the cross section shown in FIG. 5, and the base electrode main portions 32A are arranged on both sides of the emitter mesa layer 25. The emitter electrode 33 is arranged on the emitter mesa layer 25.

The insulating film 61 is arranged so as to cover the collector electrode 31, the base electrode 32, and the emitter electrode 33. The emitter wiring E1 and the collector wiring C1 are arranged on the insulating film 61. The emitter wiring E1 is connected to the emitter electrode 33 through the emitter opening 37 provided in the insulating film 61. The collector wiring C1 is connected to the collector electrode 31 through the collector opening 35 provided in the insulating film 61. In this way, a layer containing conductor patterns such as the emitter wiring E1 and the collector wiring C1 is arranged on the collector electrode 31, the base electrode 32, and the emitter electrode 33 via the insulating film 61. As shown in FIG. 5, the emitter wiring E1 is arranged in a layer above the emitter electrode 33. Although not shown in the cross section shown in FIG. 5, the base wiring B1 (FIG. 4) is arranged in a layer above the base electrode 32. As described above, the "upper layer" is not defined by the height from the main surface of the substrate 60, but is a layer of a plurality of conductor patterns stacked in the thickness direction via an insulating film. It is defined by the hierarchical relationship.

FIG. 6 is a cross-sectional view taken along the alternate long and short dash line 6-6 of FIG. Hereinafter, description of the components appearing in the cross-sectional view shown in FIG. 5 will be omitted.

Of the base electrodes 32, the base electrode pad portion 32B appears in the cross section shown in FIG. The base wiring B1 and the emitter wiring E1 are arranged on the insulating film 61 that covers the base electrode 32 and the emitter electrode 33. The base wiring B1 is connected to the base electrode pad portion 32B through the base opening 36 provided in the insulating film 61. The base wiring B1 and the emitter wiring E1 are arranged in the same layer, and the distance between the two is designed to be, for example, the minimum distance of the design rule of the layer in which the base wiring B1 and the emitter wiring E1 are arranged. Will be done. The minimum interval of the design rule is set, for example, in the range of 1.5 μm or more and 3 μm or less.

The edge 26 located on the end side of the emitter wiring E1 closer to the base electrode pad portion 32B when viewed from the base electrode pad portion 32B is the end side of the emitter mesa layer 25 closer to the base electrode pad portion 32B. It is located farther than the edge 27 located at. With such an arrangement, the base collector junction area is minimized as much as possible under the condition that the area of the emitter mesa layer 25 is kept constant, and the performance of the transistor is improved.

FIG. 7 is a plan view of the semiconductor device according to the first embodiment. The semiconductor device according to the first embodiment includes a plurality of unit transistors 70 (FIG. 4). The plurality of unit transistors 70 are arranged side by side in a direction (longitudinal direction in FIG. 7) orthogonal to the longitudinal direction (first direction) of the emitter mesa layer 25.

From each of the unit transistors 70, the emitter wiring E1 is drawn out toward one side (right side in FIG. 7) in the first direction. The emitter wiring E1 drawn from each of the unit transistors 70 is continuous with the common emitter wiring (ground wiring) 71. In a plan view, a via hole 72 is provided inside the emitter common wiring 71. The via hole 72 penetrates the substrate 60 (FIGS. 5 and 6) and reaches the back surface of the substrate 60. The emitter common wiring 71 is connected to a ground electrode for external connection provided on the back surface of the substrate 60 via a metal member arranged in the via hole 72.

The base wiring B1 is drawn out from each of the unit transistors 70 in a direction opposite to the drawing direction of the emitter wiring E1 (on the left side in FIG. 7). Each of the base wirings B1 is widened and overlaps the high frequency input wiring 75. The overlapping portion of each of the base wiring B1 and the high frequency input wiring 75 functions as a capacitor 76 having a MIM structure. Further, each of the base wirings B1 is connected to the bias wiring 78 via the thin film resistor 77.

The collector wiring C1 of the first layer of each of the unit transistors 70 is connected to the collector common wiring (not shown) of the second layer arranged above the emitter common wiring 71. The common emitter wiring 71 and the common collector wiring may be independently connected to Cu pillar bumps, solder bumps, or the like.

Next, the excellent effect of the first embodiment will be described with reference to FIG.
FIG. 8 is a diagram showing a planar positional relationship between the emitter mesa layer 25 and the base electrode 32 of the semiconductor device according to the first embodiment. The first edge 41 of the emitter mesa layer 25 and the second edge 42 of the base electrode 32 face each other.

In the terminal portions 44 and 46 of the emitter mesa layer 25, the distance G1 between the first edge 41 and the second edge 42 is wider than the distance G0 in the intermediate portion 45. Therefore, the base access resistance increases at the terminal portions 44 and 46. That is, focusing on the base access resistance per unit length in the first direction, the base access resistance of the terminal portions 44 and 46 is larger than the base access resistance of the intermediate portion 45.

When the total base current Ib increases and the total emitter current Ie and the total collector current Ic come near the snapback point SB (FIG. 3), a voltage drop due to a relatively large base access resistor occurs at the terminal portions 44 and 46. , Greater than the voltage drop in the intermediate portion 45. Therefore, at the terminal portions 44 and 46, the net base potential excluding the influence of the parasitic resistance, that is, the base potential applied to the first edge 41 of the true emitter layer 23A (FIGS. 4, 5, 6) is intermediate. It is lower than the net base potential in portion 45. As a result, at the terminal portions 44 and 46, the net base-emitter voltage excluding the influence of the parasitic resistance is relatively lowered, and as a result, the emitter current Ie and the collector current Ic are relatively suppressed. Therefore, in the terminal portions 44 and 46, the density of the current flowing through the emitter-based junction surface is relatively reduced as compared with the intermediate portion 45. The relative decrease in current density results in a relative decrease in temperature.

The decrease in temperature further causes a relative decrease in current density. Due to this chain of positive feedback, in the large current range near the snapback point SB (FIG. 3), the current densities at the end portions 44, 46 are compared to the small current range away from the snapback point SB (FIG. 3). Begins to decrease rapidly. In the large current range beyond the snapback point SB, eventually no current will flow substantially. That is, the region where the total emitter current Ie mainly flows and the region where the temperature becomes high are generally limited to the intermediate portion 45 in the first direction. As a result, the operation of the HBT in the large current region is less susceptible to the thermal and electrical asymmetry near both ends of the emitter mesa layer 25. As a result, the generation of kink K (FIG. 3) is suppressed, and the transition voltage rises. As the transition voltage rises, the SOA is expanded and the HBT can operate at high voltage.

Next, preferable dimensions of each component of the semiconductor device according to the first embodiment will be described.
The preferred length of the emitter mesa layer 25 in the longitudinal direction (first direction) is 5 μm or more and 80 μm or less. The preferred width of the intermediate portion 45 of the emitter mesa layer 25 is 1 μm or more and 8 μm or less. The preferable difference between the interval G1 and the interval G0 is 0.3 μm or more and 1 μm or less. When these dimensions are set in the above range, the effect of expanding the SOA and maintaining the emitter current is enhanced. The dimensions of the terminal portions 44 and 46 in the first direction are preferably 0.5 μm or more, and more preferably 1 μm or more. Further, in consideration of the design margin, it is preferable that the dimensions of the terminal portions 44 and 46 in the first direction are 2 μm or more.

The current amplification factor β of the HBT is generally in the range of 50 or more and 200 or less. The sheet resistance ρs of the base layer 22 (FIGS. 5 and 6), the difference between the intervals G1 and G0, and the current amplification factor shall be set so as to satisfy ρs (G1-G0) / β ≧ 0.75Ω · μm. Is preferable. For example, when ρs = 200Ω / □ and β = 80, G1-G0 ≧ 0.3μm may be set.

Next, a modified example of the first embodiment will be described. In the first embodiment, the distance G1 between the first edge 41 and the second edge 42 at the end portions 44 and 46 at both ends of the emitter mesa layer 25 is made equal, and the distance between the two ends G0 at the intermediate portion 45 is made wider than There is. As a modification, the interval G1 at one end portion 44 and the interval G1 at the other end portion 46 may be different. In particular, at the terminal portion 44 closer to the base electrode pad portion 32B, the operation of the HBT is susceptible to thermal or electrical asymmetry. In order to reduce the influence of this asymmetry, in the end portion 44 closer to the base electrode pad portion 32B, the distance G1 between the first edge 41 and the second edge 42 is wider than the distance G1 in the end portion 46. It is preferable to do so.

Next, a plurality of other modifications of the first embodiment will be described with reference to FIGS. 9A, 9B, and 9C. 9A, 9B, and 9C are diagrams showing the shape and positional relationship of the emitter mesa layer 25 and the base electrode 32 of the semiconductor device according to these modifications in a plan view.

In the modified example shown in FIG. 9A, the shape of the emitter mesa layer 25 in a plan view is elliptical. The long axis of the ellipse is parallel to the longitudinal direction (first direction) of the base electrode main portion 32A. The two outer peripheral lines obtained by dividing the emitter mesa layer 25 into two along the long axis of the ellipse can be considered as the first edge 41 which is long in the first direction.

In this modification, the boundary line 47 between the terminal portions 44 and 46 and the intermediate portion 45 cannot be clearly defined based on the shape of the emitter mesa layer 25. No matter where the boundary line 47 between the end portions 44, 46 and the intermediate portion 45 is defined, the first edge 41 of the end portions 44, 46 is second than the first edge 41 of the intermediate portion 45. It is arranged at a position retracted in a direction away from the edge 42. In this respect, this modification is the same as that of the first embodiment. In this modification, the distance between the first edge 41 and the second edge 42 in the second direction is not constant, but when the distance is averaged in the first direction, it becomes the first edge 41 of the terminal portions 44 and 46. It can be said that the distance from the second edge 42 is wider than the distance between the first edge 41 and the second edge 42 of the intermediate portion 45.

In the modified example shown in FIG. 9B, the shape of the emitter mesa layer 25 in a plan view is a race track type. Specifically, it has a shape in which a semicircle is connected to each of the two short sides of a rectangle long in the first direction. In this case, the rectangular portion may be defined as the intermediate portion 45, and the semicircular portion may be defined as the terminal portions 44 and 46. The two outer peripheral lines obtained by dividing the race track shape into two by a straight line connecting the centers of the two semicircles can be considered as the first edge 41 which is long in the first direction.

Also in this modification, the first edge 41 of the end portion 44 is arranged at a position retracted from the first edge 41 of the intermediate portion 45 in a direction away from the second edge 42. This is the same as in the case of the first embodiment. Further, it can be said that the distance between the first edge 41 and the second edge 42 of the end portions 44 and 46 is wider than the distance between the first edge 41 and the second edge 42 of the intermediate portion 45.

In the modified example shown in FIG. 9C, the shape of the emitter mesa layer 25 in a plan view is hexagonal. More specifically, it has a shape in which the bases of an isosceles triangle are connected to two short sides of a rectangle long in the first direction. In this case, the rectangular portion may be defined as the intermediate portion 45, and the isosceles triangle portion may be defined as the terminal portions 44 and 46. The two outer peripheral lines obtained by dividing this hexagon into two at the apex angles of two isosceles triangles can be considered as the first edge 41, which is long in the first direction.

Also in this modification, the first edge 41 of the end portion 44 is arranged at a position retracted from the first edge 41 of the intermediate portion 45 in a direction away from the second edge 42. This is the same as in the case of the first embodiment. Further, it can be said that the distance between the first edge 41 and the second edge 42 of the end portions 44 and 46 is wider than the distance between the first edge 41 and the second edge 42 of the intermediate portion 45.

Therefore, in the modified examples of the first embodiment shown in FIGS. 9A, 9B, and 9C, the SOA is expanded and the high voltage operation of the HBT becomes possible as in the first embodiment. Is obtained.

Next, still another modification of the first embodiment will be described with reference to FIG.
FIG. 10 is a cross-sectional view of the semiconductor device according to this modification. The configuration on the substrate 60 side of the collector wiring C1 and the emitter wiring E1 is the same as the configuration of the semiconductor device (FIG. 5) according to the first embodiment.

In the first embodiment, the common emitter wiring 71 (FIG. 7) connecting the emitter electrodes 33 of the plurality of unit transistors 70 to each other is arranged on the same layer as the emitter wiring E1. Further, the emitter common wiring 71 is arranged at a position where it does not overlap with the unit transistor 70 in a plan view. On the other hand, in this modification, the emitter wiring E2 of the second layer is arranged instead of the emitter common wiring 71. The emitter wiring E2 is arranged on the insulating film 62 that covers the emitter wiring E1 and the collector wiring C1. The second-layer emitter wiring E2 is connected to the first-layer emitter wiring E1 through an emitter opening 63 provided in the insulating film 62. In a plan view, the second layer emitter wiring E2 overlaps with a plurality of unit transistors 70.

Cu pillar bumps, solder bumps, and the like for face-down mounting are arranged on the emitter wiring E2 of the second layer. In this modification, Cu pillar bumps, solder bumps, and the like can be arranged at positions close to the emitter mesa layer 25, which is a heat generating source. This structure contributes to the reduction of thermal resistance in the heat dissipation path. In this arrangement, the collector wiring is drawn from the collector electrode 31 (FIGS. 4 and 5) in FIG. 7 to the side opposite to the side from which the base wiring B1 is drawn (right side in FIG. 7), and the wiring of the first layer. It is connected to the collector common wiring formed by. Cu pillar bumps, solder bumps, etc. for the collector are arranged on the collector common wiring.

Next, another modification of the first embodiment will be described. In the first embodiment, the emitter electrode 33 is arranged inside the emitter mesa layer 25 in a plan view, but the emitter electrode 33 may protrude to the outside of the emitter mesa layer 25. This configuration can be formed using, for example, a self-alignment process in which the emitter electrode 33 is used as an etching mask to etch the semiconductor layer beneath it, leaving the emitter mesa layer 25.

[Second Example]
Next, the semiconductor device according to the second embodiment will be described with reference to FIGS. 11, 12, and 13. Hereinafter, the description of the configuration common to the semiconductor device (drawings of FIGS. 4 to 8) according to the first embodiment will be omitted.

FIG. 11 is a plan view of one of the plurality of unit transistors 70 constituting the semiconductor device according to the second embodiment. In the first embodiment, one emitter mesa layer 25 is surrounded by a base electrode 32 in a U shape. On the other hand, the unit transistor 70 of the semiconductor device according to the second embodiment has a double emitter structure in which the emitter mesa layer 25 is composed of two portions in a plan view. The two portions of the emitter mesa layer 25 each have a long planar shape in the first direction, and are arranged at intervals in the second direction orthogonal to the first direction.

The base electrode 32 is composed of one base electrode main portion 32A and a base electrode pad portion 32B continuous with the base electrode main portion 32A. The base electrode main portion 32A is arranged between the two portions of the emitter mesa layer 25. The first edge 41, which is a part of each edge of the two portions of the emitter mesa layer 25, faces the base electrode main portion 32A. The second edge 42, which is a part of the edge of the base electrode main portion 32A, faces the two portions of the emitter mesa layer, respectively. Of the edges of the base electrode main portion 32A, both edges in the width direction correspond to the second edge 42.

Also in the second embodiment, the distance between the first edge 41 and the second edge 42 shows the same change as the distance between the two according to the first embodiment in the first direction. That is, in the terminal portions 44 and 46 of the emitter mesa layer 25, the distance G1 between the first edge 41 and the second edge 42 is wider than the distance G0 in the intermediate portion 45.

Next, the excellent effect of the second embodiment will be described.
Also in the second embodiment, since the distance between the first edge 41 and the second edge 42 is changed as in the case of the first embodiment, the transition voltage is increased and the SOA is expanded. The effect is obtained. Further, in the second embodiment, the ratio of the area of the collector layer 21 to the area of the emitter mesa layer 25 is smaller than that in the first embodiment. As a result, an excellent effect of improving the high frequency characteristics (gain, efficiency, etc.) of the HBT can be obtained.

Next, an evaluation experiment conducted to confirm the excellent effect of the second example will be described.
In the evaluation experiment, the collector current-collector voltage characteristics of the semiconductor device according to the second embodiment and the semiconductor device according to the comparative example were measured, and the SOA line was obtained. The semiconductor device according to the comparative example has a configuration in which the interval G1 in the semiconductor device according to the second embodiment shown in FIG. 11 is equal to the interval G0. The length (dimension in the first direction) of the emitter mesa layer 25 was 40 μm, the width (dimension in the direction orthogonal to the first direction) was 3 μm, and the intervals G0 and G1 were both 1 μm.

In the semiconductor device according to the second embodiment, the interval G1 is set to 2 μm and the interval G0 is set to 1 μm. The length of the emitter mesa layer 25 was set to 40 μm, and the width of the emitter mesa layer 25 in the intermediate portion 45 was set to 3 μm. A plurality of samples in which the dimensions in the first direction of the end portions 44, 46 in which the distance between the first edge 41 and the second edge 42 are relatively wide are different in the range of 1.5 μm or more and 7.5 μm or less are different. Made.

FIG. 12 is a graph showing the actual measurement results of the SOA line of the semiconductor device according to the second embodiment. The horizontal axis represents the collector voltage Vce in the unit "V", and the vertical axis represents the collector current Ic in the unit "A". The solid line and the broken line in the graph of FIG. 12 indicate the SOA line of the semiconductor device according to the second embodiment and the comparative example, respectively. In the semiconductor device according to the second embodiment in which the characteristics shown in FIG. 12 were obtained, the first direction of the end portions 44, 46 in which the distance between the first edge 41 and the second edge 42 was relatively widened. The size of is 1.5 μm.

It was confirmed that by adopting the configuration of the semiconductor device according to the second embodiment, the transition voltage increased from Vt ₀ to Vt _{1 as} compared with the configuration of the comparative example, and as a result, the SOA expanded.

FIG. 13 is a graph showing the relationship between the dimensions of the terminal portions 44 and 46 at both ends of the emitter mesa layer 25 in the first direction and the transition voltage. The horizontal axis represents the dimension Lx of the terminal portions 44 and 46 in the first direction in the unit "μm", and the vertical axis represents the transition voltage in the unit "V". A sample having a dimension Lx of 0 in the first direction of the terminal portions 44 and 46 corresponds to a semiconductor device according to a comparative example.

It was confirmed that the effect of increasing the transition voltage was clearly obtained in the range where the dimension Lx of the terminal portions 44 and 46 in the first direction was at least 1.5 μm or more and 7.5 μm or less.

Next, preferable dimensions of the terminal portions 44 and 46 will be described.
From the actual measurement results shown in FIGS. 12 and 13, it was confirmed that when the dimensions (length) of the terminal portions 44 and 46 in the first direction are set to 1.5 μm or more, the effect of expanding the SOA can be obtained. Even if the lengths of the terminal portions 44 and 46 are less than 1.5 μm, some effect of expanding the SOA can be obtained. If the end portions 44 and 46 are made too short due to the limitation of microfabrication accuracy in the semiconductor process, the end portions 44 and 46 and the intermediate portion 45 cannot be distinguished. In order to make the terminal portions 44 and 46 distinguishable from the intermediate portion 45 and to obtain the effect of expanding the SOA, it is preferable that the length of the terminal portions 44 and 46 is 0.5 μm or more.

Further, if the terminal portions 44 and 46 are made too long, the effect of reducing the areas of the emitter mesa layer 25 and the intrinsic emitter layer 23A becomes large. Specifically, the current obtained at the same base voltage becomes small. Therefore, it is preferable that the lengths of the terminal portions 44 and 46 approach the lower limit of the range in which a sufficient effect of expanding the SOA can be obtained.

If the difference between the intervals G1 and G0 is too small, the difference between the base access resistance at the terminal portions 44 and 46 and the base access resistance at the intermediate portion 45 becomes small. As a result, the phenomenon that the current density of the current flowing through the intrinsic emitter layers 23A of the terminal portions 44 and 46 relatively decreases in the large current region is less likely to appear. In the large current region, it is preferable to make the interval G1 wider than the interval G0 by 0.3 μm or more in order to limit the region in which the emitter current mainly flows to the intermediate portion 45.

Next, a preferable relationship between the difference between the intervals G1 and G0 (G1-G0) and the length Lx of the terminal portions 44 and 46 will be described. The characteristics of the transistor are not easily affected by the asymmetry in the width direction (direction orthogonal to the first direction) around the emitter mesa layer 25, and are easily affected by the asymmetry in the longitudinal direction (first direction). This is because the dimension of the emitter mesa layer 25 in the width direction is smaller than the dimension of the emitter mesa layer 25 in the longitudinal direction, and the planar spread is small. In the longitudinal direction, which is a direction susceptible to asymmetry, it is preferable that the length Lx of the end portions 44, 46 is longer than G1-G0 in order to make it less susceptible to asymmetry.

Next, a semiconductor device according to a modified example of the second embodiment will be described with reference to FIG.
FIG. 14 is a plan view of the semiconductor device according to the modified example of the second embodiment. In the second embodiment, the edge of the emitter mesa layer 25 opposite to the first edge 41 is formed by a straight line from one end to the other in a plan view. Therefore, the width of the terminal portions 44 and 46 is narrower than the width of the intermediate portion 45. On the other hand, in this modification, the edge of the emitter mesa layer 25 opposite to the first edge 41 is also bent so that the widths of the terminal portions 44 and 46 and the width of the intermediate portion 45 are substantially equal to each other. ing.

In this way, the width of the emitter mesa layer 25 may be made substantially constant from one end to the other. Also in this case, the positional relationship between the second edge 42 of the base electrode main portion 32A and the first edge 41 of the emitter mesa layer 25 is the same as in the second embodiment. Therefore, as in the case of the second embodiment, the excellent effect of increasing the transition voltage and expanding the SOA can be obtained.

Next, another modification of the second embodiment will be described. In the second embodiment, the emitter electrode 33 is arranged inside the emitter mesa layer 25 in a plan view, but the emitter electrode 33 may protrude to the outside of the emitter mesa layer 25. This configuration can be formed using, for example, a self-alignment process in which the emitter electrode 33 is used as an etching mask to etch the semiconductor layer beneath it, leaving the emitter mesa layer 25.

[Third Example]
Next, the semiconductor device according to the third embodiment will be described with reference to FIG. Hereinafter, the description of the configuration common to the semiconductor device (drawings of FIGS. 4 to 7) according to the first embodiment will be omitted.

FIG. 15 is a plan view of one of the plurality of unit transistors 70 constituting the semiconductor device according to the third embodiment. In the first embodiment, the second edge 42 of the base electrode main portion 32A is formed of one straight line, and the first edge 41 of the emitter mesa layer 25 facing the second edge 42 is formed of a bent line. By making the first edge 41 a bent line, the spacing G1 at the terminal portions 44, 46 is made wider than the spacing G0 at the intermediate portion 45.

On the other hand, in the third embodiment, the first edge 41 of the emitter mesa layer 25 is composed of one straight line, and the second edge 42 of the base electrode main portion 32A is composed of a bent line. .. Specifically, the second edge 42 of the base electrode main portion 32A facing the terminal portions 44, 46 of the emitter mesa layer 25 is the first of the emitter mesa layer 25 rather than the second edge 42 facing the intermediate portion 45. It is arranged at a position retracted in a direction away from the edge 41 of the.

The edge of the base electrode main portion 32A opposite to the second edge 42 is also composed of a bent line reflecting the shape of the second edge 42, and the width of the base electrode main portion 32A is substantially constant. Has been made. The shape of the edge of the base electrode main portion 32A is also reflected in the shape of the edges of the collector layer 21, the base layer 22, and the emitter layer 23 including the base electrode 32 in the plan view. Specifically, the collector layer 21, the base layer 22, and the emitter layer 23 are composed of curved lines at the edges of the portions corresponding to the base electrode main portion 32A. With this configuration, the distance from the edges of the collector layer 21, the base layer 22, and the emitter layer 23 to the base electrode main portion 32A is made substantially constant. The shape of the edge of the collector electrode 31 facing the collector layer 21 is also a curved line reflecting the shape of the edge of the collector layer 21.

As an example, the dimension (length) of the emitter mesa layer 25 in the first direction is 5 μm or more and 80 μm or less, and the dimension (width) in the direction orthogonal to the first direction is 1 μm or more and 8 μm or less. As in the case of the first embodiment, the difference between the interval G1 and the interval G0 is preferably 0.3 μm or more and 1 μm or less. The preferred dimensions in the first direction of the end portion 44, which is a portion where the distance between the first edge 41 and the second edge 42 is widened, are the same as in the case of the first embodiment.

Next, the excellent effect of the third embodiment will be described. Also in the third embodiment, the base access resistance is relatively large at the terminal portions 44 and 46 of the emitter mesa layer 25. Therefore, as in the case of the first embodiment, the transition voltage can be increased and the SOA can be expanded. This enables high-voltage operation of HBTs.

Further, in the third embodiment, the terminal portions 44 and 46 of the emitter mesa layer 25 are not made thinner than the intermediate portion 45. That is, the region in which the emitter current and the collector current actually flow is wider than in the case of the first embodiment. As a result, the effect that the total collector current Ic can be kept large can be obtained.

Since the edges of the collector layer 21, the base layer 22, and the emitter layer 23 are bent according to the bending shape of the outer edge of the base electrode main portion 32A, the collector layer 21, the base, and the base are compared with the case of making a straight line. The area of the plane shape of the layer 22 and the emitter layer 23 becomes smaller. As a result, an increase in the junction capacitance between base collectors Cbc can be suppressed, and a decrease in high frequency characteristics can be suppressed.

Next, a semiconductor device according to a modified example of the third embodiment will be described with reference to FIG.
FIG. 16 is a plan view of the semiconductor device according to this modification. In the third embodiment (FIG. 15), the edge of the base electrode main portion 32A opposite to the second edge 42 is also composed of a bent line reflecting the shape of the second edge 42. The width of the base electrode main portion 32A is made substantially constant. On the other hand, in this modification, the width of the end portions at both ends of the base electrode main portion 32A is narrower than the width of the intermediate portion. The second edge 42 of the terminal portion of the base electrode main portion 32A is arranged at a position recessed from the second edge 42 of the intermediate portion in a direction away from the first edge 41 of the emitter mesa layer 25. Therefore, as in the case of the third embodiment, the interval G1 at the terminal portions 44 and 46 is wider than the interval G0 at the intermediate portion 45. Therefore, the transition voltage can be increased and the SOA can be expanded as in the case of the third embodiment.

Next, a semiconductor device according to another modification of the third embodiment will be described with reference to FIG.
FIG. 17 is a plan view of the semiconductor device according to this modification. In this modification, not only the second edge 42 of the base electrode main portion 32A but also the first edge 41 of the emitter mesa layer 25 is bent as in the first embodiment (FIG. 4). When this configuration is adopted, the bending amount of the first edge 41 and the second edge 42 at the end portions 44 and 46 becomes small under the condition that the difference between the interval G1 and the interval G0 is constant. On the contrary, when the bending amount of the first edge 41 and the second edge 42 at the terminal portions 44 and 46 is the same as in the cases of the first embodiment and the second embodiment, the difference between the interval G1 and the interval G0 Can be increased. Here, the "bending amount" means the amount of misalignment in the width direction between the edges of the terminal portions 44 and 46 and the edges of the intermediate portion 45.

Next, a semiconductor device according to still another modification of the third embodiment will be described with reference to FIG.

FIG. 18 is a plan view of the semiconductor device according to this modification. In the third embodiment (FIG. 15), the base electrode main portions 32A are arranged on both sides of one emitter mesa layer 25 in the width direction. In this modification, two emitter mesa layers 25 are further arranged, and a total of three emitter mesa layers 25 are arranged. The three emitter mesa layers 25 are arranged side by side in the width direction, and the base electrode main portion 32A is arranged between the two emitter mesa layers 25 adjacent to each other in the width direction.

The first edges 41 of the emitter mesa layer 25 are arranged on both sides of one base electrode main portion 32A in the width direction. In any of the first edges 41, the position where the first edge 41 of the end portion 44 recedes from the first edge 41 of the intermediate portion 45 in a direction away from the second edge 42 of the base electrode main portion 32A. It is located in. Therefore, in this modification as well, the transition voltage can be increased and the SOA can be expanded as in the case of the third embodiment. The number of emitter mesa layers 25 may be 4 or more. For example, when four emitter mesa layers 25 are arranged side by side in the width direction, a total of three base electrode main portions 32A may be arranged.

Next, a semiconductor device according to still another modification of the third embodiment will be described with reference to FIG.

FIG. 19 is a plan view of the semiconductor device according to this modification. The semiconductor device according to the modification shown in FIG. 19 has three emitter mesa layers 25 like the semiconductor device according to the modification shown in FIG. In the modified example shown in FIG. 18, the base electrode 32 has two base electrode main portions 32A, and the two base electrode main portions 32A are between two emitter mesa layers 25 adjacent to each other in the width direction. It is located in. On the other hand, in the modified example shown in FIG. 19, the base electrode main portion 32A is further arranged outside the two emitter mesa layers 25 located on the outermost side in the width direction, and the base electrodes 32 are totaled. It has four base electrode main portions 32A. The four base electrode main portions 32A are connected to one base electrode pad portion 32B.

In this modification, the base electrode main portions 32A are arranged on both sides in the width direction in each of the three emitter mesa layers 25. Therefore, the substantial base resistance can be reduced in the three emitter mesa layers 25.

Next, another modification of the third embodiment will be described. In the third embodiment, the emitter electrode 33 is arranged inside the emitter mesa layer 25 in a plan view, but the emitter electrode 33 may protrude to the outside of the emitter mesa layer 25. This configuration can be formed using, for example, a self-alignment process in which the emitter electrode 33 is used as an etching mask to etch the semiconductor layer beneath it, leaving the emitter mesa layer 25.

[Fourth Example]
Next, the semiconductor device according to the fourth embodiment will be described with reference to FIG. Hereinafter, the description of the configuration common to the semiconductor device (drawings from FIGS. 11 to 13) according to the second embodiment will be omitted.

FIG. 20 is a plan view of one of the plurality of unit transistors 70 constituting the semiconductor device according to the fourth embodiment. In the second embodiment, at the terminal portions 44 and 46 at both ends of the emitter mesa layer 25, the first edge 41 of the emitter mesa layer 25 is farther from the second edge 42 of the base electrode main portion 32A than the edge of the intermediate portion 45. It is placed in a position that is retracted in the direction. On the other hand, in the fourth embodiment, only at the end portion 44 closer to the base electrode pad portion 32B, the first edge 41 is oriented away from the second edge 42 than the first edge of the intermediate portion 45. It is arranged in a retracted position, and at the opposite end portion 46, the interval G1 and the interval G0 are equal.

Next, the excellent effect of the fourth embodiment will be described.
The presence of the base electrode pad portion 32B greatly disrupts the thermal and electrical symmetry with respect to the first direction when viewed from the emitter mesa layer 25. In the fourth embodiment, the first edge 41 is relatively far from the base electrode pad portion 32B at the terminal portion 44 closer to the base electrode pad portion 32B. Therefore, the generation of kink K (FIG. 3) due to the presence of the base electrode pad portion 32B can be suppressed. As a result, the transition voltage can be increased and the SOA can be expanded.

Next, a modified example of the fourth embodiment will be described. In the fourth embodiment, the emitter electrode 33 is arranged inside the emitter mesa layer 25 in a plan view, but the emitter electrode 33 may protrude to the outside of the emitter mesa layer 25. This configuration can be formed using, for example, a self-alignment process in which the emitter electrode 33 is used as an etching mask to etch the semiconductor layer beneath it, leaving the emitter mesa layer 25.

Further, in the fourth embodiment, the area of the plane shape of the emitter mesa layer 25 is larger than that in the second embodiment. As a result, the amount of collector current can be increased.

[Fifth Example]
Next, the semiconductor device according to the fifth embodiment will be described with reference to FIGS. 21 and 22. Hereinafter, the description of the configuration common to the semiconductor device (drawings from FIGS. 11 to 13) according to the second embodiment will be omitted.

FIG. 21 is a plan view of one of the plurality of unit transistors 70 constituting the semiconductor device according to the fifth embodiment. In the second embodiment, the emitter electrode 33 is arranged inside the emitter mesa layer 25 (FIG. 11) in a plan view. On the other hand, in the fifth embodiment, the emitter electrode 33 protrudes outside the emitter mesa layer 25.

FIG. 22 is a cross-sectional view taken along the alternate long and short dash line 22-22 of FIG. The emitter electrode 33 is arranged on the emitter mesa layer 25. The emitter electrode 33 projects laterally from the side surface of the emitter mesa layer 25 in an eaves shape. The emitter mesa layer 25 is patterned by dry etching using the emitter electrode 33 as an etching mask. For this etching, a gas that selectively etches the InGaAs contact layer 25B and the GaAs cap layer 25A with respect to the InGaP emitter layer 23, for example, a CF-based gas is used.

Next, the excellent effect of the fifth embodiment will be described. Also in the fifth embodiment, the shape and positional relationship between the emitter mesa layer 25 and the base electrode 32 are the same as in the second embodiment. Therefore, the SOA can be expanded as in the second embodiment.

Further, in the fifth embodiment, a self-alignment process of patterning the emitter mesa layer 25 with the emitter electrode 33 as an etching mask is used. Therefore, the photomask can be omitted by one layer. As a result, the manufacturing cost can be reduced.

[Sixth Example]
Next, the semiconductor device according to the sixth embodiment will be described with reference to FIG. 23. Hereinafter, the description of the configuration common to the semiconductor device (drawings from FIGS. 11 to 13) according to the second embodiment will be omitted.

FIG. 23 is a plan view of one of the plurality of unit transistors 70 constituting the semiconductor device according to the sixth embodiment. In the second embodiment, one base electrode main portion 32A is arranged between the two portions of the emitter mesa layer 25 in a plan view. On the other hand, in the sixth embodiment, the base electrode main portion 32A is also arranged outside each of the two portions of the emitter mesa layer 25 in the second direction (width direction). The shape and positional relationship between the first edge 41 of the emitter mesa layer 25 and the second edge 42 of the base electrode main portion 32A facing the first edge 41 are the same as the shape and positional relationship of both in the second embodiment.

Next, the excellent effect of the sixth embodiment will be described.
Also in the sixth embodiment, the shape and positional relationship between the first edge 41 of the emitter mesa layer 25 and the second edge 42 of the base electrode main portion 32A facing the first edge 41 is the positional relationship between the two in the second embodiment. Since they are the same, the SOA can be expanded as in the second embodiment. Further, since the base electrode main portions 32A are arranged on both sides of each portion of the emitter mesa layer 25, the base access resistance in the intermediate portion 45 of the emitter mesa layer 25 can be reduced.

Next, a modified example of the sixth embodiment will be described.
In the sixth embodiment, the double emitter structure in which the emitter mesa layer 25 is composed of two parts is adopted, but a triple emitter structure in which the emitter mesa layer 25 is composed of three parts may be adopted. In this case, it is preferable to arrange four base electrode main portions 32A. Further, the emitter mesa layer 25 may be composed of four or more portions.

[7th Example]
Next, the semiconductor device according to the seventh embodiment will be described with reference to FIG. 24. Hereinafter, the description of the configuration common to the semiconductor device (drawings of FIGS. 4 to 8) according to the first embodiment will be omitted.

FIG. 24 is a plan view of the semiconductor device according to the seventh embodiment. In the first embodiment (FIG. 4), the direction in which the first edge 41 of the two end portions 44, 46 is farther from the second edge 42 of the base electrode main portion 32A than the first edge 41 of the intermediate portion 45. It is placed in a position retracted to. On the other hand, in the seventh embodiment, the first edge 41 of the end portion 44 closer to the base electrode pad portion 32B and the first edge 41 of the intermediate portion 45 are located on one straight line. .. The first edge 41 of only the end portion 46 farther from the base electrode pad portion 32B recedes from the first edge 41 of the intermediate portion 45 in a direction away from the second edge 42 of the base electrode main portion 32A. It is placed in position.

Next, the excellent effect of the seventh embodiment will be described.
Due to thermal and electrical asymmetry factors, the emitter current may tend to be unevenly distributed in the direction away from the base electrode pad portion 32B at the time of a large current. For example, when the temperature tends to rise on the side opposite to the base electrode pad portion 32B when viewed from the emitter mesa layer 25, the emitter current tends to be unevenly distributed in the direction away from the base electrode pad portion 32B. When such a tendency is shown, if the configuration of the seventh embodiment is adopted, uneven distribution of the emitter current is less likely to occur. As a result, the transition voltage can be increased and the SOA can be expanded.

It goes without saying that each of the above embodiments is exemplary and the configurations shown in different examples can be partially replaced or combined. Similar actions and effects due to the same configuration of a plurality of examples will not be mentioned sequentially for each example. Furthermore, the present invention is not limited to the above-mentioned examples. For example, it will be obvious to those skilled in the art that various changes, improvements, combinations, etc. are possible.

20 Sub-collector layer 21 Collector layer 22 Base layer 23 Emitter layer 23A Intrinsic emitter layer 23B Ledge layer 24 Alloy layer 25 Emitter mesa layer 25A Cap layer 25B Contact layer 26 Emitter wiring edge 27 Emitter mesa layer edge 31 Collector electrode 32 Base electrode 32A Base Electrode main part 32B Base electrode pad part 33 Emitter electrode 35 Collector opening 36 Base opening 37 Emitter opening 38 Emitor current contour line 41 First edge 42 Second edge 44 End part near the base electrode pad part 45 Intermediate Part 46 End part far from the base electrode pad part 47 Boundary line between the end part and the middle part 60 Substrate 61, 62 Insulation film 63 Emitter opening 70 Unit transistor 71 Emitter common wiring 72 Via hole 75 High frequency input wiring 76 Capacitor 77 Thin film Resistance 78 Bias wiring B1 Base wiring C1 Collector wiring E1, E2 Emitter wiring

According to one aspect of the invention
It comprises a collector layer, a base layer, an emitter layer arranged on a substrate, and an emitter mesa layer arranged on a part region of the emitter layer, and the collector layer, the base layer, and the emitter layer are the same. It is stacked in order and
further,
A region that does not overlap with the emitter mesa layer in a plan view, and has a base electrode for passing a base current through the base layer.
In plan view, the emitter mesa layer has a longer first edge in a first direction,
In plan view, the base electrode has a second edge that is long in the first direction.
The first edge of the base electrode faces the first edge of the emitter mesa layer and is located on one end side of the emitter mesa layer in the first direction. Provided is a semiconductor device in which the distance between the edge and the second edge is wider than the distance between the first edge and the second edge in the intermediate portion of the emitter mesa layer in the first direction.

The base electrode 32 is composed of one base electrode main portion 32A and a base electrode pad portion 32B continuous with the base electrode main portion 32A. The base electrode main portion 32A is arranged between the two portions of the emitter mesa layer 25. The first edge 41, which is a part of each edge of the two portions of the emitter mesa layer 25, faces the base electrode main portion 32A. The second edge 42, which is a part of the edge of the base electrode main portion 32A, faces the two portions of the emitter mesa layer 25 , respectively. Of the edges of the base electrode main portion 32A, both edges in the width direction correspond to the second edge 42.

As an example, the dimension (length) of the emitter mesa layer 25 in the first direction is 5 μm or more and 80 μm or less, and the dimension (width) in the direction orthogonal to the first direction is 1 μm or more and 8 μm or less. As in the case of the first embodiment, the difference between the interval G1 and the interval G0 is preferably 0.3 μm or more and 1 μm or less. The preferred dimensions of the end portions 44 , 46, which are the portions where the distance between the first edge 41 and the second edge 42 is widened , in the first direction are the same as in the case of the first embodiment.

FIG. 20 is a plan view of one of the plurality of unit transistors 70 constituting the semiconductor device according to the fourth embodiment. In the second embodiment, in the terminal portions 44 and 46 at both ends of the emitter mesa layer 25, the first edge 41 of the emitter mesa layer 25 is a second edge of the base electrode main portion 32A rather than the first edge 41 of the intermediate portion 45 . It is arranged at a position retracted in a direction away from the edge 42. In contrast, in the fourth embodiment, the distal portion 44 closer to the base electrode pad portion 32B only, the first edge 41 than the first edge 41 of the intermediate section 45, a direction away from the second edge 42 At the opposite end portion 46, the interval G1 and the interval G0 are equal to each other.

Next, the excellent effect of the sixth embodiment will be described.
Also in the sixth embodiment, the first edge 41 of the emitter mesa layer 25, it is position relationship between the second edge 42 of the opposing base electrode main portion 32A, identical to the positional relationship between the second embodiment Therefore, the SOA can be expanded as in the second embodiment. Further, since the base electrode main portions 32A are arranged on both sides of each portion of the emitter mesa layer 25, the base access resistance in the intermediate portion 45 of the emitter mesa layer 25 can be reduced.

Claims (11)

It comprises a collector layer, a base layer, an emitter layer arranged on a substrate, and an emitter mesa layer arranged on a part region of the emitter layer, and the collector layer, the base layer, and the emitter layer are the same. It is stacked in order and
further,
A region that does not overlap with the emitter mesa layer in a plan view, and has a base electrode for passing a base current through the base layer.
In plan view, the emitter layer has a first edge that is long in the first direction.
In plan view, the base electrode has a second edge that is long in the first direction.
The first edge of the base electrode faces the first edge of the emitter mesa layer and is located on one end side of the emitter mesa layer in the first direction. A semiconductor device in which the distance between the edge of the semiconductor device and the second edge is wider than the distance between the first edge and the second edge in the intermediate portion of the emitter mesa layer in the first direction. Further, it has a base wiring arranged in a layer above the base electrode.
The base electrode includes a base electrode pad portion and a base electrode main portion extending from the base electrode pad portion in the first direction, and the base electrode pad portion is one of the emitter mesa layers in the first direction. It is arranged at a distance from the end portion in the first direction, and the base electrode pad portion is connected to the base wiring.
At the end portion of the emitter mesa layer closer to the base electrode pad portion, the distance between the first edge and the second edge is the distance between the first edge and the first edge in the intermediate portion in the first direction. The semiconductor device according to claim 1, wherein the distance from the edge of 2 is wider. The distance between the first edge and the second edge of the emitter mesa layer at the end portion far from the base electrode pad portion is the distance between the first edge and the second edge in the intermediate portion in the first direction. The semiconductor device according to claim 2, which is wider than the distance from the edge of the semiconductor device. The second edge is parallel to the first direction, and the first edge of the end portion of the emitter mesa layer closer to the base electrode pad portion is the first edge of the intermediate portion in the first direction. The semiconductor device according to claim 2 or 3, wherein the semiconductor device is arranged at a position retracted from the edge of the second edge in a direction away from the second edge. The first edge is parallel to the first direction, and at the end portion of the emitter mesa layer closer to the base electrode pad portion, the second edge is the first in the intermediate portion of the first direction. The semiconductor device according to claim 2 or 3, which is arranged at a position retracted from the edge of 2 in a direction away from the first edge. At the end portion of the emitter mesa layer closer to the base electrode pad portion, the distance between the first edge and the second edge is the distance between the first edge and the second edge in the intermediate portion. The semiconductor device according to any one of claims 2 to 5, wherein the dimension of the wider portion in the first direction is 0.5 μm or more. At the end portion of the emitter mesa layer closer to the base electrode pad portion, the distance between the first edge and the second edge is the distance between the first edge and the second edge in the intermediate portion. The semiconductor device according to any one of claims 2 to 6, which is wider than 0.3 μm. The emitter mesa layer is composed of at least two parts in a plan view, and each of the two parts of the emitter mesa layer has a long planar shape in the first direction and is orthogonal to the first direction. They are arranged in two directions with a gap,
The base electrode main portion is arranged between two portions of the emitter mesa layer in a plan view.
The edges of the two portions of the emitter mesa layer facing the base electrode main portion form the first edge, and the edges of the base electrode main portion facing the two portions of the emitter mesa layer are the first edges. The semiconductor device according to any one of claims 2 to 7, which constitutes the edge of 2. further,
An emitter electrode arranged on the emitter mesa layer and
A layer above the emitter electrode, having an emitter wiring arranged in the same layer as the base wiring and connected to the emitter electrode.
Any of claims 2 to 8 in which the shortest distance from the edge of the base electrode pad portion to the edge of the emitter wiring is longer than the shortest distance from the edge of the base electrode pad portion to the edge of the emitter mesa layer in a plan view. The semiconductor device according to item 1. The semiconductor device according to claim 9, wherein the emitter electrode protrudes outward from the edge of the emitter mesa layer in a plan view. Further, it has an emitter electrode arranged on the emitter mesa layer.
The semiconductor device according to any one of claims 1 to 8, wherein the emitter electrode protrudes outward from the edge of the emitter mesa layer in a plan view.

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