JPS63142591A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To attain simplified picture system and low cost by providing a row address generating circuit in a dual port memory thereby having only to supply a serial clock signal externally. CONSTITUTION:A final row address signal supplied externally via a row address buffer RADB is inputted to an address detection circuit RAD via a row address register RAR of a row address generating circuit RAG. Moreover, a row address counter RAC supplies a data transfer row address signal advanced at each data transfer cycle to an address multiplexer AMX and supplies it to the circuit RAD. The circuit RAD compares signals from the counter RAC and the register RAR and when they are coincident, a final address signal syn is sent to a timing control circuit TC via an AND gate circuit AG. Thus, the word line within the designated range is designated sequentially to continue the input/output operation thereby attaining simplicity and low cost.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor memory device, for example,
The present invention relates to a technology that is particularly effective when used in dual port memories that have both a random access port and a serial access port.

[Conventional technology]

Dual port memory, which is used as an image frame buffer memory for displaying characters or figures on a CRT (cathode ray tube) screen, is described in, for example, "Nikkei Electronics J, published by Nikkei McGraw-Hill, March 24, 1986. It is described on pages 243 to 264.

[Problem that the invention seeks to solve]

The dual port memory described above has a random access port that randomly inputs and outputs stored data in units of multiple predetermined bits, and a port that inputs and outputs stored data serially in units of word lines, that is, rows of the memory array. A serial access port is provided.

Serial input/output operations of stored data by the serial access port are performed, for example, by associating word lines of a dual port memory with horizontal scanning lines of a CRT, and corresponding data lines with pixels of each scanning line. As mentioned above, dual port memory performs serial input/output of stored data in word line units, so each memory access
A row address signal for specifying a word line and a number of serial clock signals corresponding to the number of pixels of each scanning line must be supplied from an external memory control device.

Therefore, the memory control device includes a multi-bit row address counter for repeatedly and sequentially specifying a number of word lines corresponding to the number of horizontal scanning lines of the CRT in synchronization with image display, and a pixel of each scanning line of the CRT. It is necessary to provide a pulse counting circuit or the like for inputting a number of serial clock signals corresponding to the number of serial clock signals. For this reason, the memory control device becomes complicated and has a large number of parts, which hinders the simplification and cost reduction of the image system.

An object of the present invention is to provide a semiconductor memory device such as a dual port memory having new functions.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical embodiments disclosed in this application is as follows. That is,
In the dual-port memory, there is a row address register that holds the final row address signal, and a word line that is incremented as data transfer cycles are performed and that repeats the word line specified by the first row address or the final row address signal. A row address counter is provided for sequential designation.

[For production]

According to the above means, it is possible to manually output the serial data necessary for image display by simply repeating the data transfer cycle while supplying a serial clock signal from the outside, thereby simplifying the image system and reducing costs. be able to.

〔Example〕

FIG. 1 shows a dual port system to which this invention is applied.
A block diagram of one embodiment of a memory is shown. Each circuit block in the figure is formed on a single semiconductor substrate such as, but not limited to, single-crystal silicon using known semiconductor integrated circuit manufacturing techniques.

The dual port memory of this embodiment is supplied with a row address strobe (No. F1 RAS), which is used in normal dynamic RAM, from an external device.

In addition to control signals such as column address strobe signal CAS and write enable signal WE, random access
Data transfer control signal D T10 R used to control data transfer between the port and the serial access port
A serial output control signal SOE used to control input/output switching of the serial access port and a serial cross signal SC used as a synchronization signal during serial input/output are input.

Random access ports are not particularly restricted, but
Its basic configuration includes four memory arrays M-ARYI to M-ARY4. Corresponding to each memory array,
Sense amplifier 5AI-3A4 and column switch C3W
I to C3W4 are provided. Also, memory array M-A
Common to RYI to M-ARY4, random access
A boat column address decoder RCD and a row address decoder RD are provided. A plurality of these address decoders may be provided depending on the arrangement of the memory array on the semiconductor substrate. FIG. 1 exemplarily shows a memory array M-ARYI and its peripheral circuits.

In FIG. 1, the memory array M-ARY1 includes m+1 word lines WO to Wm arranged in the vertical direction of the figure, and n+1 sets of complementary data lines DO and Do to arranged in the horizontal direction of the figure. (m+1)X (n+1) placed at the intersection of Dn - Dn and these word lines and complementary data lines
It is composed of dynamic memory cells.

Each word line is coupled to a row address decoder RD;
One word line specified by the row address signal is selected.

The row address decoder RD is a row address eight sofa R.
Complementary internal address signal axQ~a supplied from ADB
xi (here, for example, the non-inverted internal address signal ax
Q and the inverted internal address signal 71 are collectively expressed as a complementary internal address signal axO. The same applies hereinafter) is decoded, one word line specified by the row address signal is selected, and the selected word line is set to a high level. The word line selection operation by row address decoder RD is performed according to word line selection timing signal φX supplied from timing control circuit TC.

The row address RADB receives the row address signal supplied from the address multiplexer AMX, forms complementary internal address signals xO to Xi, and supplies them to the row address decoder RD and the row address generation circuit RAG.

The dual port memory of this embodiment has the function of performing a series of serial input/output operations necessary for image display simply by specifying the final row address and repeating the data transfer cycle. To realize this function, data transfer row address signals cxQ~
A row address generation circuit RAG forming cxi is provided. Furthermore, in the dynamic RAM of this embodiment,
X address signal AXO for specifying the row address
A so-called address multiplex system is adopted in which AXi and a Y address signal AYO=AYj for specifying a column address are supplied in a time-division manner via the same external terminals AO to Ai. Therefore, the X address signal A
XO-AXi is supplied to external terminals AO to At in synchronization with the fall of row address strobe signal RAS, and Y
Address signals AYO to AYi are applied to external terminals AO=A in synchronization with the falling of column address strobe signal CAS.
i. Furthermore, the dynamic RAM of this embodiment is provided with an automatic refresh mode for reading and rewriting data stored in memory cells within a predetermined cycle, and in this automatic refresh mode, a word line to be refreshed is specified. A refresh address counter REFC is provided for this purpose.

X address signals AXO to AXi supplied via external terminals AO to Ai and data transfer row address signals CXO to cx formed by row address generation circuit RAG
i and the refresh address signal 1j r x O” formed by the refresh address counter REFC.
r x i is input to three sets of input terminals of the address multiplexer AMX and is selected depending on the operating mode of the dual port memory.

Address multiplexer AMX selects a row address signal according to internal control signals dtm and ref supplied from timing control circuit TC. internal control signal di
m is set to a high level in a data transfer mode in which a series of data transfer cycles for image display is repeated, and the internal control signal ver is set to a high level in an automatic refresh mode of the dual port memory.

The address multiplexer AMX uses an internal control signal ref
In the normal memory access mode in which both dtm and dtm are at low level,
Select. Further, in a data transfer mode in which only internal control signal dtm is at a high level, data transfer row address signals CXO to ext supplied from row address generation circuit RAG are selected. Furthermore, the internal control signal r
In automatic refresh mode in which only ef is set to high level, refresh address signals rxo to rxi supplied from refresh address counter REFC are selected. The row address signal selected by the address multiplexer AMX is sent to the row address buffer RAD.
It is sent to B and held.

As mentioned above, since the X address signals AXO to AXi are supplied to the external terminals AO to Ai in synchronization with the falling edge of the row address strobe signal RAS, the acquisition of the row address signal by the row address buffer RADB is controlled by the timing control circuit. This is performed in accordance with a timing signal φat generated by detecting the fall of row address strobe signal RAS at TC.

As described later, the row address generation circuit RAG includes a row address register RAR and an address counter RAC.
and a final row address detection circuit RAD. The row address register RAR takes in and holds the final row address signal supplied in the second data transfer cycle of the data transfer mode of the dual port memory in accordance with the timing signal φrs supplied from the timing control circuit TC. The row address counter RAC is
In the data transfer mode of the dual port memory in which the internal control signal dtm supplied from the timing control circuit 'rC is set to high level, the internal control signal dtm is stepped in accordance with the timing signal φcc formed in each data transfer cycle,
Data transfer row address signals cxO to cxi are formed. Further, the final row address detection circuit RAD monitors the output signal of the row address counter RAC and identifies that the word line specified by the final row address held in the row address register RAR has been selected. When the timing signal φcc is supplied while the word line of the final row address is selected, the final address detection signal syn is generated. This final address detection signal syn is used to clear the row address counter RAC and is also supplied to the timing control circuit TC.

Regarding the configuration and operation of the row address generation circuit RAG,
This will be explained in more detail later.

On the other hand, complementary data line DO/ of memory array M-ARYI
DO~Dn-Dn are coupled on the one hand to the corresponding switches MO5FET of the column switch cswi, and are further selectively connected via these switches MO3FET to the complementary common data line -Q-Di (here, the complementary common data line -Q-Di). The non-inverted signal line CDI and the inverted signal line CD that constitute the
I is collectively expressed as a complementary common data line -Ω-Di. The same applies hereafter).

The column switch C3WI includes an nl-1 pair of switches MOS l" each coupled to a corresponding complementary data line.
Constructed by ET. These switches MO5F
The other terminal of the pair E'l'' is commonly coupled to the non-inverted signal line CDI or the inverted signal line CDI that constitutes the complementary common data line.Thereby, the column 1'' Sochi C3WI is connected to the memory array M-ARY1. Complementary data line DO-DO~
Dn-Dn and the common complementary data line D1 are selectively connected. The gates of the two switches MO5FET' of each pair constituting the Karanis1C3WI are connected in common, and are supplied with a data line selection signal formed by a column address decoder RCD for the random access port.

The random access port column address decoder RCD decodes the complementary internal address signals ayQ to ayL supplied from the column address buffer CADB, and according to the data line selection timing signal φyr supplied from the timing control circuit TC. A data line selection signal is formed and supplied to column switches C3WI to C3W4.

The column address buffer CADB receives a timing signal φac generated by detecting the fall of the column address strobe signal CAS in the timing control circuit TC.
Accordingly, the Y address signals AYO to AYi supplied via the external terminals AO to Ai are input and held, and complementary internal address signals ayo to h71 are formed to output the column address decoder R for the random access boat.
Supply to CD.

Complementary data lines DO・■～D of memory array M-ARY1
On the other hand, n-Dn is coupled to a corresponding unit circuit of the sense amplifier SAI, and further coupled to a corresponding unit circuit of the data register DRI of the serial access boat.

Each unit circuit of the sense amplifier SAI has a basic configuration of a launch consisting of two cross-connected CMOS inverter circuits. These sense amplifier unit circuits receive a timing signal φp supplied from a timing control circuit TC.
a, the micro-read signals outputted from the memory cells to the corresponding complementary data lines are amplified and converted into binary signals of high level/low level.

A complementary common data line CDI to which a complementary data line designated by the Y address signal AYO=AYi is selectively connected is coupled to a random input/output circuit RIO. This random input/output circuit RIO has another memory array M-ARY.
Complementary common data lines -Ω-D2 to D4 provided corresponding to M-ARY2 to M-ARY4 are similarly coupled.

Random input/output circuit RIO is data input cover sofa DI
In addition to B and data output buffer DOB, there is also an arithmetic logic unit AL that performs arithmetic processing on storage data and write data.
Contains U. Of these, the theta output huff 7DOB is activated by the timing signal φrr supplied from the timing control circuit TC in the random read mode 1- of the dual port memory, and controls the storage data read from the selected memory cell. , input/output terminal■
Output to an external device via 01 to 104. The data manual buffer DIR is controlled by the timing control circuit TC in the random write mode of the dual port memory.
The write data supplied from the external device via the input/output terminals 101-104 is set to the operating state by the timing signal φr- supplied from introduce. In addition, the arithmetic logic unit (ALU) is a dual-port
In a memory arithmetic write cycle, various arithmetic operations are performed between stored data read from a memory cell at a designated address and write data supplied from the outside. This arithmetic logic unit ALLI is provided with various operation modes for performing rask operations and the like.

The operation mode of the ALU (arithmetic logic unit) is selected and specified by the function control circuit FC. Function control 6 The control circuit FC uses external terminal A for address signal input during the operation mode setting cycle of the dual port memory.
It includes an operation code register FCR that holds the operation code supplied through O to A3, and an operation code decoder FCD for decoding the operation code and selecting and specifying the operation mode of the arithmetic logic unit 1-ALU. this house,
The operation code register FOR executes the operation code supplied via external terminals AO to A3 for address input according to the timing signal φas supplied from the timing control circuit 1C in the operation mode setting cycle of the dual port memory. The code is taken in and sent to the operational code decoder FCD of the function control circuit FC. Operation code decoder FC
D decodes these operation codes to form operation mode selection signals a m Q to am15, and designates the operation mode of the arithmetic logic unit ALU of the random input/output circuit RIO.

On the other hand, the serial access ports of the dual port memory in this embodiment are memory arrays M-ARYI to
n provided corresponding to each complementary data line of M-ARY4
71-bit data registers DRI to DR4, data selectors DSLI to DSL4, and a pointer PNT provided commonly to these data registers and data selectors.
, a serial access boat column address decoder SCD and a serial input/output circuit SIO. Note that a plurality of pointers PNT and serial access boat column address decoders SCD may be provided depending on the arrangement of the memory array on the semiconductor substrate. In FIG. 1, memory array M-AR
A data register DRI and a data selector DSLI corresponding to YI are exemplarily shown.

Data register DRI includes n11-bit flip-flops provided corresponding to each complementary data line of memory array M-ARYi. A switch MOS for data transfer is connected between the input/output nodes of these flip-flops and the non-inverted signal line and inverted signal line of the corresponding complementary data line.
FETs are provided respectively. These switches MO
The 3FETs are turned on all at once by the high level of the timing signal φdt supplied from the timing control circuit TC, and are connected between each flip-flop of the data register DRI and the fi+1 memory cells coupled to the selected word line. Input and output of stored data is performed in parallel.

The input/output terminal of each bit of the data register DPI is further connected to the corresponding switch MO5 of the data selector DSL1.
Coupled to FET. The data selector DSL1 has the same configuration as the column switch C3WI described above, and selectively connects each bit of the data register DPI to the complementary common data line CD5l for serial input/output. The gates of each pair of switching MOS FETs of the data selector DSLI are connected in common, and a corresponding data register selection signal is supplied from the pointer P N ']'.

The pointer P N T' is constituted by a shift register of n+1 bits, and the output terminal ps of its last point is coupled to the input terminal of its first bit.

In the serial input/output mode of the dual port memory, the pointer PNT performs a loop-shaped shift operation in accordance with the shift clock timing signal φC supplied from the timing control circuit 1'C. Each bit of pointer PNT is further coupled to a corresponding output terminal of a serial access boat column address decoder SCD.

The serial access boat column address decoder SCD decodes the complementary internal address signals ayQ to ayl supplied from the column address buffer CADH, and corresponds to the first bit of the serial output specified by the Y address signals AYO to AYi. Only the bit of pointer PNT is set to logic "1". In other words, in a data transfer cycle in which serial input/output of stored data is performed,
A word line is specified by address signals A.sub.XO to AXi, and a first column address at which serial input/output is to be started is specified by Y address signals AYO to AYi. The selection signal of logic "1λ0" written in the specified hint of pointer PNT by serial access boat column address decoder SCD is shifted in a loop within pointer PNT according to timing signal φC. By shifting one logic "1" selection signal in this way, a high-level data register selection signal is sequentially supplied to the data selector DSL1, and each pin 1 of the data register DRL is sequentially set for serial input/output. Complementary common data line DS
Connected to L. This makes the dual
The port memory can initiate serial input/output operations from any column address.

The complementary common data line for serial input/output -CDSL is coupled to the serial input/output circuit S10. Complementary common data lines CD32 to CL)S4 for serial input and output, which are provided corresponding to data registers DR2 to DR4 and data selectors DSL2 to DSL4, respectively, are coupled to this serial input/output circuit SIO. .

The serial input/output circuit SIO includes a serial input/output complementary common data line CD5L=CDS4 and a serial input/output terminal 3101 to 5104.
Includes main amplifier, data input buffer and data output cover sofa. The data output cover sofa of the serial input/output circuit 510 is put into an operating state by the timing signal φsr supplied from the timing control circuit TC in the read data transfer cycle of the dual port memory, and the corresponding complementary common data line for serial input/output is activated. −Ω−
Read data outputted via DS1 to CD54 and amplified by the corresponding main amplifiers is outputted from corresponding serial input/output terminals 5101 to 5104 to external devices. Further, the data input buffer of the serial input/output circuit SIO is put into an operating state by the timing signal φS- supplied from the timing control circuit TC in the write data transfer cycle of the dual port memory, and the data input buffer of the serial input/output circuit SIO is put into an operating state by the timing signal φS- supplied from the timing control circuit TC. Write data supplied from an external device through lines 5104 to 5104 is made into a complementary write signal, and is once transmitted to the corresponding serial input/output complementary common data line -CDSL to DS4.

The timing control circuit TC receives a positive row address strobe signal supplied as a control signal from the outside, a column address strobe signal CAS, and a write enable signal 7.
π, data transfer control signal stone 〒/σ1, and serial output control signal SOE to form the above-mentioned various internal control signals and timing signals and supply them to each circuit. In addition, a timing signal φC for synchronizing serial input/output operations is formed by a serial clock signal SC supplied from the outside, and a timing signal φC for synchronizing the serial input/output operation is generated, and the pointer PNT and serial input/output circuit S10
supply to. Furthermore, the timing control circuit TC receives a final address detection signal Sy from the row address generation circuit RAG.
n, forms a bright line sweep synchronizing signal SYN, and outputs it to the CRT to which this dual port memory is connected.

FIG. 2 shows a circuit block diagram of an embodiment of the row address generation circuit RAG of the dual port memory of this embodiment.

In FIG. 2, the final row address signal supplied from an external device via the row address buffer RADB is
The signals are supplied to corresponding bits of the row address register RAR via internal address signal lines axQ to axi. The row address register RAR includes a timing control circuit T.
A timing signal φrs is supplied from C.

As mentioned above, the dual port memory of this embodiment has a data transfer mode in which serial input/output operations of stored data necessary for image display are performed by repeating data transfer cycles without supplying a row address signal. is provided. In this data transfer mode, the final row address signal is input in the second data transfer cycle of a series of data transfer modes in order to provide a margin for control timing of the main device. In the first data transfer cycle of the data transfer mode, the row address signal and column address signal are all set to logic "0", and the selection operation of the word line and data line is performed by selecting the word line WO and the complementary data line DO-D. It starts from the end. The timing signal φrs supplied from the timing control circuit TC to the row address register RAR is formed in the second data transfer cycle of the data transfer mode of the dual port memory.

The row address register RAR is controlled by the timing control circuit T.
According to the timing signal φrs supplied from C, the final row address signal input via the row address buffer RADB is taken in and held. The final row address held in the row address register RAR is supplied bit by bit to one input terminal of the final row address detection circuit RAD.

The row address counter RAC is composed of an i+l bit pinary counter. Clock input terminal Cp and enable terminal En of row address counter RAC
, a timing signal φ is sent from the timing control circuit TC.
cc and internal control signal dtm are respectively supplied. Also, the clear terminal Cr of the row address counter RAC is connected to the AND gate circuit AG of the row address generation circuit RAG.
The output signal of , that is, the final address detection signal syn is input. The output signal of the row address counter RAC is supplied as the data transfer row address signals cxQ to Cxi to the address multiplexer AMX and also to the final row address detection circuit RAD.

The row address counter RAC is activated by the internal control signal dtm, which is set to high level in the data transfer mode of the dual port memory, and increments in synchronization with the rising edge of the timing signal φcc, which is generated in each data transfer cycle. be done. Row address counter RA
As will be described later, C is cleared by the final address detection signal syn, which is generated when the timing signal φcc is supplied with the word line specified by the final row address signal selected, and is cleared from the first word line WO. Word line Ws specified by final row address signal
Specify sequentially by cycling.

The final row address detection circuit RAD compares the data transfer row address signals cxQ to cxi supplied from the row address counter RAC and the final row address signal supplied from the row address register RAR bit by bit, and determines whether both address signals are When all bits match, the output signal, that is, the final row address detection signal raf is set to high level. Since the address comparison result by the final row address detection circuit RAD is determined in synchronization with the falling edge of the timing signal φcc supplied from the timing control circuit 1'C, the final row address detection signal raf is determined by the timing signal In synchronization with the fall of φcc, °ζ is set to high level or low level.

The final row address detection signal raf output from the final row address detection circuit RAD is supplied to one input terminal of the AND gate circuit AG. This AND gate circuit A
The timing signal φcc is supplied to the other input terminal of C. As a result, the output signal of the AND gate circuit AG is output when the final row address detection signal raf and the timing signal φcc are both at high level, that is, the next data transfer cycle in which the word line specified by the final row address signal is selected. It becomes high level at the beginning of the data transfer cycle. The output signal of the AND gate circuit AG is supplied as the final address detection signal syn to the clear terminal Cr of the row address counter RAC, and sets the count value of the row address counter RAC to the initial state of all bit logic "θ". Further, this final address detection signal syn is sent to the timing control circuit TC, and is further sent to the CRT to which this dual port memory is connected.
The bright line sweep synchronization signal SYN is output as the bright line sweep synchronization signal SYN. From these facts, the dual port memory of this embodiment is
Once the data transfer mode is started, as long as the data transfer cycle is repeated, the word line WO at the first row address or the word line Ws specified by the last row address signal is repeatedly and sequentially specified, and serial input/output operations continue. do.

FIG. 3 shows a conceptual diagram when a CRT display image is obtained using the data transfer mode of the dual port memory of this embodiment.

Dual J/Bow I...Memory is (m+1) X (n
+1) bit storage capacity, X of the display image in Figure 3
The word lines WO to Wm are on the axis coordinates, that is, the horizontal scanning line xO%Xm, and the complementary data lines are on the Y axis coordinates yO-yn, that is, the pixels on each horizontal scanning line.

・■1 to Dn-Dn correspond to each other.

In this embodiment, the CRT to which the dual-port memory is connected has s+1 horizontal scanning lines and s''+1 pixels. Therefore, the data transfer mode of the dual-port memory is such that the stored data is The memory area for serial input/output is limited to the area shaded in FIG. 3. That is, the final row address "xs" is given in the second data transfer cycle in the data transfer mode. Therefore, the data transfer cycle The word line selected by repetition is the first row address “xO”
word line WO or final row address “xs” corresponding to
”.On the other hand,
The number of serial clock signals SC supplied in each data transfer cycle is s'+1.

Therefore, the storage data serially input/output in each data transfer cycle is stored at the first column address “yO
Complementary data line DO/DO corresponding to ' or complementary data line DS° corresponding to final column address "yso"
・Limited to the range of ■τ°. As a result, the stored data that is serially input/output to the dual port memory by repeating the data transfer cycle is transferred directly to the C
This corresponds to one display image of RT.

FIG. 4 shows a timing diagram of one embodiment of the read data transfer cycle of the dual port memory of this embodiment. The dual port memory is provided with a write data transfer cycle for serially writing image data and a read data transfer cycle for serially outputting image data to a CRT. By repeating these write data transfer cycles or read data transfer cycles, the dual port memory is placed in data transfer mode. With reference to the figure, an overview of the operation of the data transfer mode using the read data transfer cycle of the dual port memory will be explained.

In FIG. 4, the dual port memory is activated by changing the row address strobe signal RAS from high level to low level. Also, prior to the fall of the row address strobe signal πτ1, the write enable signal W100 is set to high level, and the data transfer control signal 1/1 and the serial output control signal g
In the unlikely event that they occur, both are considered to be low level. Furthermore, at the same time, a serial clock signal SC is supplied at a predetermined period. As a result, the dual port memory enters a read data transfer cycle, and a data transfer mode for reading stored data is started. In this data transfer mode, this first data transfer cycle cy,
Starting from o, the second data transfer cycle Cy,
l to S+1st data transfer cycle Cy, s.
It is executed by multiple data transfer cycles repeated as .

The first row address, that is, the row address of all pins logic "O" is supplied to the external terminals AO to Ai prior to the fall of the row address strobe signal RAS.

This first row address is essentially a dual port address.
It is used to initialize the row address counter RAC of the memory, but since all bits are logic "O", there is no need for the main device to perform any particular process for setting the address.

In the dual port memory, at the fall of the row address strobe signal ττ in the first data transfer cycle cy, o, the internal control signal dtm is first set to high level, indicating that the data transfer mode is in progress. , row address counter RAC is activated. Further, in the address multiplexer AMX, the data transfer row address signal cxO-ext supplied from the row address counter RAC as a row address signal is selected by the high level of the internal control signal dtm and the low level of the internal control signal ref. As a result, the data transfer row address signal cx is supplied to the row address decoder RD.
Q~cxi, that is, the all-bit logic "θ" which is the initial value of the row address counter RAC is sent.

When the row address decoder RD finishes decoding the data transfer row address signal cxQ-cxi, the word line selection timing signal φX is set to high level, and a little later, the timing signal φpa is set to high level.

As a result, the word line WO is put into a selected state, and the minute read signals of the H+1 memory cells coupled to this word line WO are output to the corresponding complementary data lines, and are processed by the corresponding unit circuits of the sense amplifiers SAI to SA4. amplified. At the point in time when the level of each complementary data line is established at high level or low level by the amplification operation of the sense amplifier, the timing signal φdt is set to high level. As a result, the corresponding bits of the n+1 bits of storage data read registers DRI to DR4 read out to each complementary data line are
It is taken in all at once.

Next, column address strobe signal στ lower is changed from high level to low level. Prior to the fall of the column address strobe signal CAS, the first column address signal "yO", that is, the Y address signal AYO-AYi of all pins logic "O" is applied to the external terminals AO-At.
is supplied.

This first column address signal also has all bits of logic "0" like the first row address signal, so no processing by the main device is required.

In the dual port memory, the leading column address "yO" is taken into the column address buffer CADH by the fall of the column address strobe signal CAS, and a decoding operation by the serial access boat column address decoder SCD is started.

At the time when the serial access boat column address decoder SCD finishes decoding the first column address signal, the data line selection timing signal φys is set to high level, and the first column l of the pointer PN'r: response signal "yo", i.e. A selection signal of logic "1" is set in the bit corresponding to the complementary data line DO.

When the dual port memory is ready for serial output operation and the CRT is ready for reception, the data transfer control signal 2/σ1- is changed from high level to low level. With the fall of the data transfer control signal /σ1, the timing signal φsr is set to high level in the dual port memory, and the timing signal φC is generated in synchronization with the serial clock signal SC. As a result, serial input/output terminals 5101 to 5IO4
The first read data, that is, the address “xO−
yO" is output. Thereafter, the pointer PNT is shifted in synchronization with the rise of the serial clock signal SC and the timing signal φC, and the corresponding memory array M is output to the serial input/output terminal 5IOI-5104. -ARYI-M-ARY4 address "xO・y1"
to XO·ys''' are serially output one after another.

Of the memory cells coupled to the word line WO, 8 +
When the bit corresponding to the first complementary data line Ds" 51°, that is, the stored data of the address "xO ySo" is output, the data transfer control signal DT/σ is returned to high level, and the serial clock signal The SC is stopped, which prepares the dual port memory for the next data transfer cycle.

The second data transfer cycle C)j,1 is started by the fall of the row address strobe signal Wτ1. As described above, prior to the fall of the row address strobe signal RAS in the second data transfer cycle cy, x, the final row address signal "xs" is supplied to the external terminals AO to At.

In a dual port memory, the timing signal φ is triggered by the fall of the row address strobe signal RAS.
ar (not shown) and a timing signal φrs are formed. As a result, the final row address signal "XS"
is taken into the row address counter RGADH, and then the row address register RA
It is taken into R and retained. At the same time, timing signal φcc is generated, row address counter RAC is incremented, and word line selection timing signal φ
The word line W1 is set to a selected state by the high level of X. Thereafter, in the same manner, the data stored in the n+l bit memory cells coupled to this word line W1 is read out.
According to timing signal φdt, data register DRI
~Imported in parallel to DR4. Also, by changing the column address strobe signal CAS from high level to low level with a slight delay, the first column address "
yo'' is taken in, and the second serial output operation of stored data is performed by the timing signal φsr being at a high level.

Thereafter, after the third data transfer cycle, only the first column address "yO" is supplied to the external terminals AO to Ai, and the same serial output operation is repeated.

When the (s+1)th data transfer cycle Cy,s is started, the row address counter RAC is incremented by the timing signal φcc, and when the counted value matches the final row address "xs", the final row address detection signal ra is activated.
f becomes high level in synchronization with the falling edge of the timing signal φCC. The high level of this final row address detection signal raf is strobed by the timing signal φCC of s+1 in the next S+2nd data transfer cycle C)', and the final address detection signal syn is set to high level.

Due to the high level of this final address detection signal syn,
The row address counter RAC is cleared, and its count value is the first row address "xO", that is, all pinpoint logic '0'.
”. Also, this final address detection signal syn
is sent to the timing control circuit TC, and is further output as a CRT bright line sweep synchronization signal SYN. As a result, the bright line of the CRT is swept, and the data stored in the word line WO starting at the address "xO.yO' is serially outputted to the serial input/output terminals 5101 to 5104.

As described above, the dual port memory of this embodiment includes a row address register RAR that holds the final row address "xs" given from the outside, and a row address register RAR that holds the final row address "xs" given from the outside, and a row address register RAR that stores the final row address "xs" from the first row address "xo". A row address generation circuit RAG including a row address counter RAC for sequentially specifying word lines WO to Ws is provided. Further, the final day address "xs" is input in the second data transfer cycle of a series of data transfer cycles in the data transfer mode, and the final address detection signal syn of the row address generation circuit RAG is
It is output as the T bright line sweep synchronization signal SYN. For this reason, dual-port
The memory control device provided outside the memory only needs to have a control circuit for repeating the data transfer cycle and a frequency dividing circuit for manually inputting the serial clock signal SC by a predetermined number depending on the number of pixels. Therefore, the configuration of the memory control device is simplified, and the cost of the entire image system can be reduced.Furthermore, the final row address signal is input in the second data transfer cycle of a series of data transfer modes. By doing so, a processor with relatively slow processing speed can be used as the main device. Furthermore, by using the final address detection signal syn, the bright line sweep synchronization signal can be obtained relatively easily.

As shown in the above embodiment, when this invention is applied to a semiconductor storage device such as a dual port memory that has both a random access port and a serial access port, the following effects can be obtained. It will be done. That is, (1) In the dual port memory, there is a row address register that holds the final row address signal supplied from the outside, and a word line specified by the final row address signal is sequentially connected from the word line of the first row address to the word line specified by the final row address signal. By providing a row address generation circuit including a row address counter for designation, it is possible to simplify the configuration of a memory control device provided outside the dual port memory.

(2) Manage the dual port memory by inputting the final row address signal in the second and subsequent data transfer cycles of a series of data transfer cycles that are repeated as the data transfer mode of the dual port memory. The advantage is that an inexpensive processor with relatively slow processing speed can be used as the main device.

(3) By outputting the final address detection signal generated by the row address generation circuit of the dual port memory from an external terminal, the bright line sweep synchronization signal of the CRT can be obtained relatively easily. It will be done.

(4) The above items (11 to 11) provide the effect of realizing an image system that is simplified and lowered in cost and is relatively easy to control.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the embodiment shown in FIG. 1, the first row address is fixed as "SO",
The final row address can be set externally, but conversely, the final row address may be fixed to, for example, "sm" and the first row address can be set externally, or the first row address and Both final row addresses may be set arbitrarily from the outside.

In this case, the first row address may be initialized in the row address counter RAC at the time it is supplied from the outside. In addition, in the embodiment shown in FIG. 1, an address counter is provided only for the row address system, but by providing a column address counter, it is possible to autonomously manage the serial clock signal SC within the dual port memory. It is also good to do this. Furthermore, the dual port memory shown in Figure 1 uses a common column address decoder RCD for the random access port and a column address decoder SCD for the serial access port, or each memory array is configured with multiple memory mants. Various embodiments can be adopted for the bronch configuration and the combination of control signals.

In the above explanation, the invention made by the present inventor was mainly explained in the case where it was applied to a dual port memory for an image system, which is the field of application that formed the background of the invention, but it is not limited thereto. It can also be applied to non-system uses and other multi-port memories. The present invention is widely applicable to semiconductor memory devices having at least a random access port and a serial access port, and semiconductor devices incorporating such semiconductor memory devices.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, in the dual port memory, there is a row address register that holds the final row address signal supplied from the outside, and a word line designated by the final row address signal is sequentially specified from the first row address port line. By providing a row address counter for
The configuration of the memory control device provided outside the dual port memory can be simplified, and an image system that is easy to control at low cost can be realized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a dual port memory to which the present invention is applied, and FIG. 2 shows an embodiment of the row address generation circuit of the dual port memory of FIG. Block diagram; Figure 3 is a conceptual diagram for explaining the image display operation of the image system using the dual port memory in Figure 1; Figure 4 is a readout diagram of the dual port memory in Figure 1. FIG. 2 is a timing diagram illustrating one embodiment of a data transfer cycle. M-ARYl...Memory array, SAl...Sense amplifier, C3WI...Column switch, DRI...
Data register, DSL 1...Data selector, P
NT...Pointer, RD...U)'Trace decoder//', RCD...Column address decoder for random access boat, 5CLI...Column address decoder for serial access boat, CADB...
・Column address buffer, RADB... row address buffer, AMX... address multiplexer,
RAG...Row address generation circuit, RIO...Random input/output circuit, FC...Function control circuit, S10...
・Serial input/output circuit, 'IC...timing control circuit, REFC...refresh address counter. RAC: Row address counter, RAR: Row address register, RAD: Final row address detection circuit, AG: AND gate circuit.

Claims (1)

[Claims] 1. A memory array consisting of a plurality of word lines, a plurality of data lines, and a plurality of memory cells arranged in a grid at the intersections of these word lines and data lines, and a memory array that is supplied from an external terminal. a row address generation circuit that sequentially selects word lines within a designated predetermined range of the memory array by automatically incrementing the address in memory access with a predetermined combination of control signals; 1. A semiconductor memory device comprising a serial-to-parallel conversion circuit that serially inputs and outputs data stored in a plurality of memory cells coupled to a word line designated by an address generation circuit in accordance with a clock signal supplied from the outside. 2. The semiconductor memory device is a dual port memory that also has a random input/output circuit, and the row address generation circuit includes a row address register that holds a final row address signal supplied from the outside, and a row address register that holds the final row address signal supplied from the outside. A final row address detection circuit that identifies that the word line designated by the final row address signal has been selected; and a final row address detection circuit that sequentially detects the word line at the first row address of the memory array or the word line designated by the final row address signal. 2. The semiconductor memory device according to claim 1, further comprising a row address counter circuit for selection. 3. Claim 1, wherein the final row address signal is input in a second or subsequent memory access among the memory accesses in which the control signals are a predetermined combination. Or the semiconductor memory device according to item 2. 4. The output signal of the final row address detection circuit is outputted from a predetermined external terminal as a bright line sweep synchronization signal of a CRT display device to which the semiconductor memory device is connected. Range 1st term,
The semiconductor memory device according to item 2 or 3.