JPS63142060U - - Google Patents
Info
- Publication number
- JPS63142060U JPS63142060U JP3384287U JP3384287U JPS63142060U JP S63142060 U JPS63142060 U JP S63142060U JP 3384287 U JP3384287 U JP 3384287U JP 3384287 U JP3384287 U JP 3384287U JP S63142060 U JPS63142060 U JP S63142060U
- Authority
- JP
- Japan
- Prior art keywords
- relative speed
- bit clock
- voltage
- magnetic tape
- controlled oscillator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 4
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Signal Processing For Digital Recording And Reproducing (AREA)
Description
第１図はこの考案の一実施例の回路構成を示す
ブロツク図である。
１…磁気テープ、２…ドラム、３，４…回転磁
気ヘツド、５…再生アンプ、６，７…イコライザ
、８…コンパレータ、９…位相比較器、１０，１
６，１８…フイルタ、１１…加算器、１２…電圧
制御発振器（ＶＣＯ）、１３…ＰＬＬ回路、１４
…相対速度検出回路、１５…ＰＷＭ信号変換回路
、１７…レベル調整回路、１９…ドライバ、２０
…リールモータ、２１，２２…リール。
FIG. 1 is a block diagram showing the circuit configuration of an embodiment of this invention. 1... Magnetic tape, 2... Drum, 3, 4... Rotating magnetic head, 5... Reproduction amplifier, 6, 7... Equalizer, 8... Comparator, 9... Phase comparator, 10, 1
6, 18... Filter, 11... Adder, 12... Voltage controlled oscillator (VCO), 13... PLL circuit, 14
...Relative speed detection circuit, 15...PWM signal conversion circuit, 17...Level adjustment circuit, 19...Driver, 20
...Reel motor, 21, 22...Reel.
Claims (1)
た再生デジタル信号からビツトクロツクを生成す
るビツトクロツク生成装置において、 位相比較器、フイルタ及び電圧制御発振器から
なるＰＬＬ回路と、 高速サーチ時に動作し、回転ヘツドと磁気テー
プとの相対速度を検出する相対速度検出回路と、 この相対速度検出回路の検出結果に応じて作成
した相対速度誤差電圧をリールモータ制御系に出
力すると共に、上記ＰＬＬ回路内の電圧制御発振
器に制御電圧として印加する電圧印加手段と を具備したことを特徴とするビツトクロツク生成
装置。[Claims for Utility Model Registration] A bit clock generation device that generates a bit clock from a reproduced digital signal obtained by scanning a magnetic tape with a rotating head, comprising a PLL circuit consisting of a phase comparator, a filter, and a voltage controlled oscillator, and a high-speed search. A relative speed detection circuit that operates to detect the relative speed between the rotating head and the magnetic tape, and outputs a relative speed error voltage created according to the detection result of this relative speed detection circuit to the reel motor control system. 1. A bit clock generation device comprising voltage application means for applying a control voltage to a voltage controlled oscillator in a PLL circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3384287U JPS63142060U (en) | 1987-03-10 | 1987-03-10 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3384287U JPS63142060U (en) | 1987-03-10 | 1987-03-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63142060U true JPS63142060U (en) | 1988-09-19 |
Family
ID=30841825
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3384287U Pending JPS63142060U (en) | 1987-03-10 | 1987-03-10 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63142060U (en) |
-
1987
- 1987-03-10 JP JP3384287U patent/JPS63142060U/ja active Pending
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