JPS5851281B2 - digital servo circuit - Google Patents

Description

Detailed Description of the Invention For example, in a VTR, in order to servo control the rotational phase of a rotating magnetic head, a vertical synchronizing pulse in a video signal to be recorded or a control pulse reproduced from a video tape and a control pulse of the head are used. The phase of the head is compared with a pulse indicating the rotational phase, and the head drive motor is controlled by the comparison output.

In this case, if the signal is processed digitally, there will be no circuit drift, so there will be no need for integral compensation, which is often used in analog systems, and the transient response will be improved accordingly.

However, when digitized, quantization noise occurs,
In a VTR, this causes jitter and degrades the quality of the reproduced image, so the number of bits (quantum number) must be increased.

In particular, when the head starts to rotate or when the head starts scanning a video track from a non-recorded area, the rotational phase of the head is largely deviated, so in order to lock to the correct rotational phase from this state, it is necessary to The number of bits must be increased to correspond to the shift.

However, if the number of bits is simply increased, the number of bits will increase to 15 to 20 bits, and the circuit scale will become significantly larger if an attempt is made to obtain performance equivalent to that of an analog type.

The present invention aims to provide a digital servo circuit that takes these points into consideration.

Therefore, in the present invention, in the case of a VTR, first, only whether the rotational phase of the head is ahead or behind the reference is detected using binary values n Oyl and n 1'', and each detection is As shown in Fig. 2 (■), the rotational phase is controlled by a certain amount Aθ to lock it to the correct rotational phase, and once the rotational phase is locked, a rest period Tr is provided in the control of the rotational phase to maintain the locked state. This is what I did.

Let's explain one example below.

In FIG. 1, reference numeral 1 indicates a motor for rotationally driving a rotating magnetic head, and pulses from a pulse generation circuit 2 are
The phase shift output is supplied to the variable digital phase shift circuit 3 and digitally shifted by a predetermined amount, and the phase shift output is supplied to the drive circuit 4 where it is D-A converted and used as a drive signal for the motor 1. Motor 1 is supplied with phase shift circuit 3.
It rotates at a speed corresponding to the amount of phase shift.

Reference numeral 11 denotes a reference pulse Pa as shown in FIG. Control pulses are supplied for playback from the tape.

Further, 12 indicates a pulse generating means, which is connected to the motor 1.
Alternatively, it may be provided rotatably coupled to the head, as shown in Figure 2B.
As shown in , the pulse Pb indicating the rotational phase of the head is
It is taken out every revolution of the head.

For example, when recording, when the record button is operated, a pulse Pr is supplied to the terminal 13, and this pulse Pr is sent to the up/down counter 15 and the up counter 16.
, are supplied to the RS flip-flop circuit 17 as a reset pulse, and these circuits M15 to M17 are reset.

Furthermore, when the motor 1 starts rotating by operating the record button (or even if it is already rotating), a reference pulse Pa is applied to the clock terminal Cp of the falling trigger type D flip flow circuit 21 at time t1 through the terminal 11. At the same time, the pulse Pb from the pulse generating means 12 is supplied to the data terminal of the flip-flop circuit 21 through the pulse amplifier 22.

Therefore, at this time, if the rotational phase of the head is ahead of the reference and the trailing edge of pulse Pb is ahead of the trailing edge of pulse Pa as shown in FIGS. 2A and B, then the flip-flop circuit From the Q terminal of the flip-flop circuit 21, a falling signal SC is obtained as shown in FIG.

Further, the pulse Pb from the amplifier 22 is supplied to the frequency dividing circuit 23 which performs frequency division, and at this time, a falling signal is generated from the flip-flop circuit 17, which is reset by the pulse Pr, as shown in the second figure. Sd is taken out, and this signal Sd is supplied to the frequency divider circuit 23 as a control signal for its frequency division operation, and the frequency divider circuit 23 is brought into a state in which it does not perform the division operation.

Therefore, a pulse Pe is obtained from the frequency dividing circuit 23 at time t1 as shown in FIG. 2E.

This pulse Pe is supplied to the AND circuit 24, and at the same time, the signal Sc from the flip-flop circuit 21 is supplied to the AND circuit 24.
As shown in the figure, a pulse Pf is taken out at time t1, and this pulse Pf is supplied to the up-count terminal UP of the counter 15.

Therefore, the count content of the counter 15 increases by [1], and since this content is supplied to the phase shift circuit 3 as its control signal, the phase shift amount of the phase shift circuit 3 lags behind the reference state by Aα. state.

Therefore, the rotational speed of the motor 1 is slowed down, and the rotational phase of the head is delayed by Aθ as shown in FIG. 2I.

In this way, even if the rotational phase of the head is delayed by Aθ, the overall head is still ahead of the standard.
The above operation is repeated for each pulse Pa, and the rotational phase of the head is delayed by Aθ.

Then, when the rotational phase of the head is further delayed by Jθ at time t2, this rotational phase is delayed from the reference.

Then, at time t3 when the pulse Pa is next supplied, the phase of the pulse Pb lags behind the pulse Pa.

Therefore, since the signal SC from the flip-flop circuit 21 falls at time t3, the pulse P from the AND circuit 24
f becomes unobtainable.

On the other hand, at the same time as the signal SC from the flip-flop circuit 21 falls at time t3, the signal from its Q terminal rises.

Then, this signal and the pulse Pe from the frequency dividing circuit 23 are supplied to the AND circuit 25, and from the AND circuit 25, the second
As shown in FIG. G, a pulse Pg is obtained at time t3, and this pulse Pg
supplied to

Therefore, the contents of the counter 15 decreases by [1], so
The phase shift amount of the phase shift circuit 3 is advanced by Aα, so the rotational speed of the motor 1 becomes faster, and the rotational phase of the head becomes Aα.
It advances by θ and becomes in a state where it has advanced further than the standard.

However, when the pulse Pa is supplied at the next time t4, the pulse Pb is ahead of the pulse Pa in phase, so the signal Sc from the flip-flop circuit 21 rises again, and the pulse Pf is obtained from the AND circuit 24. , the pulse Pg from the AND circuit 25 is no longer obtained.

Therefore, the content of the counter 15 increases by [1], so
The circuit phase of the head is delayed by Aθ and is in a state delayed from the reference.

Therefore, thereafter, the operation is repeated from time t2 to t4, and the rotational phase of the head is locked within the range of Aθ from the reference.

However, if this is done alone, the rotational phase of the head will be advanced or delayed for each pulse Pa, making it unstable.

Therefore, a rest period Tr is provided, and the period of control of the rotational phase is lengthened.

That is, the signal Sc from the flip-flop circuit 21 is supplied to the differentiating circuit 18, and the signal Sc is output as shown in FIG. 2H.
A pulse Ph is formed at each rise and fall of c, and this pulse Ph is supplied to the counter 16 as a counting input, and its counting output is supplied to the set terminal S of the flip-flop circuit 17, so that the counter 16 receives the pulse Ph When, for example, 2 is counted, that is, at time t4, the flip-flop circuit 17 is set and the signal Sd therefrom rises at time t4 as shown in the second diagram.

When the signal Sd is rising, the frequency dividing circuit 23 performs frequency division of the sum.

Therefore, even if the pulse Pa is supplied at the next time t5, the frequency dividing circuit 23 divides the pulse Pb into % to produce the pulse Pe, so the pulse Pe is not obtained at the time t5, and therefore the pulses Pf and Pg are also Therefore, the rotational phase is not controlled at time t5.

This state continues, and when the eighth pulse Pa is reached from time t5 to time t6, the pulse Pe is obtained from the frequency dividing circuit 23, so that, for example, the AND circuit 25 Pulse Pg is obtained from
Therefore, the rotational phase of the head is advanced by Jθ.

Thereafter, the rotational phase of the head is controlled at every eight pulses Pa, and the locked state is maintained.

In this way, the rotational phase of the head is servo-controlled. In this case, according to the present invention, the flip-flop circuit 21 only uses the pulses Pa and Pb to determine whether the rotational phase of the head is ahead or behind the reference. ! Q
Since servo control is performed by detecting binary values of +1 and ++111, the number of bits is minimal, and as is clear from FIG. 1, the configuration does not become complicated or large-scale.

Further, Aθ corresponds to quantization noise, but even if it is reduced, the number of bits does not increase, so the quantization noise can be sufficiently reduced.

Also, when the rotational phase of the head is locked to the reference phase,
Since the control cycle becomes longer due to the rest period Tr, instability does not occur.

Note that in the above description, time t2. This is a case where the pulse Ph detects that the rotational phase of the head crosses the reference phase twice at t3, and a pause period Tr is provided, but the number of crossings may be two or more times.

In addition, the output signal of the flip-flop circuit 21 is pulsed Pa
It is also possible to provide the pulse with a rest period Tr using the output signal of the frequency dividing circuit 23 and then supply it to the counter 15.

Furthermore, the present invention is applicable not only to servo control of the rotational phase of a head but also to other servo control circuits.

[Brief explanation of the drawing]

FIG. 1 is a system diagram of an example of the present invention, and FIG. 2 is a waveform diagram for explaining the same. 15 is an up/down counter, 16 is an up counter,
18 is a differentiating circuit, and 23 is a frequency dividing circuit.

Claims (1)

[Claims] 1 The up/down counter whose count contents are supplied to the drive system of the rotary body as a signal to control the rotation of the rotary body, and only the direction of the phase shift between the pulse indicating the rotational phase of the rotary body and the reference pulse are ``91191''; a second detection circuit that detects when the detection output of the first detection circuit is inverted at least twice; and a pulse or pulse indicating the rotational phase. a frequency dividing circuit that divides the frequency of one of the reference pulses at a predetermined ratio;
The counting direction of up-counting or down-counting is controlled by the detection output of the detection circuit, and one of the divided pulse frequency-divided in the frequency dividing circuit and the original pulse that is not frequency-divided is The pulses are controlled and supplied by the detection output of the detection circuit, and when the detection output of the second detection circuit is not obtained, the original pulse is counted by the up-down counter and the rotational phase of the rotating body is controlled by servo control. and when the detection output of the second detection circuit is obtained, the frequency-divided pulse is counted by the up-down counter to servo-control the rotational phase of the rotating body.