JPS63141347A - Manufacture of monolithic integrated circuit - Google Patents

Abstract

PURPOSE:To improve yield and to decrease the days required for manufacturing by a method wherein a monitoring resistance element equipped with two openings or more is provided on an insulating film on an impurity region and the resistance value of the element is determined prior to a wiring process. CONSTITUTION:A P-type impurity region 11 is formed on a primary surface of a semiconductor substrate whereon an N-type epitaxial layer has been grown. Openings 12 and 13 are selectively provided in an insulating film covering the P-type impurity region 11, and platinum silicide is formed in the openings 12 and 13, and a probe is applied to the openings 12 and 13 for measuring resistance. After the measurement, wirings are provided only on substrates whose resistance falls in a specified range of values. A monitoring resistance element impurity region width W1 and length L1 are so designed as to be equal to the width and length, respectively, of an circuit internal resistance element to be measured.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a gate array type master slice type monolithic integrated circuit (hereinafter referred to as gate array) including a monolithic multiplication circuit and a bipolar transistor in 45+.

[Conventional technology]

Conventionally, in a gate array capable of forming integrated circuits having various circuit functions, a resistor element for monitoring the resistance value of a resistor element inside the circuit was formed using a resistor element of the same type as a resistor wire inside the circuit during the process of forming a common substrate of the gate array. is formed on a common substrate, and during the wiring process, all the wiring is drawn out from this resistor element, the entire wiring area that can be measured by the probe is formed, and after the wiring process is completed, the resistance value of the monitor resistor VL resistor is measured. I ran into a lot of stuff.

[Problem that the invention seeks to solve]

The resistance value of a resistance element inside an integrated circuit is determined by the accuracy of a diffusion mask and variations in impurity concentration, and therefore influences the power consumption and processing speed of the circuit. Recently, customers have strict requirements regarding power consumption and processing speed, and the tolerance range for variations in the accuracy and impurity concentration of this resistance value diffusion mask may be narrower than the variations determined by manufacturing technology. With the above-mentioned monitor resistor, the resistance value of the monitor resistor inside the circuit cannot be known until after the wiring process is completed, and the accuracy of the diffusion mask and the variation in impurity concentration must be within the allowable range in advance. It is not possible to perform the wiring process after selecting the above, which has the drawbacks of lowering the manufacturing yield and prolonging the manufacturing time due to remanufacturing.

[Elaborate means to solve problems]

In the gate array type master slice method monolithic integrated circuit manufacturing method of the present invention, the resistance value of the monitoring resistance element is measured and calibrated by first setting the element forming metal, and then the wiring process is performed. That is, according to the manufacturing method of the monolithically integrated 1gJ circuit of the present invention, the resistance value of the monitor resistor element of the lPjw/& inner blade part can be known before the wiring process is performed. The resistance value can be measured using a resistance element, and a common substrate having a desired resistance value can be selected and used, thereby increasing the manufacturing yield and shortening the number of manufacturing days.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a plan view of a monitoring resistance element according to a first embodiment of the present invention. P-type impurity region 11 is selectively formed on one main surface of a semiconductor substrate on which a hemi-shaped epitaxial layer is grown. This impurity region 11 is covered with apertures 12.13 on the P3 edge film, and the apertures 12,13 are
All platinum silicide is formed on the probe, and all resistance values are measured using all teeth of the probe. After the measurement, a wiring process is performed only on semiconductor substrates having resistance values within a predetermined range. This monitor resistor element is coated with a film during the wiring process and is not wired.

The manufacturing process of this monitor resistance element is the same as the fPF manufacturing process of the resistance element inside the circuit, and by implementing the present invention, no new manufacturing process is required.

The impurity region width Wl and impurity region length L1 of the monitoring resistance element are equal to the resistance element width and resistance element length' of the resistance element inside the circuit to be measured, respectively. Here, it is assumed that the impurity region @Wli is 5 μm and the impurity region length Llt is 100 μm.The opening portion is 40 μm×40 μm excluding the protrusion.

Assuming that the layer resistance of the impurity region 11 is "ftPs" and the contact resistance between the opening and the probe is t"kLC, the resistance value R of this resistance element can be expressed by the following equation.

The layer resistance Ps is IKΩ, and the contact resistance & is 50.

When this value is used, the resistance value is approximately 20.005 R, which gives a negligible value for the contact resistance (Lc). Now, suppose that the width of the resistance element inside the circuit becomes narrower by 0.5 μm due to manufacturing variations, and the contact resistance of the resistance element inside the next 9 circuits becomes lOΩ.
,,2z2 becomes Ω, but the impurity region width W1 of the monitoring resistor element is similarly narrowed by 0.5 μm.

Therefore, there is a difference in the resistance value of the resistance element for monitoring due to the difference between the resistance element inside the circuit and the contact resistance, but as mentioned above, the proportion of the contact resistance in the resistance value of the entire resistance element is small; This means that the resistance value is almost the same as the resistance value of the resistance element inside the circuit.

The second factor is a plan view of the monitoring resistance element used in the second embodiment of the present invention. Impurity region 21 and opening 2
2.23 is made in the same manner as in the first embodiment. The difference between this embodiment and the first embodiment is that the impurity region @
W2 is 50μ wider than the impurity region width W1 in Figure 8J1
Meri in that m.

The impurity region length L2 and the size of the opening 22.23 are:
Same as the first example, 100μm and 40μm×40
It is μm. In this embodiment, the impurity region width W2 and the impurity region length are 1.2"k, and the change in resistance VL value of the resistor element due to manufacturing variations is negligible11. Therefore, the layer resistance of the impurity region 21 is relatively It is possible to accurately find φ.Now, the I'll resistance PS and the contact resistance C of the impurity loading 21 are respectively IKΩA as in the first disaster example.
and 5Ω, then according to the formula for calculating the resistance value mentioned above,
The resistance value of the resistance element is approximately 2XQ, and the impurity region width W2
Even if α5μm becomes narrower due to manufacturing variations, 几=
z02 becomes Ω, and the resistance value Kl-) of the monitoring resistor element is stable regardless of manufacturing variations in the impurity region width W2, and from this, the impurity region 210 layer resistance Ps can be determined. In the circuit, there are resistive elements with a plurality of resistance values, and it is impossible to determine the resistance value for each of them according to the first embodiment. Since it is necessary to determine the layer resistance, it is effective to measure the layer resistance using a non-example.

〔Effect of the invention〕

As explained above, monolithic integration (b) of the present invention will be explained as follows.
w & stile, the resistance of the resistance element inside the common substrate 1 before the deployment process [by having all the measurable monitor resistance elements on the common substrate, during the wiring process.

Wait for the resistance value of the desired resistance element based on the resistance value measured by this monitoring resistance element. Select the next common base and perform the wiring process on t. The resistance of the resistance element inside the circuit. The effect is that products whose values fall within the tolerance range inevitably determined by customer requirements can be manufactured with high yield. In addition, although the above explanations have been made regarding a resistance element formed in an impurity region within an epitaxial island, the same effect can be obtained even if the present invention is applied to a resistivity element formed on an insulating film made of polycrystalline silicon or the like. can get.

[Brief explanation of the drawing]

FIG. 1 is a plan view of a monitoring resistance element used in a first embodiment of the present invention. FIG. 2 is a plan view of a monitoring resistance element used in a second embodiment of the present invention. 11.21... Impurity region, 12, 13, 22°23
...Opening portion, Wl, W2...Impurity region width, Ll
. L2... Impurity region length

Claims (1)

[Claims] In a method for manufacturing a monolithic integrated circuit using a gate array type master slice method in which a desired logic function can be configured by selecting a wiring connection form, a semiconductor substrate on which element formation has been completed is selectively formed on the main surface of the semiconductor substrate. an impurity region having a conductivity type opposite to that of the semiconductor substrate, the insulating film on the impurity region has at least two openings for probe measurement, and the resistance value of the impurity region between the openings. A method for manufacturing a monolithic integrated circuit, characterized in that a wiring process is performed after measuring.