JPS63140709U - - Google Patents
Info
- Publication number
- JPS63140709U JPS63140709U JP1987031951U JP3195187U JPS63140709U JP S63140709 U JPS63140709 U JP S63140709U JP 1987031951 U JP1987031951 U JP 1987031951U JP 3195187 U JP3195187 U JP 3195187U JP S63140709 U JPS63140709 U JP S63140709U
- Authority
- JP
- Japan
- Prior art keywords
- generation circuit
- pulse generation
- delayed
- emitter
- inverter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003111 delayed effect Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 1
Landscapes
- Pulse Circuits (AREA)
Description
第１図は本考案による一実施例を示す回路図、
第２図は実施例の動作を説明するためのタイミン
グチヤート、第３図は実施例における復調カーブ
を示す特性図、第４図は本考案が適用される復調
器の構成図、第５図は第４図に示す復調器の動作
を説明するための波形図、第６図は従来例を示す
回路図、第７図は従来例の動作を説明するための
タイミングチヤート、第８図は従来例における復
調カーブを示す特性図である。
Ｑ１，Ｑ２，Ｑ３，Ｑ４，Ｑ７，Ｑ８……トラ
ンジスタ、Ｃ０……コンデンサ。
FIG. 1 is a circuit diagram showing an embodiment of the present invention;
Fig. 2 is a timing chart for explaining the operation of the embodiment, Fig. 3 is a characteristic diagram showing the demodulation curve in the embodiment, Fig. 4 is a configuration diagram of a demodulator to which the present invention is applied, and Fig. 5 is Figure 4 is a waveform diagram for explaining the operation of the demodulator, Figure 6 is a circuit diagram for the conventional example, Figure 7 is a timing chart for explaining the operation of the conventional example, and Figure 8 is the conventional example. FIG. 2 is a characteristic diagram showing a demodulation curve in FIG. Q 1 , Q 2 , Q 3 , Q 4 , Q 7 , Q 8 ... transistor, C 0 ... capacitor.
Claims (1)
で構成された遅延パルス発生回路において、設定
遅延時間よりも短い周期の入力信号に対しては、
インバータとして動作するようにしたことを特徴
とする遅延パルス発生回路。 In a delayed pulse generation circuit composed of an emitter-coupled delayed multivibrator, for an input signal with a period shorter than the set delay time,
A delay pulse generation circuit characterized in that it operates as an inverter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987031951U JPS63140709U (en) | 1987-03-06 | 1987-03-06 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987031951U JPS63140709U (en) | 1987-03-06 | 1987-03-06 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63140709U true JPS63140709U (en) | 1988-09-16 |
Family
ID=30838164
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987031951U Pending JPS63140709U (en) | 1987-03-06 | 1987-03-06 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63140709U (en) |
-
1987
- 1987-03-06 JP JP1987031951U patent/JPS63140709U/ja active Pending
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