JPS63140708U - - Google Patents

Info

Publication number
JPS63140708U
JPS63140708U JP3239587U JP3239587U JPS63140708U JP S63140708 U JPS63140708 U JP S63140708U JP 3239587 U JP3239587 U JP 3239587U JP 3239587 U JP3239587 U JP 3239587U JP S63140708 U JPS63140708 U JP S63140708U
Authority
JP
Japan
Prior art keywords
diagram
detection circuit
circuit
detection
output end
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3239587U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP3239587U priority Critical patent/JPS63140708U/ja
Publication of JPS63140708U publication Critical patent/JPS63140708U/ja
Pending legal-status Critical Current

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  • Measurement Of Velocity Or Position Using Acoustic Or Ultrasonic Waves (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例の回路図、第2図は
JFETのドレイン・ソース間の電圧電流特性の
図、第3図は平均値検波回路の原理図、第4図は
包絡線検波回路の原理図、第5図は包絡線検波と
平均値検波の効率曲線図、第6図は本考案の他の
実施例の回路の説明図で、イ図はその回路図、ロ
図、ハ図は検波の状況を示す図、第7図はバイポ
ーラ対数増幅器の特性曲線図である。 1……高周波トランス、2A,2B,10……
ダイオード、3……JFET、4,11……抵抗
、5,12……コンデンサ、6……時定数回路、
7……低域フイルタ。
Fig. 1 is a circuit diagram of an embodiment of the present invention, Fig. 2 is a diagram of voltage-current characteristics between the drain and source of a JFET, Fig. 3 is a principle diagram of an average value detection circuit, and Fig. 4 is an envelope detection circuit. Figure 5 is a diagram of the principle of the circuit, Figure 5 is an efficiency curve diagram of envelope detection and average value detection, Figure 6 is an explanatory diagram of a circuit of another embodiment of the present invention, Figure A is the circuit diagram, Figure 5 is the circuit diagram, The figure shows the detection situation, and FIG. 7 is a characteristic curve diagram of the bipolar logarithmic amplifier. 1...High frequency transformer, 2A, 2B, 10...
Diode, 3... JFET, 4, 11... Resistor, 5, 12... Capacitor, 6... Time constant circuit,
7...Low frequency filter.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ダイナミツクレンジの広い受信エコー信号を対
数圧縮増幅したのち検波する検波回路において、
検波手段の出力端に接続した定電流回路と、平滑
用コンデンサとを具備したことを特徴とする検波
回路。
In a detection circuit that logarithmically compresses and amplifies received echo signals with a wide dynamic range,
A detection circuit characterized by comprising a constant current circuit connected to an output end of a detection means and a smoothing capacitor.
JP3239587U 1987-03-05 1987-03-05 Pending JPS63140708U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3239587U JPS63140708U (en) 1987-03-05 1987-03-05

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3239587U JPS63140708U (en) 1987-03-05 1987-03-05

Publications (1)

Publication Number Publication Date
JPS63140708U true JPS63140708U (en) 1988-09-16

Family

ID=30839031

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3239587U Pending JPS63140708U (en) 1987-03-05 1987-03-05

Country Status (1)

Country Link
JP (1) JPS63140708U (en)

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