JPS63140379A - Parallel-picture processor - Google Patents

Abstract

PURPOSE:To obtain a parallel-picture processing processor having an architecture suitable for an LSI and in which a high speed processing can be attained by dividing a local parallel-picture processor into modules having the small number of input and output ports and a regular array. CONSTITUTION:The picture information of the picture memory 3 of a picture processing system is processed in the parallel-picture processing processor 2, the processed result is stored in a memory 3 or applied to a management proces sor 1 for controlling the entirety of the system. This processor 2 is constituted by combining the four modules of the basic modules 10A-10D of the picture processing processor having a processor element 12. Picture data to be processed in the picture data input port 24 of the modules 10A-10D is fetched and processed by an input picture shift register 11, the element 12, a partial sum arithmetic circuit 13 and a partial sum accumulation arithmetic circuit 14. The result processed in the respective modules 10A-10D is outputted from the picture data output port 25 and the LSI of the processor 2 is easily carried out.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a parallel image processing processor that performs local neighborhood image processing such as spatial product-sum operations, and particularly to a parallel image processing processor having an architecture suitable for LSI implementation.

Image processing processors process image data in parallel at high speeds, as developed in the Ministry of International Trade and Industry's large-scale project "Pattern Information Processing System" (a collection of research and development results was published in October 1980). There are many things that we are trying to change.

Since image data has a two-dimensional spread, it is difficult to process all image data in parallel. However, since there are many calculations between neighboring image data, such as spatial product-sum calculations that realize noise removal and contour extraction functions, for example, it is difficult to process local data in m rows by n columns of an image in parallel. many.

Such local parallel image processing is comprehensively explained in the above-mentioned literature or in Masatsugu Kido - Trends in Image Processing Hardware; Information Processing Computer Vision Study Group Material 8-6 (September 1980). There are no LSI versions other than the CCD analog processing type. There are difficulties in converting a processor with a conventional architecture into an LSI as it is in terms of: 1) the degree of integration, and 2) the number of pins.

An object of the present invention is to provide a parallel image processing processor that has an architecture suitable for LSI implementation and is capable of high-speed processing.

A feature of the present invention is that a parallel image processing processor that takes in image data from an image data source and performs locally parallel image data processing includes an image data input port and a plurality of processors that perform image processing operations based on the input image. a plurality of first arithmetic circuits that add the arithmetic results of the respective processor elements and the arithmetic results of the preceding processor element; and an arithmetic result data input port that inputs the arithmetic result data of the preceding basic module. a second arithmetic circuit that adds the arithmetic result data to the arithmetic result of the first arithmetic circuit in the final stage; and an arithmetic result data output port that outputs the arithmetic result data of the second arithmetic circuit. The parallel image processing processor includes a plurality of basic image processing processor modules arranged in parallel.

Hereinafter, the present invention will be explained using illustrative embodiments. still,
1 to 8 and FIGS. 11 and 12 are explanatory diagrams of recently considered parallel image processing techniques, and FIGS. 9 and 10 show an embodiment of the present invention.

FIG. 1 shows the configuration of a typical image processing system, which includes an industrial television camera 5 as an image input device, an image memory 3 as an image storage device, and a CRT monitor 4 for displaying the contents thereof. The image information in the image memory 3 is processed by the image processor 2, and the results are also stored in the image memory 3 or provided to the management processor 1 which controls the entire system.

A typical image processing function is spatial product-sum operation. As shown in FIG. 2, for example, a predetermined load W1'1~
W44 is multiplied and the sum is calculated.

This results in noise removal Contour enhancement Image processing such as

For example, as an image processing processor that processes 4×4 pixel local image data, a 4×4 pixel image processor as shown in FIG.
A parallel image processing processor (referred to as type I) that combines four image processing processor basic modules 10 each having 12 processor elements (PE#1 to #4).
2-■. One column of local image data (f14 to f44 in FIG. 3) is given in parallel from the image memory 3, and the calculation result (g in FIG. 3) is stored in the image memory 3.

The basic module 10 has an image data input port 24 that takes in image data of a row to be processed, and a calculation result data output port 35 that outputs internal processing results. image data f
When L4 is input, 1 is passed through the shift register 11.
Adjacent pixel f for each pixel 13. fi2. f tt
are also input to the corresponding PEs 84-1. The pixel f1t is
The image data is output from the image data output port 25 in case the size of the spatial product-sum operation is expanded to 4×4 or more. P.E.
12 is given the image data f to be processed from the shift register 11 and the load data W from the load storage memory 15, and multiplication by 1 is executed. This result is 4 PE12
A partial sum is calculated by the arithmetic circuit 13 which adds the results. The partial sums input from the calculation result input port 30 are accumulated one after another by the calculation circuit 14, and the partial sums input from the calculation result input port 30 are accumulated one after another by the calculation circuit 14.
5 to the next basic module 10.

In this way, by stacking the basic modules 10 in four stages, the final basic module 1.0D is output.

This time chart is shown in FIG. The above-mentioned operation is executed within the basic clock time Δt1 and the result g is output,
At the next Δt1, the result g for the input image of 4×4 picture elements shifted by one pixel is output. Therefore, all 4×4 images for image data that are input one after another
The spatial product-sum calculation results of the picture elements are output one after another.

The embodiment shown in FIG. 5 shows a configuration in which the basic clock time Δt1 of the type 1 image processing processor 2-I of the previous embodiment is shortened by pipeline processing. This is called a Type I pipeline version parallel image processing processor 2-IP. That is, in type ■, the basic clock time Δt1 is ■ Input processing of image data L and a to shift register 1 ■ Product-sum load W52 by processor element 12,
Multiplying process by image f+,a ■ Partial sum processing by arithmetic circuit 13 ■ It was necessary that the processing time of all partial sum accumulation processes by arithmetic circuit 14 be longer than the sum.

On the other hand, for example, as in the example in Figure 5, ■, ■, ■
By interposing the pipeline register 6 between and ■, and between ■ and ■, the basic clock time Δt2 can be reduced to ■
The maximum processing time of ~■ (not the sum of all)
It is possible to make it as small as possible. This time chart is shown in FIG.

Processing ■ is executed at time 1, ■ at time 2, ■ at time 3, and ■ at time 4. At time 2, the next input image is processed ■.

3, 4, and 5 are executed, and the processing speed can be improved by operating each component one after another in a pipeline manner.

The embodiment of FIG. 7 is based on the parallel image processing processor 2-
This shows a configuration in which the IP basic clock Δt2 can be further shortened, and is called a type (2) pipeline-skew version parallel image processing processor 2-IPS. Fifth
The basic clock time Δt2 in the IP type shown in the figure is the processing ■
There is a strong possibility that it is constrained by the partial sum accumulation time of . This is because when the basic module 10 has n stages, Δt2 requires n times the sum of the processing time in the arithmetic circuit 14 and the input/output time of the arithmetic result 30.35. In particular, when the basic module 10 is implemented as an LSI, the input/output delay time cannot be ignored. For this reason, a pipeline register 16 is further added to the type IP shown in FIG. 5 in the partial sum accumulation path, so that calculations between basic modules l0A-D are also pipelined, and the above-mentioned Δt 2' The time regulation is set to 1/n. In the IPS type shown in FIG. 7, as shown in the time chart of FIG. 8, the partial sums of the basic modules 10A-D are calculated at the same time 3, and the timings in the cumulative part do not match. I in Figure 7
In the PS, the variable stage skew correction shift register 17 for this timing adjustment is connected to the image data input port 2.
It is installed immediately after 4. Each basic module IOA~D
Since the number of pipeline stages in the cumulative path is 1, the number of stages of the variable stage skew correction shift register 17 is the basic module IOA...0 stage B...
...1st step C...2nd step D...3rd step. In this way, the mismatch (... part) in the time chart of FIG. 8 is corrected, and the continuous Δt
Pipeline operation can be completed in 3 hours.

As can be easily seen, the timing mismatch is similarly resolved even if the skew register 17 is installed immediately after the arithmetic circuit 13 that calculates the partial sum, or even if it is installed immediately before or after each PE 12. .

FIG. 9 shows an embodiment of a parallel image processing processor according to the present invention. In the configuration of type (2) described above, image data is input to each PE 12 #1 through the shift register 11.
Picture elements adjacent to 4 were distributed. On the other hand, in this embodiment, the input image data is commonly given to each PE 12#1-4, and the multiplication result is sent to the arithmetic circuit 18. The partial sum Σ1 is accumulated through the register 19 and output. This operation will be explained with reference to the time chart of FIG.

At time 1, the image f1t is input from the image data input port 20, and the product f11*W11 with the load Wll read out from the load storage memory 15 at PEj2#1 is stored in register 1.
9 #2 is set.

Image data f12 is input at time 2, and P E 12'
In #2, the product fL2*W12 with the load W12 is taken, and the sum fxz of this and the value f1z*wz of register 19#2
*w1t+f12*W12 is taken by the arithmetic circuit 18 and set in the register 19#3.

Image data f1g is input at time 3, and the product f ss * wta with the load Wi11 is taken at PE 12 #3, and this and the value of register 19 #3 f ll'l wit+ f
Sum of xz*W12 f engineering 1* wtt+ f 12
*W12+f 1sk wta is taken by the arithmetic circuit 18 and set in the register 19#4.

Image data fza is input at time 4, and the product f14*W14 with the load W14 is taken at PE12#4, and this and the value of register 19#4 f11*W11+f i2
*W 12+ f 13 'k Sum of W 13 ΣL=
f 11 * W IL+ ~+ f 14 * W
14 is taken by the arithmetic circuit 18. This partial sum Σ is accumulated in the arithmetic circuit 14 of each basic module l0A-D, and is output from the final stage.

Thereafter, the spatial product-sum calculation result g is output at intervals of each basic clock time Δt4.

Similar to type I, types P and IIPS can be considered for this type II parallel image processing processor 2-n.
It is possible to reduce the basic clock time Δt4. Since these can be easily inferred, they are omitted here.

FIG. 11 shows another embodiment with a further different processing form.

Add product-sum load (memory) 15 independently to each PE 12 up to the above.
In the configuration shown in Figure 11, the total PE1
This is a system in which a sum-of-products load (memory) 15 is given to the two in common, and is called a type (2) parallel image processing processor 2-m. This operation will be explained with reference to the time chart of FIG.

First, at time 1, the image f has already been input from the image data input port 20.
Assume that 14 is input. At this time, flz and
fiz, fza, fz4 are given. Then, the load Wli is read out from the load storage memory 15 and multiplied by each input image. In the arithmetic circuit 20,
The value held at the beginning of time 1 is cleared to 110'', and the products of the aforementioned f14 and Wll are held respectively.

At time 2, image fz5 is input, and PE12 #1 to #4
are given fz2 to fz5, respectively, and the next load wt2
The product is taken. Thereafter, the arithmetic circuit 20 performs an accumulation process with the previous value. For example, in #1, f 11 * w
tz + f 12 * wtx, fx21'w in #2
xt+ft3*wx2 is retained as the result.

The same process is executed at times 3 and 4, and the arithmetic circuit 20#
For 1 to #4, #1:ΣL=”f 11” wzt+f 12's
W12+ f x3 * W18+ f 14 * w
za#2・Σxx= f 12* W11+ f 1g
"w engineering 2+ f 14" wtll+f ls*wt
a#3: ΣKeis= f 13” wtt+ f 1+*
w1z+ f 15J wt3+ f 18*W14
#4: Σj4== f 14 + wtt ten f t5 * W
12+f 18 cells Wll+f 17*w14 and their respective first partial sums are obtained, which are set in the shift register 21 at the end of time Δ.

At times 5 to 8, the shift registers 21 of each basic module 10A-D transfer data from Σ) to Σ11. Σ)2 to Σ12.
Σ)3 to Σ18. Σ)4 to Σ14 are sequentially accumulated by the arithmetic circuit 14, and the results g11 to g14 are output.

At the same time, in PEAL, image data fx5 to ftg, P
f16~fts in E#2, f1r~fz in PE#3
o, PE#4 has f 18 to Lzx at times 1 to 4
Processing similar to is executed, and partial sum Σ15. Σ′X6゜Σ
1F, Σ18 is calculated, and these are accumulated at times 9 to 12 to obtain results g1R to g1g. In this way, spatial product-sum calculation results are continuously output.

Similar to the type (2), types mP and (2) PS can be considered for the parallel image processing processor 2-H of the type (2), and it is possible to reduce the basic clock time Δt5.

Now, in the embodiments of Types 1 to 2 described above, calculations between the basic modules 10 are performed by connecting partial sum calculation circuits 14 in series, and this circuit 14 is also included in the basic module. However, if the number of pins becomes an issue for LSI implementation, for example, only the dotted line in Figure 3 should be used as the basic module.
Inter-module operations can also be performed externally in parallel.

According to the present invention, since a locally parallel image processor can be divided into modules with a small number of input/output ports and a regular arrangement, an architecture suitable for LSI implementation can be achieved.

[Brief explanation of the drawing]

Figure 1 is a diagram showing the configuration of an image processing system, Figure 2 is a diagram explaining an example of local parallel processing, and Figures 3 and 5゜7.9.11
The figure is a block diagram showing the configuration of the parallel image processing processor of the present invention, and Figures 4.6, 8, 10 and 12 are diagrams showing time charts of the parallel image processing processor. 2...Parallel image processing processor, 3...Image memory, 10...Image processing processor basic module, 11
... Input image shift register, 12... Processor element, 13... Partial sum calculation circuit, 14... Partial sum accumulation calculation circuit, 15... Load storage memory, 16.
... Pipeline register, 17... (variable number of stages) skew correction shift register, 18... Propagation/accumulation arithmetic circuit, 19... Propagation register, 20... Accumulation arithmetic circuit, 21... Partial sum Output shift register, 24...
Image data input port, 25... Image data output port, 30... Calculation result data input port, 35...
Operation result data output port.

Claims (1)

[Claims] 1. In a parallel image processing processor that takes in image data from an image data source and performs local parallel image data processing, an image data input port and a plurality of processor elements that perform image processing operations based on the input image; a plurality of first arithmetic circuits that add the arithmetic results of the respective processor elements and the arithmetic results of the preceding processor element; an arithmetic result data input port that inputs the arithmetic result data of the preceding basic module; and the arithmetic result data and a second arithmetic circuit that adds the arithmetic results of the first arithmetic circuit in the final stage, and an arithmetic result data output port that outputs the arithmetic result data of the second arithmetic circuit. of,
A parallel image processing processor characterized by having multiple sets arranged in parallel.