JPS63139576U - - Google Patents
Info
- Publication number
- JPS63139576U JPS63139576U JP3212487U JP3212487U JPS63139576U JP S63139576 U JPS63139576 U JP S63139576U JP 3212487 U JP3212487 U JP 3212487U JP 3212487 U JP3212487 U JP 3212487U JP S63139576 U JPS63139576 U JP S63139576U
- Authority
- JP
- Japan
- Prior art keywords
- section
- signal
- radio waves
- stc
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005540 biological transmission Effects 0.000 claims description 3
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 2
- 238000006243 chemical reaction Methods 0.000 claims 1
- 238000001514 detection method Methods 0.000 claims 1
- 238000000034 method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
- 230000010355 oscillation Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
Landscapes
- Radar Systems Or Details Thereof (AREA)
Description
第1図は考案の実施例を示す構成図、第2図は
この考案のSTC(Sensivity Tim
e Control)制御回路の詳細な構成図、
第3図はこの考案によるSTC制御のタイムチヤ
ート、第4図は従来のレーダー装置の構成図、第
5図は従来のレーダー装置のSTC制御の動作説
明図である。
図において1は送受信共用のアンテナ、2は送
信機部、3は送受切換部、4は周波数ミキサ、5
はローカル信号発生部、6は受信機部、7は信号
処理部、8は表示部、9はSTC制御部、10は
A/Dコンバータ回路、11A〜11Dはアンド
回路、12A〜12Dはレジスタ回路、13A〜
13Dは加算回路、14A〜14Dはレジスタ回
路、15A,15Bは乗算回路、16は減算回路
、17は符号判定回路、18は絶対値回路、19
A〜19Cは1スキヤン記憶回路、20はスイツ
チ回路、21は制御回路、22A,22Bはカウ
ンタ回路、23は発振回路、24は分周回路、2
5は選択回路、26はアツプダウン制御付カウン
タ回路、27は加算回路、28はD/Aコンバー
タ回路、29は受信ビデオ信号、30は一定のレ
ベルを越えたビデオ・ゲート、31は前方ゲート
、32は後方ゲート、33は指定領域の前方ゲー
ト内のビデオ振幅の和、34は指定領域の後方ゲ
ート内のビデオ振幅の和、35は前方ゲート内の
クラツタを計数するクロツク、36は後方ゲート
内のクラツタを計数するクロツク、37は指定領
域の前方ゲート内のクラツタを計数したクロツク
の和、38は指定領域の後方ゲート内のクラツタ
を計数したクロツクの和、39は読み出しパルス
、40は書き込みパルス、41は重みを付与され
たSTC制御信号、42は送信パルス、43はS
TC制御を受けた処理ビデオ、44は従来のレー
ダ装置のSTC制御信号、45は従来のレーダ装
置のSTC制御を受けた処理ビデオである。なお
、図中同一あるいは相当部分には同一符号を付し
て示してある。
Fig. 1 is a block diagram showing an embodiment of the invention, and Fig. 2 is an STC (Sensitivity Timing) diagram of this invention.
e Control) Detailed configuration diagram of the control circuit,
FIG. 3 is a time chart of STC control according to this invention, FIG. 4 is a block diagram of a conventional radar device, and FIG. 5 is an explanatory diagram of the operation of STC control of a conventional radar device. In the figure, 1 is an antenna for both transmitting and receiving, 2 is a transmitter section, 3 is a transmitting/receiving switching section, 4 is a frequency mixer, and 5 is a transmitting/receiving antenna.
is a local signal generation section, 6 is a receiver section, 7 is a signal processing section, 8 is a display section, 9 is an STC control section, 10 is an A/D converter circuit, 11A to 11D are AND circuits, and 12A to 12D are register circuits. , 13A~
13D is an addition circuit, 14A to 14D are register circuits, 15A and 15B are multiplication circuits, 16 is a subtraction circuit, 17 is a sign determination circuit, 18 is an absolute value circuit, 19
A to 19C are 1 scan memory circuits, 20 is a switch circuit, 21 is a control circuit, 22A and 22B are counter circuits, 23 is an oscillation circuit, 24 is a frequency dividing circuit, 2
5 is a selection circuit, 26 is a counter circuit with up-down control, 27 is an adder circuit, 28 is a D/A converter circuit, 29 is a received video signal, 30 is a video gate exceeding a certain level, 31 is a front gate, 32 is the rear gate, 33 is the sum of the video amplitudes in the front gate of the specified area, 34 is the sum of the video amplitudes in the rear gate of the specified area, 35 is a clock for counting clutter in the front gate, and 36 is the sum of the video amplitudes in the rear gate of the specified area. 37 is the sum of the clocks that count the clutter in the front gate of the specified area; 38 is the sum of the clocks that counts the clutter in the rear gate of the specified area; 39 is the read pulse; 40 is the write pulse; 41 is a weighted STC control signal, 42 is a transmission pulse, and 43 is S
44 is a processed video subjected to TC control, 44 is an STC control signal of a conventional radar device, and 45 is a processed video subjected to STC control of a conventional radar device. It should be noted that the same or corresponding parts in the drawings are designated by the same reference numerals.
Claims (1)
置において送信電波を外部に放射し、目標からの
反射波を受信する送受信共用のアンテナと、高周
波電力パルスを作成する送信機部と、上記送信機
部からの電波の送信と上記アンテナからの受信電
波を受信するための切り替えを行う送受切替部と
、上記送受切替部から入力される受信電波を中間
周波数に周波数変換を行う周波数ミキサと、上記
受信電波を中間周波数に変換するためのローカル
信号を作成するローカル信号発生部と、上記周波
数ミキサ出力を増幅した後ビデオ信号として出力
する受信機部と、上記受信機部の出力を受けて距
離追尾や角度追尾及び検出の処理や各種トリガを
作成する信号処理部と、受信機部の出力のビデオ
信号を入力とし、ビデオ信号に含まれるクラツタ
の広がりと振幅の積に依る傾きをもつSTC(S
ensivity Time Control)
信号を出力するSTC制御部と、信号処理部の出
力を受けてこれを表示する表示部から構成されて
いることを特徴とするレーダー装置。 A radar device having a target search or tracking function includes a transmitting and receiving antenna that emits transmitted radio waves to the outside and receives reflected waves from the target, a transmitter unit that creates high-frequency power pulses, and radio waves from the transmitter unit. a transmission/reception switching unit that performs switching between transmitting and receiving the received radio waves from the antenna; a frequency mixer that converts the received radio waves input from the transmission/reception switching unit into an intermediate frequency; a local signal generation section that creates a local signal for conversion into a local signal, a receiver section that amplifies the frequency mixer output and outputs it as a video signal, and a receiver section that receives the output of the receiver section and performs distance tracking, angle tracking, and detection. A signal processing section that processes the clutter and creates various triggers, and a video signal output from the receiver section are input, and the STC (STC) has a slope depending on the product of the spread and amplitude of clutter included in the video signal.
Safety Time Control)
A radar device comprising an STC control section that outputs a signal, and a display section that receives and displays the output of the signal processing section.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3212487U JPS63139576U (en) | 1987-03-05 | 1987-03-05 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3212487U JPS63139576U (en) | 1987-03-05 | 1987-03-05 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63139576U true JPS63139576U (en) | 1988-09-14 |
Family
ID=30838497
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3212487U Pending JPS63139576U (en) | 1987-03-05 | 1987-03-05 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63139576U (en) |
-
1987
- 1987-03-05 JP JP3212487U patent/JPS63139576U/ja active Pending