JPH03114076U - - Google Patents

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Publication number
JPH03114076U
JPH03114076U JP2351890U JP2351890U JPH03114076U JP H03114076 U JPH03114076 U JP H03114076U JP 2351890 U JP2351890 U JP 2351890U JP 2351890 U JP2351890 U JP 2351890U JP H03114076 U JPH03114076 U JP H03114076U
Authority
JP
Japan
Prior art keywords
section
signal
receives
outputs
unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2351890U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP2351890U priority Critical patent/JPH03114076U/ja
Publication of JPH03114076U publication Critical patent/JPH03114076U/ja
Pending legal-status Critical Current

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  • Radar Systems Or Details Thereof (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの考案の実施例を示す構成図、第2
図はこの考案の受信機部の詳細な構成図、第3図
はこの考案のデフルータ回路と切り替え回路の構
成図、第4図Aと第4図Bはこの考案の2つの使
用例のタイムチヤート、第5図は従来のレーダ装
置の構成図である。 図に於て1……フエーズドアレイアンテナ、2
……サーキユレータ、3……送信機部、4……S
TAL部、5……L/O部、6……受信機部、7
……信号処理部、8……目標検出部、9……追尾
処理部、10……表示部、11……計算機部、1
2……BSC部、13……デフルータ部、14…
…切り替え回路部、15……ゲート回路部、16
……可変スレツシヨルド、17……受信機入力信
号、18……MIX、19……FIL、20,2
4……IFAMP、21……DIV、22,34
……DLY、23……GAT、25,31……D
ET、26……VIDAMP、27……DIV出
力信号或いはデフルータ入力信号、28……受信
機部内のゲート回路入力信号、29……受信機部
出力信号、30,36……DRV、32……A/
D、33……比較回路、35……不一致回路、3
7〜41……切り替えスイツチ、42……切り替
え回路出力或いはゲート回路入力、43……計算
機からの切り替え回路制御信号、44……A/D
出力信号、45……スレツシヨルド信号、46…
…比較回路出力信号、47……不一致回路出力信
号、48……送信パルスタイミング波形、49…
…有効受信範囲を示すタイミング波形、50……
出力信号波形、S1……非同期な妨害波、S2…
…目標信号、S3……セカンドエコーである。な
お、図中同一或いは相当部分には同一符号を付し
て示してある。
Figure 1 is a configuration diagram showing an embodiment of this invention, Figure 2
Figure 3 is a detailed configuration diagram of the receiver section of this invention, Figure 3 is a configuration diagram of the defruer circuit and switching circuit of this invention, and Figures 4A and 4B are time charts of two usage examples of this invention. , FIG. 5 is a block diagram of a conventional radar device. In the figure 1... Phased array antenna, 2
...Circulator, 3...Transmitter section, 4...S
TAL section, 5... L/O section, 6... Receiver section, 7
... Signal processing section, 8 ... Target detection section, 9 ... Tracking processing section, 10 ... Display section, 11 ... Computer section, 1
2... BSC section, 13... Defruter section, 14...
...Switching circuit section, 15...Gate circuit section, 16
...Variable threshold, 17...Receiver input signal, 18...MIX, 19...FIL, 20,2
4...IFAMP, 21...DIV, 22,34
...DLY, 23...GAT, 25, 31...D
ET, 26...VIDAMP, 27...DIV output signal or defrouter input signal, 28...gate circuit input signal in the receiver section, 29...receiver section output signal, 30, 36...DRV, 32...A /
D, 33... Comparison circuit, 35... Mismatch circuit, 3
7-41...Switching switch, 42...Switching circuit output or gate circuit input, 43...Switching circuit control signal from computer, 44...A/D
Output signal, 45...Threshold signal, 46...
... Comparison circuit output signal, 47 ... Mismatch circuit output signal, 48 ... Transmission pulse timing waveform, 49 ...
...Timing waveform indicating effective reception range, 50...
Output signal waveform, S1...Asynchronous interference wave, S2...
...Target signal, S3...Second echo. It should be noted that the same or equivalent parts in the figures are indicated by the same reference numerals.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] アンテナを固定したまま旋回及び俯仰方向に自
由にビーム走査することができ、さらに目標を捜
索或いは探知そして追尾する機能を有し、しかも
多目標についてそれを行うことができるフエイズ
ドアレイレーダ装置において、送信電波を外部に
放射し、目標から反射波を受信する送受信共用の
フエイズドアレイレーダアンテナと、送信と受信
のアイソレーシヨンを行うサーキユレータと、高
周波電力パルスを出力する送信機部と、安定した
周波数を出力する安定化発振器部と、上記安定化
発振器部からの信号を受けて後述の受信機で使用
するローカル信号を作り出すローカル信号発生部
と、上記アンテナからの入力を中間周波数信号に
変換した後、ビデオ信号として出力する受信機部
と、上記受信機部からのビデオ信号を受けて、ア
ナログ信号からデジタル信号へ変換するアナログ
ツウデジタルコンバータを含み、移動目標表示機
能やパルスドツプラー機能及びパルス積分機能な
どを有する信号処理部と、上記信号処理部からの
信号を受けて目標検出を行う目標検出部と、上記
目標検出部からの信号を受けて目標追尾を行う追
尾処理部と、上記の各種処理ビデオを表示する表
示部と、上記信号処理部から表示部等のほとんど
の機能に連接されている計算機部と、上記アンテ
ナのビーム走査指令信号を出力するビームステア
リング部と、上記受信機部から分配された入力信
号のヒツト間相関処理を行うデフルータ回路部と
、上記デフルータ回路にて行うヒツト間相関処理
の基準レベルを変えることができる可変スレツシ
ヨルド部と、上記デフルータ回路部出力を受けて
、上記計算機部からの指令によりその出力信号や
ステータス信号を上記受信機部や後述のゲート回
路部へ出力する切り替え回路部と、上記切り替え
回路部からの信号を受けて上記目標検出部出力を
無効なものにするか有効なものとして上記追尾処
理部へ送出するかを決めるゲート回路部から構成
されていることを特徴とするフエイズドアレイレ
ーダ装置。
In a phased array radar device that can freely scan the beam in the turning and elevation directions with the antenna fixed, and has the function of searching, detecting and tracking targets, and can do this for multiple targets. , a phased array radar antenna for both transmission and reception that radiates transmission radio waves to the outside and receives reflected waves from the target, a circulator that isolates transmission and reception, and a transmitter section that outputs high-frequency power pulses; A stabilizing oscillator section that outputs a stable frequency; a local signal generating section that receives the signal from the stabilizing oscillator section and generates a local signal to be used in the receiver described later; and converts the input from the antenna into an intermediate frequency signal. It includes a receiver section that outputs the converted video signal as a video signal, and an analog-to-digital converter that receives the video signal from the receiver section and converts it from an analog signal to a digital signal, and has a moving target display function and a pulse Doppler function. and a signal processing section having a pulse integration function, a target detection section that receives a signal from the signal processing section and performs target detection, and a tracking processing section that receives a signal from the target detection section and performs target tracking. a display unit that displays the various processed videos described above; a computer unit that is connected to most of the functions from the signal processing unit to the display unit; a beam steering unit that outputs beam scanning command signals for the antenna; a defruter circuit section that performs inter-human correlation processing of the input signal distributed from the machine section; a variable threshold section that can change the reference level of the inter-human correlation processing performed in the defruter circuit; and a variable threshold section that receives the output of the defruter circuit section. and a switching circuit section that outputs the output signal and status signal to the receiver section and the gate circuit section described later according to a command from the computer section, and a switching circuit section that receives the signal from the switching circuit section and outputs the output signal of the target detection section. A phased array radar device comprising a gate circuit unit that determines whether to send the data to the tracking processing unit as an invalid item or a valid item to the tracking processing unit.
JP2351890U 1990-03-08 1990-03-08 Pending JPH03114076U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2351890U JPH03114076U (en) 1990-03-08 1990-03-08

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2351890U JPH03114076U (en) 1990-03-08 1990-03-08

Publications (1)

Publication Number Publication Date
JPH03114076U true JPH03114076U (en) 1991-11-22

Family

ID=31526502

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2351890U Pending JPH03114076U (en) 1990-03-08 1990-03-08

Country Status (1)

Country Link
JP (1) JPH03114076U (en)

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