JPS63138743A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63138743A JPS63138743A JP28693286A JP28693286A JPS63138743A JP S63138743 A JPS63138743 A JP S63138743A JP 28693286 A JP28693286 A JP 28693286A JP 28693286 A JP28693286 A JP 28693286A JP S63138743 A JPS63138743 A JP S63138743A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- section
- molding
- mold
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims 3
- 239000004065 semiconductor Substances 0.000 title claims 3
- 239000011347 resin Substances 0.000 claims abstract description 25
- 229920005989 resin Polymers 0.000 claims abstract description 25
- 238000000465 moulding Methods 0.000 claims abstract description 22
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims description 11
- 238000005538 encapsulation Methods 0.000 claims description 7
- 238000005452 bending Methods 0.000 abstract description 3
- 238000007789 sealing Methods 0.000 abstract 2
- 230000002040 relaxant effect Effects 0.000 abstract 1
- 235000014676 Phragmites communis Nutrition 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は表面実装用のＩＣパッケージ、特にＳＯＰ （
Ｓｍａｌｌ ０ｕｔｌｉｎｅ Ｐａｃｋａｇｅ）とＱＦ
Ｐ （Ｑｕａｄ Ｆｌａｔ Ｐａｃｋａｇｅ） Ｏ外形
構造に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to surface mounting IC packages, particularly SOP (
Small 0utline Package) and QF
P (Quad Flat Package) O Regarding the external structure.
従来、この種のＩＣパッケージは、上下の封入金型がほ
ぼ同一幅でつくられており、ボディの側面形状としては
ほば四角である。Conventionally, in this type of IC package, the upper and lower encapsulation molds are made to have approximately the same width, and the side surface shape of the body is approximately square.
またリード形状としてはボディからめる敢さで水平に引
き出し、クランク型に成型されていた。In addition, the lead shape was pulled out horizontally from the body and molded into a crank shape.
第６図は従来ＳＯＰの外鋭図で、（ａ）は平面図、（ｂ
）は正面図、（Ｃ）は側面図である。ＱＦＰも４方向に
リード線が出ている違いがあってもリード形状は同様で
ある。Figure 6 is an external view of the conventional SOP, (a) is a plan view, (b)
) is a front view, and (C) is a side view. QFPs also have the same lead shape, although there are lead wires protruding in four directions.
上述した従来のＳＯＰ 、ＱＦＰでは、リード線を引き
出し箇所でしか同定していないため、リード線１０が外
圧に対する強度面で難があった。In the conventional SOP and QFP described above, the lead wires are identified only at the point where they are drawn out, and therefore the lead wires 10 have a problem in terms of strength against external pressure.
運搬時とかプリント仮への装着時にリード線に外圧が加
えられると簡単にリード変形が失じるという欠点があっ
た。There is a drawback that the lead easily loses its deformation when external pressure is applied to the lead wire during transportation or attachment to a temporary print.
またリード線１０に下樹脂部１３に近接成形することも
考えられるが、このま１の状態で曲けると、下樹脂部１
３と上樹脂部６の接合部にリード曲げ応力が加わるため
、樹脂クラックを生じＩＣの耐湿特性の力比をまねくこ
とになり実現が困難である。It is also possible to mold the lead wire 10 close to the lower resin part 13, but if it is bent in this state, the lower resin part 13
Since lead bending stress is applied to the joint between 3 and the upper resin part 6, resin cracks occur and the force ratio of the moisture resistance characteristics of the IC is affected, making it difficult to realize.
本発明のＩＣパッケージは、リード線の変形防止を目的
とし、下樹脂部に突出部を設け、リード線をその突出部
に近接成形する。In the IC package of the present invention, a protrusion is provided in the lower resin part for the purpose of preventing deformation of the lead wire, and the lead wire is molded close to the protrusion.
次に、本発明についてＳＯＰの実施例を示し以下に説明
する。Next, an example of the SOP of the present invention will be shown and explained below.
第１図〜第５図は本発明の一実施例の側面からみた断面
図である。1 to 5 are cross-sectional views of an embodiment of the present invention viewed from the side.
第１図は封入金型、第２図と第３図は樹脂対人、第４図
はリード成形金型、第５図はリード成形の状態を示す。FIG. 1 shows the encapsulation mold, FIGS. 2 and 3 show the resin molding, FIG. 4 shows the lead molding mold, and FIG. 5 shows the lead molding state.
封入金型は上金型１と下金型２で構成しておシ、上金型
ｌに比べ下金型２の樹脂封入部分の幅を広くしておく、
ＩＣチップ４をマウントおよびポンディング処理された
リードフレーム３を下金型１と下金型２ではさんだ状態
で第２図で、これに樹脂を流し込み、封入金型を外し、
かつリードフレームを切断したものが第３図で、上樹脂
部６、下樹脂部７、成形前のリード線５を得る。The encapsulation mold consists of an upper mold 1 and a lower mold 2, and the width of the resin-filled part of the lower mold 2 is made wider than that of the upper mold 1.
As shown in FIG. 2, the lead frame 3 on which the IC chip 4 has been mounted and subjected to the bonding process is sandwiched between the lower mold 1 and the lower mold 2, resin is poured into this, the encapsulation mold is removed,
FIG. 3 shows a cut of the lead frame to obtain an upper resin part 6, a lower resin part 7, and a lead wire 5 before molding.
第４図はリード成形金型で、成形上型８と成形下型９と
成形時に上樹脂部６と下樹脂部７の接合部に加わる曲げ
応力を緩和させる支え金具１１と支える力を調整するバ
ネ１２によって構成する。FIG. 4 shows a lead molding die, which includes an upper molding mold 8, a lower molding mold 9, a supporting metal fitting 11 that relieves the bending stress applied to the joint between the upper resin part 6 and the lower resin part 7 during molding, and adjusts the supporting force. It is constituted by a spring 12.
リード成形は成形上盤８が降下させることによシ行われ
るのが、その際支え金具１１がリードの肩にあてられ、
徐々にバネ１３によって加圧される。The reed forming is performed by lowering the upper molding plate 8, and at this time, the support fitting 11 is placed on the shoulder of the reed.
It is gradually pressurized by the spring 13.
第５図はリード成形後を示す。FIG. 5 shows the lead after molding.
以上説明したように本発明は、下樹脂部に突出部を設け
、リード線をその突出部に近接成形することにより、リ
ード線が保羨され、リード変形の防止に効果がある。As explained above, the present invention provides a protrusion on the lower resin part and molds the lead wire close to the protrusion, thereby maintaining the lead wire and effectively preventing lead deformation.
第１図〜第５図は本発明の実施例を示す説明図で、第１
図は封入金型、第２図と第３図は樹脂封入、第４図はリ
ード成形金型、第５図はリード成形後のパッケージを示
す断面図である。
ｌ・・・・・・下金型、２・・・・・・下金型、３・・
・・・・リードフレーム、４・・・・・・チップ、５・
・・・・・成形前のリード線、６・・・、・、上樹脂部
、７・・・・・・下樹脂部、８・・・・・・成形下型、
９・・・・・・成形下型、ｌｏ・・・・・・成形後のリ
ード線、１１°°°°・・支え金具、１２・・・・・・
バネ。
嬉６図は従来ＳＯＰの外観図で、（匈は平面図、（切に
正面図、（Ｃ）は側面図である。
６・・・・・・上樹脂部、１３・・・・・・下樹脂部、
１０−°・・・・成形後のリード線。
と
第Ｇ 図Figures 1 to 5 are explanatory views showing embodiments of the present invention.
The figure shows an encapsulating mold, FIGS. 2 and 3 show resin encapsulation, FIG. 4 shows a lead molding mold, and FIG. 5 shows a sectional view of a package after lead molding. l...Lower mold, 2...Lower mold, 3...
...Lead frame, 4...Chip, 5.
... Lead wire before molding, 6 ..., ..., upper resin part, 7 ... lower resin part, 8 ... lower mold,
9...Molding lower mold, lo...Lead wire after molding, 11°°°°...Supporting metal fittings, 12...
Spring. Figure 6 is an external view of the conventional SOP, (the top is the plan view, (the front view is the front view, and (C) is the side view. 6... Upper resin part, 13... Lower resin part,
10-°・・・Lead wire after molding. and Figure G
Claims (1)
体装置の製造方法において、片方の封入金型の樹脂封入
部分の幅を広くすることによって突出部を設け、リード
線をその突出部に近接成形したことを特徴とする半導体
装置の製造方法。In a semiconductor device manufacturing method in which two encapsulation molds are combined and resin is encapsulated therein, a protrusion is provided by widening the resin-filled portion of one of the encapsulation molds, and a lead wire is attached to the protrusion. A method of manufacturing a semiconductor device characterized by close-proximity molding.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28693286A JPS63138743A (en) | 1986-12-01 | 1986-12-01 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28693286A JPS63138743A (en) | 1986-12-01 | 1986-12-01 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63138743A true JPS63138743A (en) | 1988-06-10 |
Family
ID=17710824
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28693286A Pending JPS63138743A (en) | 1986-12-01 | 1986-12-01 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63138743A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR950021459A (en) * | 1993-12-10 | 1995-07-26 | 가나이 쓰토무 | Package semiconductor device having a flange on the side and manufacturing method thereof |
-
1986
- 1986-12-01 JP JP28693286A patent/JPS63138743A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR950021459A (en) * | 1993-12-10 | 1995-07-26 | 가나이 쓰토무 | Package semiconductor device having a flange on the side and manufacturing method thereof |
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