JPS63138715U - - Google Patents
Info
- Publication number
- JPS63138715U JPS63138715U JP3200687U JP3200687U JPS63138715U JP S63138715 U JPS63138715 U JP S63138715U JP 3200687 U JP3200687 U JP 3200687U JP 3200687 U JP3200687 U JP 3200687U JP S63138715 U JPS63138715 U JP S63138715U
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- specified frequency
- resonator
- grounded
- rejection filter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010355 oscillation Effects 0.000 claims description 9
- 230000000903 blocking effect Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 6
Landscapes
- Inductance-Capacitance Distribution Constants And Capacitance-Resistance Oscillators (AREA)
Description
第１図は本考案の発振逓倍器の原理ブロツク図
、第２図は本考案の一実施例の発振逓倍器の回路
図、第３図は従来の発振逓倍器のブロツク図、第
４図は従来の発振逓倍器の回路図、第５図は規定
周波数における従来の発振逓倍器の等価回路図で
ある。
図において、１は３端子素子、２は共振器（ｆ
／２）、３は終端抵抗、４は発振回路、５は第１
の帯域阻止フイルタ（ＢＥＦ，ｆ／２）、６はＢ
ＥＦ（ｆ／２）、７は第２の帯域阻止フイルタ（
ｆ）、８は負荷、９はマイクロストリツプ線路、
１０，１１は誘電体共振器を示している。
Fig. 1 is a principle block diagram of the oscillation multiplier of the present invention, Fig. 2 is a circuit diagram of an oscillation multiplier according to an embodiment of the invention, Fig. 3 is a block diagram of a conventional oscillation multiplier, and Fig. 4 is a block diagram of the oscillation multiplier of the present invention. Circuit diagram of a conventional oscillation multiplier. FIG. 5 is an equivalent circuit diagram of a conventional oscillation multiplier at a specified frequency. In the figure, 1 is a three-terminal element, 2 is a resonator (f
/2), 3 is the terminal resistor, 4 is the oscillation circuit, 5 is the first
band rejection filter (BEF, f/2), 6 is B
EF (f/2), 7 is the second band rejection filter (
f), 8 is a load, 9 is a microstrip line,
10 and 11 indicate dielectric resonators.
Claims (1)
端子素子１の前記ドレイン端を接地し、また前記
ゲート端に規定周波数の二分の一の周波数に共振
する共振器２と終端抵抗３とを直列状に接続して
接地して発振回路４を形成するとともに、前記ソ
ース端に前記規定周波数の二分の一の周波数を阻
止する帯域阻止フイルタ５を備え、前記ソース端
から規定周波数を出力する発振逓倍器において、 前記ゲート端と前記共振器２との間に前記規定
周波数を阻止する帯域阻止フイルタ７を設けたこ
とを特徴とする発振逓倍器。[Claims for Utility Model Registration] The drain end of a terminal element 1 having a gate end, a source end, and a drain end is grounded, and a resonator 2 resonates at a frequency that is one-half of a specified frequency at the gate end. and a termination resistor 3 are connected in series and grounded to form an oscillation circuit 4, and the source end is provided with a band rejection filter 5 for blocking a frequency that is one-half of the specified frequency. An oscillation multiplier that outputs a specified frequency, characterized in that a band rejection filter 7 for blocking the specified frequency is provided between the gate end and the resonator 2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3200687U JPS63138715U (en) | 1987-03-04 | 1987-03-04 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3200687U JPS63138715U (en) | 1987-03-04 | 1987-03-04 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63138715U true JPS63138715U (en) | 1988-09-13 |
Family
ID=30838265
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3200687U Pending JPS63138715U (en) | 1987-03-04 | 1987-03-04 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63138715U (en) |
-
1987
- 1987-03-04 JP JP3200687U patent/JPS63138715U/ja active Pending
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