JPS63138471A - Logical arithmetic system for binary picture - Google Patents

Abstract

PURPOSE:To obtain at a time the arithmetic results of plural binary pictures by having reference to a conversion table based on the connecting information on two memory data stored in the same picture element positions of two variable density picture memories storing plural binary pictures respectively. CONSTITUTION:The reference is given to a conversion table 14 based on the connecting information on two memory data stored in the optional same picture element positions of 1st and 2nd variable density picture memories 12A-12C. Then the entry contents of the table 14 are taken out to obtain simultaneously plural binary picture logical arithmetic results. That is, the arithmetic result c0 of the binary logical arithmetic x0 obtained between binary pictures a0 and b0 stored in bit planes 12A0 and 12B0 of memories 12A and 12B is obtained by the memory 12C for all picture elements together with the arithmetic result c1 of the binary logical arithmetic x1 obtained between binary pictures a1 and b1 stored in bit planes 12A1 and 12B1 of memories 12A and 12B respectively.

Description

Detailed Description of the Invention [Objective of the Invention] (Industrial Field of Application) This invention provides a method for discriminating information between images at the same bit position with respect to a plurality of binary images respectively stored at the same pixel position of two grayscale image memories. This invention relates to a binary image logic operation method for performing binary logic operations.

(Prior Art) An image processing device that handles grayscale image data generally includes a number of grayscale image memories each consisting of a plurality of bit brains.

The bitplanes in this grayscale image memory are also used to store binary images.

Therefore, a plurality of binary images can be stored in one grayscale image memory. In such an image processing device, 2
A plurality of 2ft images each stored in one grayscale image memory.
Logical operations between i images are required.

There are cases. The conventional method of this logical operation will be explained below by taking an image processing apparatus equipped with grayscale image memories A, B, and C as an example.

Now, bit plane AO of grayscale image memory A.

Binary image aQ stored at the same pixel position of At.

al and bit plane BO of grayscale image memory B.

2 stored in the same pixel position as the above pixel position of Bl
It is assumed that binary logical operations xo and xi are performed between the value images bO and bl, and the results cQ and cl are stored in the same pixel position of the bit planes Co and CI of the grayscale image memory C. In this case, by bit-brain reading of the grayscale image memory (depending on which bit is specified), first read aO from AO of A and bO from BO of B, and perform a logical operation xO between aO and bo. , the first step of storing the result co in the CO of C is performed. When this first step is performed, from A1 to al
A second step is performed in which bl is read from B1 of B, a logical operation x1 is performed between al and bl, and the result cl is stored in C1 of C. That is, in order to perform a plurality of binary image logical operations, conventionally, the number of calculations required is equal to the number of operations.

(Problems to be Solved by the Invention) As described above, in the past, there has been a problem in that in order to perform a plurality of binary image logical operations, arithmetic steps corresponding to the number of operations are required.

The present invention has been made in view of the above circumstances, and its object is to provide a binary image logical operation system that can perform a plurality of binary image logical operations simultaneously.

[Structure of the invention] (Means and effects for solving the problem) This invention has n
A predetermined m number of first bit planes (m
A first bit plane of n bits in which a binary image is stored in each first bit plane (≦n), and a first bit plane of m pieces in the first bit plane consisting of n second bit planes. A binary image is stored in each of the m second bit planes that have the same bit positions as the planes.The n-bit second grayscale image memory stores the same bit positions in advance for all possible bit combinations of both stored data. A conversion table is provided in which the result of a predetermined logical operation is registered in advance in an entry specified by the connection information of the corresponding two stored data, and this conversion table is applied to any same pixel in the first and second grayscale image memories. By referring to the connection information of both stored data of the position and extracting the entry contents, m binary image logical operation results can be obtained simultaneously.

(Embodiment) FIG. 1 is a block diagram showing an embodiment of an image processing apparatus to which the present invention is applied. In the figure, 11 is a CPU L2A that controls the entire device.

12B and 12c are 8-bit grayscale image memories.

In this embodiment, the grayscale image memories 12A and 12B are used to store binary images to be subjected to logical operations (i.e., as input image memories), and the grayscale image memory 12C is used to store logical operation results (i.e., as output images). used as memory).

FIG. 2 shows the structure of the grayscale image memories 12A, 12B, and 12C. As shown in the figure, the grayscale image memory 12A
.

12B and 12c each have 8 bit planes 1
2A O~12A7, 128O~12B7, 12C
It consists of O~12C7. Bitplane 12AO, BO
.

CO designates the least significant bit (LSB) of the data stored in the grayscale image memories 12A, 12B, and 12C, and the bit planes 12A7, B7, and C7 similarly designate the most significant bit (MSB). In this example, bit planes 12AO, 12Al, 128O,
Bl is used to store a binary image to be subjected to logical operations, and bit planes 12CO and 12C1 are used to store results of logical operations.

Referring again to FIG. 1, 13 is a data conversion processor that performs logical operations between binary images.

The data conversion processor 13 includes a grayscale image memory 12A.
, 12B, the connection information (1
Translation table 1 addressed by 6 bits)
4 is provided. This conversion table 14 is used to register in advance the results of logical operations between bit brains (binary images stored in) that specify the same bit positions of the data stored in the grayscale image memories 12Δ and 12B. Consists of 8-bit memory. The data (8 bits) stored in the grayscale image memory 12A is the lower 8 bits (bits 8 to 7) including the least significant bit of the above-mentioned concatenated ↑h information.
The data (8 bits) stored in the grayscale image memory 12B are the upper 8 bits including the most significant bit of the above connected information.
(bits 8 to 15).

The grayscale image memories 12A to 12C and the data conversion processor 13 are connected to the CPU II via a control bus 15. Furthermore, the grayscale image memories 12A to 12C and the data conversion processor 13 are interconnected by an image bus IB.

Next, the operation of one embodiment of the present invention will be explained with reference to the operation diagram of FIG. 3 as appropriate.

Bit brain 12A0°12 of grayscale image memory 12A
Bit brain 1 of Al and grayscale image memory 121p
In this example, 2B0 and 1281 are used for binary image storage, the 8-bit stored data at the same pixel position in the grayscale image memories 12A and 12B is stored as "aO(LSB)al".
a2 a3 a4 a5 aOa7(MSB)","b
o (LSB)bl b2 b3b4 b5 be
b7 (MSB)', a2 to a7 and b
2 to b7 are all "0".

Now, binary logical operations xO and 2 between binary images aO and bO
Assuming that a binary logical operation X1 is performed between the value images al and b1 and the operation results CO and cl are stored in the grayscale image memory 12C, the CPU II performs the “aO
at 000000” and “bo bt ooooooo”
The operation of presetting 'co cl 000000'' in the entry of the conversion table 14 specified by the concatenated data with the grayscale image memories 12A and 12B is performed using all possible bit combinations (here, ANA
l.

Possible values of bo bt are 00, 01°10.
Since there are four combinations of 11, 4×4-16 combinations are executed. As a result, for example, ao-1,a
If xO and xi are AND (logical product operation) at t-1, bO-0, bl -1, co-0, c
Since it is l ml, “11000000” (
(lower address) and “01000000” (upper address) (i.e. 5
"01000000" is set in advance at address 15).

After completing the above-mentioned setting operation to the conversion table 14, the CPULI transfers the data to the grayscale image memory 12 via the control bus 15.
A, 12B, 12c and data conversion processor 1
3 to activate the binary image logical operation. As a result, reading is performed in the grayscale image memories 12A and 12B using the rask scan method, and the stored data "aOal 000000" at the same pixel position is read each time.

"bObl 000000" is simultaneously output onto the image bus 1B. The data conversion processor 13 includes an image bus 1
The data stored at the same pixel position in the grayscale image memories 12A and 12B output on B are taken in and concatenated as shown in FIG. 3, and the concatenated information is used as an address (entry address).
Refer to the conversion table 14 as follows. As described above, "co cl 000000" is preset (registered) at the address (entry) position in this conversion table 14. Therefore, the data conversion processor 13 stores data "aOaloooooo" and 'bObl 0000 at the same pixel position in the grayscale image memories 12A and 12B.
The conversion table 14 is referred to using the link information of "00" as an address (entry address), and the set (registered) content of the address (entry) position is "cOcl 000000
By performing a data conversion operation to extract ", the result co of the binary logical operation xO between the binary images aO and bo and the result C1 of the binary logical operation x1 between the binary images al and b1 are simultaneously obtained. That is, according to this embodiment, the binary logical operation xO between the binary images aO1bO and the binary logical operation x1 between the binary images at and b1 can be performed simultaneously. Now, the remaining 6 bits (b2 to b7) excluding the lower 2 bits bO and bl of the data stored in the grayscale image memory 12B are all MO" as described above.
It is. Therefore, the number of entries in the conversion table 14 is
210-1024, and the conversion table 14 is based on the stored data "ao al 00000" in the grayscale image memory 12A.
0” and the grayscale image memory 12 at the same pixel position as this data.
Linkage information (10 bits 5) with the lower 2 bits "bo bl" of the stored data "abOb1000000" of B.

The data conversion processor 13 refers to the conversion table 14 to obtain data “co” containing logical operation results cO, cl.
cl 000000", the data is sent onto the image bus IB. The data on this image bus 16,
That is, the data "cOcl 000000" obtained by referring to the conversion table 14 is the data "aOat 00000" from the grayscale image memories 12A and 12B.
0" and "bObl 000000" are stored in the storage area of the grayscale image memory 12c at the same pixel position as shown in FIG.

By repeating the above operations pixel by pixel using the rask scan method, the grayscale image memories 12A, 1
The operation result CO of the binary logical operation The operation result cl of the binary logical operation x1 between the value images al and b1 can be obtained in the grayscale image memory 12C for all pixels.

Although the case of two binary image logical operations has been described above, the present invention can also be applied to three or more binary image logical operations. For example, the grayscale image memories 12A and 12 in FIG.
B bit brain 12A O~12A3, 12BO
Binary images aO~a3゜bO~b3 are stored in ~12AB3, binary logical operations xO~x3 are performed between aO~a3 and bO~b3, and the results are stored in the grayscale image memory 1.
When storing in the bit brains 12cO to 12c3 of 2C, the CPU 11 stores 'ao al a2 a30
000" and 'bObl b2b3° connection information (12
The operation of presetting "co cl c2c30000" in the entry of the conversion table 14 specified by the grayscale image memory 12A and 12B is performed for all possible bit combinations of the data stored in both the grayscale image memories 12A and 12B. 12A, 12B, 12c and the data conversion processor 13 may be activated for binary image logic operation. Note that in this case, the required number of entries in the conversion table 14 is 212-4096, which is feasible.

[Effects of the Invention] As detailed above, according to the present invention, the conversion table is referred to based on the concatenation information of both stored data at the same pixel position of two grayscale image memories each storing a number of stages of binary images. By simply doing this, the results of multiple binary image operations can be obtained simultaneously.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram showing an embodiment of an image processing apparatus to which the present invention is applied, FIG. 2 is a diagram showing the configuration of the grayscale image memories 12A to 12c in FIG. 1, and FIG. 3 is an operation explanatory diagram. be. +1... CPU, 12A-12C... Grayscale image memory, 12A O to 12A7, 128O to 12B7
, 12CO~12C7...Bitbrain, 13.
...Data conversion processor, 14...Conversion table. Applicant's Representative Patent Attorney Takehiko Suzue 1st Prisoner 2nd. 17A(J(12BulZCOJFig. 3)

Claims (1)

[Claims] An n-bit first grayscale image memory consisting of n first bit planes, wherein each of predetermined m first bit planes (m≦n) among the n first bit planes has a binary value. a first grayscale image memory in which an image is stored; and a second grayscale image memory of n bits consisting of n second bit planes, which are identical to the m first bitplanes in the first grayscale image memory. A second grayscale image memory in which a binary image is stored in each of m second bit planes forming a bit position, and the same for all possible bit combinations of the data stored in both the first and second grayscale image memories. A conversion table is registered in advance in an entry specified by the concatenation information of the above-mentioned both stored data to which the result of a predetermined logical operation between bit positions corresponds, and this conversion table is stored in the above-mentioned first and second grayscale image memories. conversion table reference means for referencing both stored data at an arbitrary same pixel position based on concatenated information and extracting the entry contents; the conversion table reference means refers to the conversion table to convert m binary image logics; A binary image logical operation method characterized in that a calculation result is obtained.